Staging: comedi: remove C99 comments in s526.c
Signed-off-by: Bill Pemberton <wfp5p@virginia.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Bill Pemberton
Greg Kroah-Hartman
Родитель
58c0576eea
Коммит
232f650253
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@ -277,8 +277,8 @@ static int s526_attach(struct comedi_device * dev, struct comedi_devconfig * it)
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struct comedi_subdevice *s;
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int iobase;
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int i, n;
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// short value;
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// int subdev_channel = 0;
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/* short value; */
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/* int subdev_channel = 0; */
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printk("comedi%d: s526: ", dev->minor);
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@ -334,12 +334,12 @@ static int s526_attach(struct comedi_device * dev, struct comedi_devconfig * it)
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/* Command are not implemented yet, however they are necessary to
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allocate the necessary memory for the comedi_async struct (used
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to trigger the GPCT in case of pulsegenerator function */
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//s->do_cmd = s526_gpct_cmd;
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//s->do_cmdtest = s526_gpct_cmdtest;
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//s->cancel = s526_gpct_cancel;
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/* s->do_cmd = s526_gpct_cmd; */
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/* s->do_cmdtest = s526_gpct_cmdtest; */
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/* s->cancel = s526_gpct_cancel; */
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s = dev->subdevices + 1;
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//dev->read_subdev=s;
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/* dev->read_subdev=s; */
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/* analog input subdevice */
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s->type = COMEDI_SUBD_AI;
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/* we support differential */
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@ -383,18 +383,18 @@ static int s526_attach(struct comedi_device * dev, struct comedi_devconfig * it)
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return 1;
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#if 0
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// Example of Counter Application
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//One-shot (software trigger)
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cmReg.reg.coutSource = 0; // out RCAP
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cmReg.reg.coutPolarity = 1; // Polarity inverted
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cmReg.reg.autoLoadResetRcap = 1; // Auto load 0:disabled, 1:enabled
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cmReg.reg.hwCtEnableSource = 3; // NOT RCAP
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cmReg.reg.ctEnableCtrl = 2; // Hardware
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cmReg.reg.clockSource = 2; // Internal
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cmReg.reg.countDir = 1; // Down
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cmReg.reg.countDirCtrl = 1; // Software
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cmReg.reg.outputRegLatchCtrl = 0; // latch on read
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cmReg.reg.preloadRegSel = 0; // PR0
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/* Example of Counter Application */
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/* One-shot (software trigger) */
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cmReg.reg.coutSource = 0; /* out RCAP */
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cmReg.reg.coutPolarity = 1; /* Polarity inverted */
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cmReg.reg.autoLoadResetRcap = 1; /* Auto load 0:disabled, 1:enabled */
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cmReg.reg.hwCtEnableSource = 3; /* NOT RCAP */
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cmReg.reg.ctEnableCtrl = 2; /* Hardware */
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cmReg.reg.clockSource = 2; /* Internal */
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cmReg.reg.countDir = 1; /* Down */
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cmReg.reg.countDirCtrl = 1; /* Software */
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cmReg.reg.outputRegLatchCtrl = 0; /* latch on read */
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cmReg.reg.preloadRegSel = 0; /* PR0 */
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cmReg.reg.reserved = 0;
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outw(cmReg.value, ADDR_CHAN_REG(REG_C0M, subdev_channel));
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@ -402,24 +402,24 @@ static int s526_attach(struct comedi_device * dev, struct comedi_devconfig * it)
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outw(0x0001, ADDR_CHAN_REG(REG_C0H, subdev_channel));
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outw(0x3C68, ADDR_CHAN_REG(REG_C0L, subdev_channel));
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outw(0x8000, ADDR_CHAN_REG(REG_C0C, subdev_channel)); // Reset the counter
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outw(0x4000, ADDR_CHAN_REG(REG_C0C, subdev_channel)); // Load the counter from PR0
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outw(0x8000, ADDR_CHAN_REG(REG_C0C, subdev_channel)); /* Reset the counter */
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outw(0x4000, ADDR_CHAN_REG(REG_C0C, subdev_channel)); /* Load the counter from PR0 */
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outw(0x0008, ADDR_CHAN_REG(REG_C0C, subdev_channel)); // Reset RCAP (fires one-shot)
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outw(0x0008, ADDR_CHAN_REG(REG_C0C, subdev_channel)); /* Reset RCAP (fires one-shot) */
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#else
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// Set Counter Mode Register
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cmReg.reg.coutSource = 0; // out RCAP
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cmReg.reg.coutPolarity = 0; // Polarity inverted
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cmReg.reg.autoLoadResetRcap = 0; // Auto load disabled
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cmReg.reg.hwCtEnableSource = 2; // NOT RCAP
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cmReg.reg.ctEnableCtrl = 1; // 1: Software, >1 : Hardware
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cmReg.reg.clockSource = 3; // x4
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cmReg.reg.countDir = 0; // up
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cmReg.reg.countDirCtrl = 0; // quadrature
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cmReg.reg.outputRegLatchCtrl = 0; // latch on read
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cmReg.reg.preloadRegSel = 0; // PR0
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/* Set Counter Mode Register */
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cmReg.reg.coutSource = 0; /* out RCAP */
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cmReg.reg.coutPolarity = 0; /* Polarity inverted */
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cmReg.reg.autoLoadResetRcap = 0; /* Auto load disabled */
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cmReg.reg.hwCtEnableSource = 2; /* NOT RCAP */
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cmReg.reg.ctEnableCtrl = 1; /* 1: Software, >1 : Hardware */
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cmReg.reg.clockSource = 3; /* x4 */
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cmReg.reg.countDir = 0; /* up */
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cmReg.reg.countDirCtrl = 0; /* quadrature */
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cmReg.reg.outputRegLatchCtrl = 0; /* latch on read */
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cmReg.reg.preloadRegSel = 0; /* PR0 */
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cmReg.reg.reserved = 0;
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n = 0;
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@ -429,21 +429,21 @@ static int s526_attach(struct comedi_device * dev, struct comedi_devconfig * it)
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udelay(1000);
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printk("Read back mode reg=0x%04x\n", inw(ADDR_CHAN_REG(REG_C0M, n)));
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// Load the pre-laod register high word
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// value = (short) (0x55);
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// outw(value, ADDR_CHAN_REG(REG_C0H, n));
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/* Load the pre-laod register high word */
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/* value = (short) (0x55); */
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/* outw(value, ADDR_CHAN_REG(REG_C0H, n)); */
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// Load the pre-laod register low word
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// value = (short)(0xaa55);
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// outw(value, ADDR_CHAN_REG(REG_C0L, n));
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/* Load the pre-laod register low word */
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/* value = (short)(0xaa55); */
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/* outw(value, ADDR_CHAN_REG(REG_C0L, n)); */
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// Write the Counter Control Register
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// outw(value, ADDR_CHAN_REG(REG_C0C, 0));
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/* Write the Counter Control Register */
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/* outw(value, ADDR_CHAN_REG(REG_C0C, 0)); */
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// Reset the counter if it is software preload
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/* Reset the counter if it is software preload */
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if (cmReg.reg.autoLoadResetRcap == 0) {
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outw(0x8000, ADDR_CHAN_REG(REG_C0C, n)); // Reset the counter
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outw(0x4000, ADDR_CHAN_REG(REG_C0C, n)); // Load the counter from PR0
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outw(0x8000, ADDR_CHAN_REG(REG_C0C, n)); /* Reset the counter */
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outw(0x4000, ADDR_CHAN_REG(REG_C0C, n)); /* Load the counter from PR0 */
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}
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outw(cmReg.value, ADDR_CHAN_REG(REG_C0M, n));
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@ -481,23 +481,23 @@ static int s526_detach(struct comedi_device * dev)
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static int s526_gpct_rinsn(struct comedi_device * dev, struct comedi_subdevice * s,
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struct comedi_insn * insn, unsigned int * data)
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{
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int i; // counts the Data
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int i; /* counts the Data */
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int counter_channel = CR_CHAN(insn->chanspec);
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unsigned short datalow;
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unsigned short datahigh;
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// Check if (n > 0)
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/* Check if (n > 0) */
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if (insn->n <= 0) {
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printk("s526: INSN_READ: n should be > 0\n");
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return -EINVAL;
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}
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// Read the low word first
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/* Read the low word first */
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for (i = 0; i < insn->n; i++) {
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datalow = inw(ADDR_CHAN_REG(REG_C0L, counter_channel));
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datahigh = inw(ADDR_CHAN_REG(REG_C0H, counter_channel));
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data[i] = (int)(datahigh & 0x00FF);
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data[i] = (data[i] << 16) | (datalow & 0xFFFF);
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// printk("s526 GPCT[%d]: %x(0x%04x, 0x%04x)\n", counter_channel, data[i], datahigh, datalow);
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/* printk("s526 GPCT[%d]: %x(0x%04x, 0x%04x)\n", counter_channel, data[i], datahigh, datalow); */
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}
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return i;
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}
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@ -505,20 +505,20 @@ static int s526_gpct_rinsn(struct comedi_device * dev, struct comedi_subdevice *
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static int s526_gpct_insn_config(struct comedi_device * dev, struct comedi_subdevice * s,
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struct comedi_insn * insn, unsigned int * data)
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{
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int subdev_channel = CR_CHAN(insn->chanspec); // Unpack chanspec
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int subdev_channel = CR_CHAN(insn->chanspec); /* Unpack chanspec */
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int i;
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short value;
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// printk("s526: GPCT_INSN_CONFIG: Configuring Channel %d\n", subdev_channel);
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/* printk("s526: GPCT_INSN_CONFIG: Configuring Channel %d\n", subdev_channel); */
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for (i = 0; i < MAX_GPCT_CONFIG_DATA; i++) {
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devpriv->s526_gpct_config[subdev_channel].data[i] =
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insn->data[i];
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// printk("data[%d]=%x\n", i, insn->data[i]);
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/* printk("data[%d]=%x\n", i, insn->data[i]); */
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}
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// Check what type of Counter the user requested, data[0] contains
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// the Application type
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/* Check what type of Counter the user requested, data[0] contains */
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/* the Application type */
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switch (insn->data[0]) {
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case INSN_CONFIG_GPCT_QUADRATURE_ENCODER:
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/*
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@ -531,19 +531,19 @@ static int s526_gpct_insn_config(struct comedi_device * dev, struct comedi_subde
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devpriv->s526_gpct_config[subdev_channel].app =
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PositionMeasurement;
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/*
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// Example of Counter Application
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//One-shot (software trigger)
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cmReg.reg.coutSource = 0; // out RCAP
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cmReg.reg.coutPolarity = 1; // Polarity inverted
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cmReg.reg.autoLoadResetRcap = 0; // Auto load disabled
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cmReg.reg.hwCtEnableSource = 3; // NOT RCAP
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cmReg.reg.ctEnableCtrl = 2; // Hardware
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cmReg.reg.clockSource = 2; // Internal
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cmReg.reg.countDir = 1; // Down
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cmReg.reg.countDirCtrl = 1; // Software
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cmReg.reg.outputRegLatchCtrl = 0; // latch on read
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cmReg.reg.preloadRegSel = 0; // PR0
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#if 0
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/* Example of Counter Application */
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/* One-shot (software trigger) */
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cmReg.reg.coutSource = 0; /* out RCAP */
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cmReg.reg.coutPolarity = 1; /* Polarity inverted */
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cmReg.reg.autoLoadResetRcap = 0; /* Auto load disabled */
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cmReg.reg.hwCtEnableSource = 3; /* NOT RCAP */
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cmReg.reg.ctEnableCtrl = 2; /* Hardware */
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cmReg.reg.clockSource = 2; /* Internal */
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cmReg.reg.countDir = 1; /* Down */
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cmReg.reg.countDirCtrl = 1; /* Software */
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cmReg.reg.outputRegLatchCtrl = 0; /* latch on read */
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cmReg.reg.preloadRegSel = 0; /* PR0 */
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cmReg.reg.reserved = 0;
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outw(cmReg.value, ADDR_CHAN_REG(REG_C0M, subdev_channel));
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@ -551,40 +551,40 @@ static int s526_gpct_insn_config(struct comedi_device * dev, struct comedi_subde
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outw(0x0001, ADDR_CHAN_REG(REG_C0H, subdev_channel));
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outw(0x3C68, ADDR_CHAN_REG(REG_C0L, subdev_channel));
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outw(0x8000, ADDR_CHAN_REG(REG_C0C, subdev_channel)); // Reset the counter
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outw(0x4000, ADDR_CHAN_REG(REG_C0C, subdev_channel)); // Load the counter from PR0
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outw(0x8000, ADDR_CHAN_REG(REG_C0C, subdev_channel)); /* Reset the counter */
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outw(0x4000, ADDR_CHAN_REG(REG_C0C, subdev_channel)); /* Load the counter from PR0 */
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outw(0x0008, ADDR_CHAN_REG(REG_C0C, subdev_channel)); // Reset RCAP (fires one-shot)
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outw(0x0008, ADDR_CHAN_REG(REG_C0C, subdev_channel)); /* Reset RCAP (fires one-shot) */
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*/
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#endif
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#if 1
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// Set Counter Mode Register
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cmReg.reg.coutSource = 0; // out RCAP
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cmReg.reg.coutPolarity = 0; // Polarity inverted
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cmReg.reg.autoLoadResetRcap = 0; // Auto load disabled
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cmReg.reg.hwCtEnableSource = 2; // NOT RCAP
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cmReg.reg.ctEnableCtrl = 1; // 1: Software, >1 : Hardware
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cmReg.reg.clockSource = 3; // x4
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cmReg.reg.countDir = 0; // up
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cmReg.reg.countDirCtrl = 0; // quadrature
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cmReg.reg.outputRegLatchCtrl = 0; // latch on read
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cmReg.reg.preloadRegSel = 0; // PR0
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/* Set Counter Mode Register */
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cmReg.reg.coutSource = 0; /* out RCAP */
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cmReg.reg.coutPolarity = 0; /* Polarity inverted */
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cmReg.reg.autoLoadResetRcap = 0; /* Auto load disabled */
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cmReg.reg.hwCtEnableSource = 2; /* NOT RCAP */
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cmReg.reg.ctEnableCtrl = 1; /* 1: Software, >1 : Hardware */
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cmReg.reg.clockSource = 3; /* x4 */
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cmReg.reg.countDir = 0; /* up */
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cmReg.reg.countDirCtrl = 0; /* quadrature */
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cmReg.reg.outputRegLatchCtrl = 0; /* latch on read */
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cmReg.reg.preloadRegSel = 0; /* PR0 */
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cmReg.reg.reserved = 0;
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// Set Counter Mode Register
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// printk("s526: Counter Mode register=%x\n", cmReg.value);
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/* Set Counter Mode Register */
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/* printk("s526: Counter Mode register=%x\n", cmReg.value); */
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outw(cmReg.value, ADDR_CHAN_REG(REG_C0M, subdev_channel));
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// Reset the counter if it is software preload
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/* Reset the counter if it is software preload */
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if (cmReg.reg.autoLoadResetRcap == 0) {
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outw(0x8000, ADDR_CHAN_REG(REG_C0C, subdev_channel)); // Reset the counter
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// outw(0x4000, ADDR_CHAN_REG(REG_C0C, subdev_channel)); // Load the counter from PR0
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outw(0x8000, ADDR_CHAN_REG(REG_C0C, subdev_channel)); /* Reset the counter */
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/* outw(0x4000, ADDR_CHAN_REG(REG_C0C, subdev_channel)); Load the counter from PR0 */
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}
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#else
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cmReg.reg.countDirCtrl = 0; // 0 quadrature, 1 software control
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cmReg.reg.countDirCtrl = 0; /* 0 quadrature, 1 software control */
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// data[1] contains GPCT_X1, GPCT_X2 or GPCT_X4
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/* data[1] contains GPCT_X1, GPCT_X2 or GPCT_X4 */
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if (insn->data[1] == GPCT_X2) {
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cmReg.reg.clockSource = 1;
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} else if (insn->data[1] == GPCT_X4) {
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@ -593,37 +593,37 @@ static int s526_gpct_insn_config(struct comedi_device * dev, struct comedi_subde
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cmReg.reg.clockSource = 0;
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}
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// When to take into account the indexpulse:
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/* When to take into account the indexpulse: */
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if (insn->data[2] == GPCT_IndexPhaseLowLow) {
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} else if (insn->data[2] == GPCT_IndexPhaseLowHigh) {
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} else if (insn->data[2] == GPCT_IndexPhaseHighLow) {
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} else if (insn->data[2] == GPCT_IndexPhaseHighHigh) {
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}
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// Take into account the index pulse?
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/* Take into account the index pulse? */
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if (insn->data[3] == GPCT_RESET_COUNTER_ON_INDEX)
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cmReg.reg.autoLoadResetRcap = 4; // Auto load with INDEX^
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cmReg.reg.autoLoadResetRcap = 4; /* Auto load with INDEX^ */
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// Set Counter Mode Register
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/* Set Counter Mode Register */
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cmReg.value = (short) (insn->data[1] & 0xFFFF);
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outw(cmReg.value, ADDR_CHAN_REG(REG_C0M, subdev_channel));
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// Load the pre-laod register high word
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/* Load the pre-laod register high word */
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value = (short) ((insn->data[2] >> 16) & 0xFFFF);
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outw(value, ADDR_CHAN_REG(REG_C0H, subdev_channel));
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// Load the pre-laod register low word
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/* Load the pre-laod register low word */
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value = (short) (insn->data[2] & 0xFFFF);
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outw(value, ADDR_CHAN_REG(REG_C0L, subdev_channel));
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// Write the Counter Control Register
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/* Write the Counter Control Register */
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if (insn->data[3] != 0) {
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value = (short) (insn->data[3] & 0xFFFF);
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outw(value, ADDR_CHAN_REG(REG_C0C, subdev_channel));
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}
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// Reset the counter if it is software preload
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/* Reset the counter if it is software preload */
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if (cmReg.reg.autoLoadResetRcap == 0) {
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outw(0x8000, ADDR_CHAN_REG(REG_C0C, subdev_channel)); // Reset the counter
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outw(0x4000, ADDR_CHAN_REG(REG_C0C, subdev_channel)); // Load the counter from PR0
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outw(0x8000, ADDR_CHAN_REG(REG_C0C, subdev_channel)); /* Reset the counter */
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outw(0x4000, ADDR_CHAN_REG(REG_C0C, subdev_channel)); /* Load the counter from PR0 */
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}
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#endif
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break;
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@ -640,33 +640,33 @@ static int s526_gpct_insn_config(struct comedi_device * dev, struct comedi_subde
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devpriv->s526_gpct_config[subdev_channel].app =
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SinglePulseGeneration;
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// Set Counter Mode Register
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/* Set Counter Mode Register */
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cmReg.value = (short) (insn->data[1] & 0xFFFF);
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cmReg.reg.preloadRegSel = 0; // PR0
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cmReg.reg.preloadRegSel = 0; /* PR0 */
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outw(cmReg.value, ADDR_CHAN_REG(REG_C0M, subdev_channel));
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// Load the pre-laod register 0 high word
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/* Load the pre-laod register 0 high word */
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value = (short) ((insn->data[2] >> 16) & 0xFFFF);
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outw(value, ADDR_CHAN_REG(REG_C0H, subdev_channel));
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// Load the pre-laod register 0 low word
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/* Load the pre-laod register 0 low word */
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value = (short) (insn->data[2] & 0xFFFF);
|
||||
outw(value, ADDR_CHAN_REG(REG_C0L, subdev_channel));
|
||||
|
||||
// Set Counter Mode Register
|
||||
/* Set Counter Mode Register */
|
||||
cmReg.value = (short) (insn->data[1] & 0xFFFF);
|
||||
cmReg.reg.preloadRegSel = 1; // PR1
|
||||
cmReg.reg.preloadRegSel = 1; /* PR1 */
|
||||
outw(cmReg.value, ADDR_CHAN_REG(REG_C0M, subdev_channel));
|
||||
|
||||
// Load the pre-laod register 1 high word
|
||||
/* Load the pre-laod register 1 high word */
|
||||
value = (short) ((insn->data[3] >> 16) & 0xFFFF);
|
||||
outw(value, ADDR_CHAN_REG(REG_C0H, subdev_channel));
|
||||
|
||||
// Load the pre-laod register 1 low word
|
||||
/* Load the pre-laod register 1 low word */
|
||||
value = (short) (insn->data[3] & 0xFFFF);
|
||||
outw(value, ADDR_CHAN_REG(REG_C0L, subdev_channel));
|
||||
|
||||
// Write the Counter Control Register
|
||||
/* Write the Counter Control Register */
|
||||
if (insn->data[3] != 0) {
|
||||
value = (short) (insn->data[3] & 0xFFFF);
|
||||
outw(value, ADDR_CHAN_REG(REG_C0C, subdev_channel));
|
||||
|
|
@ -685,33 +685,33 @@ static int s526_gpct_insn_config(struct comedi_device * dev, struct comedi_subde
|
|||
devpriv->s526_gpct_config[subdev_channel].app =
|
||||
PulseTrainGeneration;
|
||||
|
||||
// Set Counter Mode Register
|
||||
/* Set Counter Mode Register */
|
||||
cmReg.value = (short) (insn->data[1] & 0xFFFF);
|
||||
cmReg.reg.preloadRegSel = 0; // PR0
|
||||
cmReg.reg.preloadRegSel = 0; /* PR0 */
|
||||
outw(cmReg.value, ADDR_CHAN_REG(REG_C0M, subdev_channel));
|
||||
|
||||
// Load the pre-laod register 0 high word
|
||||
/* Load the pre-laod register 0 high word */
|
||||
value = (short) ((insn->data[2] >> 16) & 0xFFFF);
|
||||
outw(value, ADDR_CHAN_REG(REG_C0H, subdev_channel));
|
||||
|
||||
// Load the pre-laod register 0 low word
|
||||
/* Load the pre-laod register 0 low word */
|
||||
value = (short) (insn->data[2] & 0xFFFF);
|
||||
outw(value, ADDR_CHAN_REG(REG_C0L, subdev_channel));
|
||||
|
||||
// Set Counter Mode Register
|
||||
/* Set Counter Mode Register */
|
||||
cmReg.value = (short) (insn->data[1] & 0xFFFF);
|
||||
cmReg.reg.preloadRegSel = 1; // PR1
|
||||
cmReg.reg.preloadRegSel = 1; /* PR1 */
|
||||
outw(cmReg.value, ADDR_CHAN_REG(REG_C0M, subdev_channel));
|
||||
|
||||
// Load the pre-laod register 1 high word
|
||||
/* Load the pre-laod register 1 high word */
|
||||
value = (short) ((insn->data[3] >> 16) & 0xFFFF);
|
||||
outw(value, ADDR_CHAN_REG(REG_C0H, subdev_channel));
|
||||
|
||||
// Load the pre-laod register 1 low word
|
||||
/* Load the pre-laod register 1 low word */
|
||||
value = (short) (insn->data[3] & 0xFFFF);
|
||||
outw(value, ADDR_CHAN_REG(REG_C0L, subdev_channel));
|
||||
|
||||
// Write the Counter Control Register
|
||||
/* Write the Counter Control Register */
|
||||
if (insn->data[3] != 0) {
|
||||
value = (short) (insn->data[3] & 0xFFFF);
|
||||
outw(value, ADDR_CHAN_REG(REG_C0C, subdev_channel));
|
||||
|
|
@ -730,13 +730,13 @@ static int s526_gpct_insn_config(struct comedi_device * dev, struct comedi_subde
|
|||
static int s526_gpct_winsn(struct comedi_device * dev, struct comedi_subdevice * s,
|
||||
struct comedi_insn * insn, unsigned int * data)
|
||||
{
|
||||
int subdev_channel = CR_CHAN(insn->chanspec); // Unpack chanspec
|
||||
int subdev_channel = CR_CHAN(insn->chanspec); /* Unpack chanspec */
|
||||
short value;
|
||||
|
||||
printk("s526: GPCT_INSN_WRITE on channel %d\n", subdev_channel);
|
||||
cmReg.value = inw(ADDR_CHAN_REG(REG_C0M, subdev_channel));
|
||||
printk("s526: Counter Mode Register: %x\n", cmReg.value);
|
||||
// Check what Application of Counter this channel is configured for
|
||||
/* Check what Application of Counter this channel is configured for */
|
||||
switch (devpriv->s526_gpct_config[subdev_channel].app) {
|
||||
case PositionMeasurement:
|
||||
printk("S526: INSN_WRITE: PM\n");
|
||||
|
|
@ -776,12 +776,12 @@ static int s526_gpct_winsn(struct comedi_device * dev, struct comedi_subdevice *
|
|||
value = (short) (*data & 0xFFFF);
|
||||
outw(value, ADDR_CHAN_REG(REG_C0L, subdev_channel));
|
||||
break;
|
||||
default: // Impossible
|
||||
default: /* Impossible */
|
||||
printk("s526: INSN_WRITE: Functionality %d not implemented yet\n", devpriv->s526_gpct_config[subdev_channel].app);
|
||||
return -EINVAL;
|
||||
break;
|
||||
}
|
||||
// return the number of samples written
|
||||
/* return the number of samples written */
|
||||
return insn->n;
|
||||
}
|
||||
|
||||
|
|
@ -803,14 +803,14 @@ static int s526_ai_insn_config(struct comedi_device * dev, struct comedi_subdevi
|
|||
* enable channels here. The channel should be enabled in the
|
||||
* INSN_READ handler. */
|
||||
|
||||
// Enable ADC interrupt
|
||||
/* Enable ADC interrupt */
|
||||
outw(ISR_ADC_DONE, ADDR_REG(REG_IER));
|
||||
// printk("s526: ADC current value: 0x%04x\n", inw(ADDR_REG(REG_ADC)));
|
||||
/* printk("s526: ADC current value: 0x%04x\n", inw(ADDR_REG(REG_ADC))); */
|
||||
devpriv->s526_ai_config = (data[0] & 0x3FF) << 5;
|
||||
if (data[1] > 0)
|
||||
devpriv->s526_ai_config |= 0x8000; //set the delay
|
||||
devpriv->s526_ai_config |= 0x8000; /* set the delay */
|
||||
|
||||
devpriv->s526_ai_config |= 0x0001; // ADC start bit.
|
||||
devpriv->s526_ai_config |= 0x0001; /* ADC start bit. */
|
||||
|
||||
return result;
|
||||
}
|
||||
|
|
@ -837,8 +837,8 @@ static int s526_ai_rinsn(struct comedi_device * dev, struct comedi_subdevice * s
|
|||
for (n = 0; n < insn->n; n++) {
|
||||
/* trigger conversion */
|
||||
outw(value, ADDR_REG(REG_ADC));
|
||||
// printk("s526: Wrote 0x%04x to ADC\n", value);
|
||||
// printk("s526: ADC reg=0x%04x\n", inw(ADDR_REG(REG_ADC)));
|
||||
/* printk("s526: Wrote 0x%04x to ADC\n", value); */
|
||||
/* printk("s526: ADC reg=0x%04x\n", inw(ADDR_REG(REG_ADC))); */
|
||||
|
||||
#define TIMEOUT 100
|
||||
/* wait for conversion to end */
|
||||
|
|
@ -859,7 +859,7 @@ static int s526_ai_rinsn(struct comedi_device * dev, struct comedi_subdevice * s
|
|||
|
||||
/* read data */
|
||||
d = inw(ADDR_REG(REG_ADD));
|
||||
// printk("AI[%d]=0x%04x\n", n, (unsigned short)(d & 0xFFFF));
|
||||
/* printk("AI[%d]=0x%04x\n", n, (unsigned short)(d & 0xFFFF)); */
|
||||
|
||||
/* munge data */
|
||||
data[n] = d ^ 0x8000;
|
||||
|
|
@ -876,20 +876,20 @@ static int s526_ao_winsn(struct comedi_device * dev, struct comedi_subdevice * s
|
|||
int chan = CR_CHAN(insn->chanspec);
|
||||
unsigned short val;
|
||||
|
||||
// printk("s526_ao_winsn\n");
|
||||
/* printk("s526_ao_winsn\n"); */
|
||||
val = chan << 1;
|
||||
// outw(val, dev->iobase + REG_DAC);
|
||||
/* outw(val, dev->iobase + REG_DAC); */
|
||||
outw(val, ADDR_REG(REG_DAC));
|
||||
|
||||
/* Writing a list of values to an AO channel is probably not
|
||||
* very useful, but that's how the interface is defined. */
|
||||
for (i = 0; i < insn->n; i++) {
|
||||
/* a typical programming sequence */
|
||||
// outw(data[i], dev->iobase + REG_ADD); // write the data to preload register
|
||||
outw(data[i], ADDR_REG(REG_ADD)); // write the data to preload register
|
||||
/* outw(data[i], dev->iobase + REG_ADD); write the data to preload register */
|
||||
outw(data[i], ADDR_REG(REG_ADD)); /* write the data to preload register */
|
||||
devpriv->ao_readback[chan] = data[i];
|
||||
// outw(val + 1, dev->iobase + REG_DAC); // starts the D/A conversion.
|
||||
outw(val + 1, ADDR_REG(REG_DAC)); // starts the D/A conversion.
|
||||
/* outw(val + 1, dev->iobase + REG_DAC); starts the D/A conversion. */
|
||||
outw(val + 1, ADDR_REG(REG_DAC)); /* starts the D/A conversion. */
|
||||
}
|
||||
|
||||
/* return the number of samples read/written */
|
||||
|
|
@ -932,10 +932,10 @@ static int s526_dio_insn_bits(struct comedi_device * dev, struct comedi_subdevic
|
|||
|
||||
/* on return, data[1] contains the value of the digital
|
||||
* input and output lines. */
|
||||
data[1] = inw(ADDR_REG(REG_DIO)) & 0xFF; // low 8 bits are the data
|
||||
data[1] = inw(ADDR_REG(REG_DIO)) & 0xFF; /* low 8 bits are the data */
|
||||
/* or we could just return the software copy of the output values if
|
||||
* it was a purely digital output subdevice */
|
||||
//data[1]=s->state;
|
||||
/* data[1]=s->state; */
|
||||
|
||||
return 2;
|
||||
}
|
||||
|
|
@ -959,10 +959,10 @@ static int s526_dio_insn_config(struct comedi_device * dev, struct comedi_subdev
|
|||
* value COMEDI_INPUT or COMEDI_OUTPUT. */
|
||||
|
||||
if (data[0] == COMEDI_OUTPUT) {
|
||||
value |= 1 << (chan + 10); // bit 10/11 set the group 1/2's mode
|
||||
value |= 1 << (chan + 10); /* bit 10/11 set the group 1/2's mode */
|
||||
s->io_bits |= (0xF << chan);
|
||||
} else {
|
||||
value &= ~(1 << (chan + 10)); // 1 is output, 0 is input.
|
||||
value &= ~(1 << (chan + 10)); /* 1 is output, 0 is input. */
|
||||
s->io_bits &= ~(0xF << chan);
|
||||
}
|
||||
outw(value, ADDR_REG(REG_DIO));
|
||||
|
|
|
|||
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