From e39942f527fb02b73236d872d22c1b6b8335266c Mon Sep 17 00:00:00 2001 From: Alexandre Pereira da Silva Date: Fri, 20 Jul 2012 14:01:51 +0200 Subject: [PATCH 1/3] ARM: LPC32xx: Set system serial based on cpu unique id LPC32xx SoC has a 128 bits unique id that can be used as a system serial number, if none has been provided by atags or dt. Signed-off-by: Alexandre Pereira da Silva Signed-off-by: Roland Stigge --- arch/arm/mach-lpc32xx/common.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c index 5c96057b6d78..a48dc2dec485 100644 --- a/arch/arm/mach-lpc32xx/common.c +++ b/arch/arm/mach-lpc32xx/common.c @@ -26,6 +26,7 @@ #include #include +#include #include #include @@ -224,7 +225,7 @@ void lpc23xx_restart(char mode, const char *cmd) ; } -static int __init lpc32xx_display_uid(void) +static int __init lpc32xx_check_uid(void) { u32 uid[4]; @@ -233,6 +234,11 @@ static int __init lpc32xx_display_uid(void) printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n", uid[3], uid[2], uid[1], uid[0]); + if (!system_serial_low && !system_serial_high) { + system_serial_low = uid[0]; + system_serial_high = uid[1]; + } + return 1; } -arch_initcall(lpc32xx_display_uid); +arch_initcall(lpc32xx_check_uid); From 1f37a3a32b86c443396293b1f9d3e23b0a0344e5 Mon Sep 17 00:00:00 2001 From: Alexandre Pereira da Silva Date: Fri, 20 Jul 2012 14:01:51 +0200 Subject: [PATCH 2/3] ARM: LPC32xx: Add PWM clock Signed-off-by: Alexandre Pereira da Silva Signed-off-by: Roland Stigge --- arch/arm/mach-lpc32xx/clock.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c index 8a4e7cb74ae1..f48c2e961b84 100644 --- a/arch/arm/mach-lpc32xx/clock.c +++ b/arch/arm/mach-lpc32xx/clock.c @@ -607,6 +607,19 @@ static struct clk clk_dma = { .get_rate = local_return_parent_rate, }; +static struct clk clk_pwm = { + .parent = &clk_pclk, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_PWM_CLK_CTRL, + .enable_mask = LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN | + LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK | + LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(1) | + LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN | + LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK | + LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(1), + .get_rate = local_return_parent_rate, +}; + static struct clk clk_uart3 = { .parent = &clk_pclk, .enable = local_onoff_enable, @@ -1188,6 +1201,7 @@ static struct clk_lookup lookups[] = { CLKDEV_INIT(NULL, "vfp9_ck", &clk_vfp9), CLKDEV_INIT("pl08xdmac", NULL, &clk_dma), CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt), + CLKDEV_INIT("4005c000.pwm", NULL, &clk_pwm), CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3), CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4), CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5), From c49a18308669a7c1bd61ddd4f575a88d49b0b852 Mon Sep 17 00:00:00 2001 From: Alexandre Pereira da Silva Date: Fri, 20 Jul 2012 14:01:51 +0200 Subject: [PATCH 3/3] ARM: LPC32xx: Add PWM support This SoC has two PWM channels Signed-off-by: Alexandre Pereira da Silva Signed-off-by: Roland Stigge --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 973d5380a431..ef4c66f13c15 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -566,6 +566,7 @@ config ARCH_LPC32XX select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS select USE_OF + select HAVE_PWM help Support for the NXP LPC32XX family of processors