gpio: omap: protect regs access in omap_gpio_irq_handler
The access to HW registers has to be be protected in omap_gpio_irq_handler(), as it may race with code executed on another CPUs. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Tested-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -718,6 +718,7 @@ static void omap_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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int unmasked = 0;
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struct irq_chip *irqchip = irq_desc_get_chip(desc);
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struct gpio_chip *chip = irq_desc_get_handler_data(desc);
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unsigned long lock_flags;
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chained_irq_enter(irqchip, desc);
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@ -732,6 +733,8 @@ static void omap_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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u32 isr_saved, level_mask = 0;
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u32 enabled;
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raw_spin_lock_irqsave(&bank->lock, lock_flags);
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enabled = omap_get_gpio_irqbank_mask(bank);
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isr_saved = isr = readl_relaxed(isr_reg) & enabled;
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@ -745,6 +748,8 @@ static void omap_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
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omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask);
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raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
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/* if there is only edge sensitive GPIO pin interrupts
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configured, we could unmask GPIO bank interrupt immediately */
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if (!level_mask && !unmasked) {
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@ -759,6 +764,7 @@ static void omap_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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bit = __ffs(isr);
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isr &= ~(BIT(bit));
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raw_spin_lock_irqsave(&bank->lock, lock_flags);
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/*
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* Some chips can't respond to both rising and falling
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* at the same time. If this irq was requested with
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@ -769,6 +775,8 @@ static void omap_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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if (bank->toggle_mask & (BIT(bit)))
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omap_toggle_gpio_edge_triggering(bank, bit);
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raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
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generic_handle_irq(irq_find_mapping(bank->chip.irqdomain,
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bit));
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}
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