A three-set which makes the APIC LVT interrupt optional because a subset
of F15h models don't support it. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJPno0hAAoJEBLB8Bhh3lVKSJkP+gJTnMUOTzLgW47zuo/aadkk r8YxPWZ135Lijvv7fdB7TijT0X9W4v1oIwjzQPcULW88Oig63eo2O+TocYEANq4A Vj4CaLePGTPZ4tX7KT/qaafelyp58lx/FOJWDshhvvnCT6UqfhYlX+9Coj+SGPaA 97PlDGWvMoVlpTQouurQjUqs2NQYelnw4eEPpAP0b1zi+DE2W0DuAcYE1cc44qqy GNJZr9ZdFZ7mdoDO0gcZp/WQVeDD7fCId2nrvi0wGRFoS+oXr8jbyNHGhrHu84DW cgr+OuHQXuNe+ZhRA3PpqCWIFdp9jT3/zDKR0NCDn2PdBmzLdpTDq8ZmXHQhEjHn gGH2pOVqgQbT9+2Tt1pzqjIG8iNMoj5C3WCoVPZ2TD+EHWv0Ao2MNyS3UGmE8EOu tplKu24mf1J+1SmuDcncyHGrU5KWE9p1WbM4YpSAiTFnz7Qs1GJzHmJOK4j2jK0O 2IqPlPPsFSPMrU2JX7wjsmvoAIg4Q1FAjev8y1+bfcZW14YrcLMzBbmIgedb7zef nVnpCfaSa+bXJ8i2lh12+CKBZEfefU4aMOwPKWwe4ZwTzd1JVThfLhi0e2b76KZj ut2mez9iIXp9RrmUwj2L+hqT3McXgDqWG6OS8Or/wzGP5XIkCeHpMYuN9iF8jlfQ vhHVzbeALV7rpovpxQhu =WJEO -----END PGP SIGNATURE----- Merge tag 'amd-thresholding-fixes-for-3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras into x86/mce - make the APIC LVT interrupt optional because a subset of AMD F15h models don't support it. Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Ingo Molnar
Коммит
239e7bad43
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@ -1423,6 +1423,43 @@ static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
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*/
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if (c->x86 == 6 && banks > 0)
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mce_banks[0].ctl = 0;
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/*
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* Turn off MC4_MISC thresholding banks on those models since
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* they're not supported there.
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*/
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if (c->x86 == 0x15 &&
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(c->x86_model >= 0x10 && c->x86_model <= 0x1f)) {
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int i;
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u64 val, hwcr;
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bool need_toggle;
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u32 msrs[] = {
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0x00000413, /* MC4_MISC0 */
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0xc0000408, /* MC4_MISC1 */
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};
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rdmsrl(MSR_K7_HWCR, hwcr);
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/* McStatusWrEn has to be set */
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need_toggle = !(hwcr & BIT(18));
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if (need_toggle)
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wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
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for (i = 0; i < ARRAY_SIZE(msrs); i++) {
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rdmsrl(msrs[i], val);
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/* CntP bit set? */
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if (val & BIT(62)) {
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val &= ~BIT(62);
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wrmsrl(msrs[i], val);
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}
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}
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/* restore old settings */
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if (need_toggle)
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wrmsrl(MSR_K7_HWCR, hwcr);
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}
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}
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if (c->x86_vendor == X86_VENDOR_INTEL) {
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@ -51,6 +51,7 @@ struct threshold_block {
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unsigned int cpu;
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u32 address;
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u16 interrupt_enable;
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bool interrupt_capable;
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u16 threshold_limit;
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struct kobject kobj;
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struct list_head miscj;
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@ -83,6 +84,21 @@ struct thresh_restart {
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u16 old_limit;
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};
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static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)
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{
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/*
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* bank 4 supports APIC LVT interrupts implicitly since forever.
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*/
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if (bank == 4)
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return true;
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/*
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* IntP: interrupt present; if this bit is set, the thresholding
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* bank can generate APIC LVT interrupts
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*/
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return msr_high_bits & BIT(28);
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}
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static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
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{
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int msr = (hi & MASK_LVTOFF_HI) >> 20;
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@ -104,8 +120,10 @@ static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
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return 1;
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};
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/* must be called with correct cpu affinity */
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/* Called via smp_call_function_single() */
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/*
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* Called via smp_call_function_single(), must be called with correct
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* cpu affinity.
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*/
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static void threshold_restart_bank(void *_tr)
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{
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struct thresh_restart *tr = _tr;
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@ -128,6 +146,12 @@ static void threshold_restart_bank(void *_tr)
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(new_count & THRESHOLD_MAX);
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}
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/* clear IntType */
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hi &= ~MASK_INT_TYPE_HI;
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if (!tr->b->interrupt_capable)
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goto done;
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if (tr->set_lvt_off) {
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if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
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/* set new lvt offset */
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@ -136,9 +160,10 @@ static void threshold_restart_bank(void *_tr)
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}
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}
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tr->b->interrupt_enable ?
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(hi = (hi & ~MASK_INT_TYPE_HI) | INT_TYPE_APIC) :
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(hi &= ~MASK_INT_TYPE_HI);
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if (tr->b->interrupt_enable)
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hi |= INT_TYPE_APIC;
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done:
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hi |= MASK_COUNT_EN_HI;
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wrmsr(tr->b->address, lo, hi);
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@ -202,14 +227,17 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
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if (shared_bank[bank] && c->cpu_core_id)
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break;
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offset = setup_APIC_mce(offset,
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(high & MASK_LVTOFF_HI) >> 20);
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memset(&b, 0, sizeof(b));
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b.cpu = cpu;
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b.bank = bank;
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b.block = block;
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b.address = address;
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b.cpu = cpu;
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b.bank = bank;
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b.block = block;
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b.address = address;
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b.interrupt_capable = lvt_interrupt_supported(bank, high);
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if (b.interrupt_capable) {
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int new = (high & MASK_LVTOFF_HI) >> 20;
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offset = setup_APIC_mce(offset, new);
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}
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mce_threshold_block_init(&b, offset);
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mce_threshold_vector = amd_threshold_interrupt;
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@ -309,6 +337,9 @@ store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
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struct thresh_restart tr;
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unsigned long new;
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if (!b->interrupt_capable)
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return -EINVAL;
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if (strict_strtoul(buf, 0, &new) < 0)
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return -EINVAL;
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@ -390,10 +421,10 @@ RW_ATTR(threshold_limit);
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RW_ATTR(error_count);
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static struct attribute *default_attrs[] = {
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&interrupt_enable.attr,
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&threshold_limit.attr,
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&error_count.attr,
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NULL
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NULL, /* possibly interrupt_enable if supported, see below */
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NULL,
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};
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#define to_block(k) container_of(k, struct threshold_block, kobj)
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@ -467,8 +498,14 @@ static __cpuinit int allocate_threshold_blocks(unsigned int cpu,
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b->cpu = cpu;
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b->address = address;
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b->interrupt_enable = 0;
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b->interrupt_capable = lvt_interrupt_supported(bank, high);
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b->threshold_limit = THRESHOLD_MAX;
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if (b->interrupt_capable)
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threshold_ktype.default_attrs[2] = &interrupt_enable.attr;
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else
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threshold_ktype.default_attrs[2] = NULL;
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INIT_LIST_HEAD(&b->miscj);
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if (per_cpu(threshold_banks, cpu)[bank]->blocks) {
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