Documentation: riscv: Remove the old documentation
The existing pmu documentation describes the limitation of perf infrastructure in RISC-V ISA and limited feature set of perf in RISC-V. However, SBI PMU extension and sscofpmf extension(ISA extension) allows to implement most of the required features of perf. Remove the old documentation which is not accurate anymore. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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Atish Patra
Palmer Dabbelt
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===================================
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Supporting PMUs on RISC-V platforms
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===================================
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Alan Kao <alankao@andestech.com>, Mar 2018
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Introduction
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------------
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As of this writing, perf_event-related features mentioned in The RISC-V ISA
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Privileged Version 1.10 are as follows:
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(please check the manual for more details)
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* [m|s]counteren
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* mcycle[h], cycle[h]
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* minstret[h], instret[h]
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* mhpeventx, mhpcounterx[h]
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With such function set only, porting perf would require a lot of work, due to
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the lack of the following general architectural performance monitoring features:
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* Enabling/Disabling counters
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Counters are just free-running all the time in our case.
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* Interrupt caused by counter overflow
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No such feature in the spec.
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* Interrupt indicator
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It is not possible to have many interrupt ports for all counters, so an
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interrupt indicator is required for software to tell which counter has
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just overflowed.
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* Writing to counters
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There will be an SBI to support this since the kernel cannot modify the
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counters [1]. Alternatively, some vendor considers to implement
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hardware-extension for M-S-U model machines to write counters directly.
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This document aims to provide developers a quick guide on supporting their
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PMUs in the kernel. The following sections briefly explain perf' mechanism
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and todos.
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You may check previous discussions here [1][2]. Also, it might be helpful
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to check the appendix for related kernel structures.
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1. Initialization
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-----------------
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*riscv_pmu* is a global pointer of type *struct riscv_pmu*, which contains
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various methods according to perf's internal convention and PMU-specific
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parameters. One should declare such instance to represent the PMU. By default,
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*riscv_pmu* points to a constant structure *riscv_base_pmu*, which has very
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basic support to a baseline QEMU model.
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Then he/she can either assign the instance's pointer to *riscv_pmu* so that
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the minimal and already-implemented logic can be leveraged, or invent his/her
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own *riscv_init_platform_pmu* implementation.
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In other words, existing sources of *riscv_base_pmu* merely provide a
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reference implementation. Developers can flexibly decide how many parts they
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can leverage, and in the most extreme case, they can customize every function
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according to their needs.
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2. Event Initialization
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-----------------------
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When a user launches a perf command to monitor some events, it is first
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interpreted by the userspace perf tool into multiple *perf_event_open*
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system calls, and then each of them calls to the body of *event_init*
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member function that was assigned in the previous step. In *riscv_base_pmu*'s
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case, it is *riscv_event_init*.
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The main purpose of this function is to translate the event provided by user
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into bitmap, so that HW-related control registers or counters can directly be
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manipulated. The translation is based on the mappings and methods provided in
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*riscv_pmu*.
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Note that some features can be done in this stage as well:
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(1) interrupt setting, which is stated in the next section;
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(2) privilege level setting (user space only, kernel space only, both);
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(3) destructor setting. Normally it is sufficient to apply *riscv_destroy_event*;
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(4) tweaks for non-sampling events, which will be utilized by functions such as
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*perf_adjust_period*, usually something like the follows::
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if (!is_sampling_event(event)) {
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hwc->sample_period = x86_pmu.max_period;
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hwc->last_period = hwc->sample_period;
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local64_set(&hwc->period_left, hwc->sample_period);
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}
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In the case of *riscv_base_pmu*, only (3) is provided for now.
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3. Interrupt
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------------
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3.1. Interrupt Initialization
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This often occurs at the beginning of the *event_init* method. In common
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practice, this should be a code segment like::
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int x86_reserve_hardware(void)
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{
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int err = 0;
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if (!atomic_inc_not_zero(&pmc_refcount)) {
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mutex_lock(&pmc_reserve_mutex);
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if (atomic_read(&pmc_refcount) == 0) {
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if (!reserve_pmc_hardware())
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err = -EBUSY;
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else
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reserve_ds_buffers();
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}
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if (!err)
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atomic_inc(&pmc_refcount);
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mutex_unlock(&pmc_reserve_mutex);
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}
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return err;
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}
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And the magic is in *reserve_pmc_hardware*, which usually does atomic
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operations to make implemented IRQ accessible from some global function pointer.
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*release_pmc_hardware* serves the opposite purpose, and it is used in event
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destructors mentioned in previous section.
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(Note: From the implementations in all the architectures, the *reserve/release*
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pair are always IRQ settings, so the *pmc_hardware* seems somehow misleading.
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It does NOT deal with the binding between an event and a physical counter,
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which will be introduced in the next section.)
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3.2. IRQ Structure
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Basically, a IRQ runs the following pseudo code::
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for each hardware counter that triggered this overflow
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get the event of this counter
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// following two steps are defined as *read()*,
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// check the section Reading/Writing Counters for details.
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count the delta value since previous interrupt
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update the event->count (# event occurs) by adding delta, and
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event->hw.period_left by subtracting delta
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if the event overflows
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sample data
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set the counter appropriately for the next overflow
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if the event overflows again
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too frequently, throttle this event
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fi
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fi
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end for
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However as of this writing, none of the RISC-V implementations have designed an
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interrupt for perf, so the details are to be completed in the future.
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4. Reading/Writing Counters
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---------------------------
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They seem symmetric but perf treats them quite differently. For reading, there
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is a *read* interface in *struct pmu*, but it serves more than just reading.
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According to the context, the *read* function not only reads the content of the
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counter (event->count), but also updates the left period to the next interrupt
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(event->hw.period_left).
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But the core of perf does not need direct write to counters. Writing counters
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is hidden behind the abstraction of 1) *pmu->start*, literally start counting so one
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has to set the counter to a good value for the next interrupt; 2) inside the IRQ
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it should set the counter to the same resonable value.
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Reading is not a problem in RISC-V but writing would need some effort, since
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counters are not allowed to be written by S-mode.
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5. add()/del()/start()/stop()
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-----------------------------
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Basic idea: add()/del() adds/deletes events to/from a PMU, and start()/stop()
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starts/stop the counter of some event in the PMU. All of them take the same
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arguments: *struct perf_event *event* and *int flag*.
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Consider perf as a state machine, then you will find that these functions serve
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as the state transition process between those states.
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Three states (event->hw.state) are defined:
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* PERF_HES_STOPPED: the counter is stopped
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* PERF_HES_UPTODATE: the event->count is up-to-date
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* PERF_HES_ARCH: arch-dependent usage ... we don't need this for now
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A normal flow of these state transitions are as follows:
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* A user launches a perf event, resulting in calling to *event_init*.
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* When being context-switched in, *add* is called by the perf core, with a flag
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PERF_EF_START, which means that the event should be started after it is added.
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At this stage, a general event is bound to a physical counter, if any.
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The state changes to PERF_HES_STOPPED and PERF_HES_UPTODATE, because it is now
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stopped, and the (software) event count does not need updating.
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- *start* is then called, and the counter is enabled.
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With flag PERF_EF_RELOAD, it writes an appropriate value to the counter (check
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previous section for detail).
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Nothing is written if the flag does not contain PERF_EF_RELOAD.
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The state now is reset to none, because it is neither stopped nor updated
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(the counting already started)
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* When being context-switched out, *del* is called. It then checks out all the
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events in the PMU and calls *stop* to update their counts.
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- *stop* is called by *del*
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and the perf core with flag PERF_EF_UPDATE, and it often shares the same
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subroutine as *read* with the same logic.
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The state changes to PERF_HES_STOPPED and PERF_HES_UPTODATE, again.
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- Life cycle of these two pairs: *add* and *del* are called repeatedly as
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tasks switch in-and-out; *start* and *stop* is also called when the perf core
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needs a quick stop-and-start, for instance, when the interrupt period is being
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adjusted.
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Current implementation is sufficient for now and can be easily extended to
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features in the future.
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A. Related Structures
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---------------------
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* struct pmu: include/linux/perf_event.h
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* struct riscv_pmu: arch/riscv/include/asm/perf_event.h
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Both structures are designed to be read-only.
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*struct pmu* defines some function pointer interfaces, and most of them take
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*struct perf_event* as a main argument, dealing with perf events according to
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perf's internal state machine (check kernel/events/core.c for details).
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*struct riscv_pmu* defines PMU-specific parameters. The naming follows the
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convention of all other architectures.
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* struct perf_event: include/linux/perf_event.h
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* struct hw_perf_event
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The generic structure that represents perf events, and the hardware-related
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details.
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* struct riscv_hw_events: arch/riscv/include/asm/perf_event.h
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The structure that holds the status of events, has two fixed members:
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the number of events and the array of the events.
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References
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----------
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[1] https://github.com/riscv/riscv-linux/pull/124
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[2] https://groups.google.com/a/groups.riscv.org/forum/#!topic/sw-dev/f19TmCNP6yA
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