[media] Staging: media: solo6x10: core.c Fix some coding style issue
Replaced spaces with tabs Signed-off-by: Andrew Miller <amiller@amilx.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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68a6bb5465
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@ -195,28 +195,28 @@ static int __devinit solo_pci_probe(struct pci_dev *pdev,
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SOLO6010_SYS_CFG_OUTDIV(3);
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solo_reg_write(solo_dev, SOLO_SYS_CFG, reg);
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if (solo_dev->flags & FLAGS_6110) {
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u32 sys_clock_MHz = SOLO_CLOCK_MHZ;
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u32 pll_DIVQ;
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u32 pll_DIVF;
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if (solo_dev->flags & FLAGS_6110) {
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u32 sys_clock_MHz = SOLO_CLOCK_MHZ;
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u32 pll_DIVQ;
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u32 pll_DIVF;
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if (sys_clock_MHz < 125) {
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pll_DIVQ = 3;
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pll_DIVF = (sys_clock_MHz * 4) / 3;
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} else {
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pll_DIVQ = 2;
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pll_DIVF = (sys_clock_MHz * 2) / 3;
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}
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if (sys_clock_MHz < 125) {
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pll_DIVQ = 3;
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pll_DIVF = (sys_clock_MHz * 4) / 3;
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} else {
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pll_DIVQ = 2;
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pll_DIVF = (sys_clock_MHz * 2) / 3;
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}
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solo_reg_write(solo_dev, SOLO6110_PLL_CONFIG,
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solo_reg_write(solo_dev, SOLO6110_PLL_CONFIG,
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SOLO6110_PLL_RANGE_5_10MHZ |
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SOLO6110_PLL_DIVR(9) |
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SOLO6110_PLL_DIVQ_EXP(pll_DIVQ) |
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SOLO6110_PLL_DIVF(pll_DIVF) | SOLO6110_PLL_FSEN);
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mdelay(1); // PLL Locking time (1ms)
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mdelay(1); /* PLL Locking time (1ms) */
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solo_reg_write(solo_dev, SOLO_DMA_CTRL1, 3 << 8); /* ? */
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} else
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} else
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solo_reg_write(solo_dev, SOLO_DMA_CTRL1, 1 << 8); /* ? */
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solo_reg_write(solo_dev, SOLO_TIMER_CLOCK_NUM, SOLO_CLOCK_MHZ - 1);
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