Merge branch 'marco-prepare' of git://gitorious.org/sirfprima2-kernel/sirfprima2-kernel into next/cleanup
* 'marco-prepare' of git://gitorious.org/sirfprima2-kernel/sirfprima2-kernel: ARM: SIRF: make sirf irqchip driver optional since new SoCs will have GIC ARM: PRIMA2: adjust Kconfig to support select SoC features ARM: PRIMA2: use DT_MACHINE_START and convert to generic board clk: prima2: move from arch/arm/mach to drivers/clk ARM: PRIMA2: convert to common clk and finish full clk tree
This commit is contained in:
Olof Johansson
Коммит
242521e90e
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@ -405,21 +405,19 @@ config ARCH_GEMINI
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help
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Support for the Cortina Systems Gemini family SoCs
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config ARCH_PRIMA2
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bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
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select CPU_V7
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config ARCH_SIRF
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bool "CSR SiRF"
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select NO_IOPORT
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select ARCH_REQUIRE_GPIOLIB
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select GENERIC_CLOCKEVENTS
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select CLKDEV_LOOKUP
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select COMMON_CLK
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select GENERIC_IRQ_CHIP
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select MIGHT_HAVE_CACHE_L2X0
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select PINCTRL
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select PINCTRL_SIRF
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select USE_OF
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select ZONE_DMA
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help
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Support for CSR SiRFSoC ARM Cortex A9 Platform
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Support for CSR SiRFprimaII/Marco/Polo platforms
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config ARCH_EBSA110
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bool "EBSA-110"
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@ -1108,6 +1106,8 @@ source "arch/arm/mach-exynos/Kconfig"
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source "arch/arm/mach-shmobile/Kconfig"
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source "arch/arm/mach-prima2/Kconfig"
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source "arch/arm/mach-tegra/Kconfig"
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source "arch/arm/mach-u300/Kconfig"
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@ -1,4 +1,6 @@
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CONFIG_EXPERIMENTAL=y
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CONFIG_NO_HZ=y
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CONFIG_HIGH_RES_TIMERS=y
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CONFIG_RELAY=y
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CONFIG_BLK_DEV_INITRD=y
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CONFIG_KALLSYMS_ALL=y
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@ -8,9 +10,7 @@ CONFIG_MODULE_UNLOAD=y
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CONFIG_PARTITION_ADVANCED=y
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CONFIG_BSD_DISKLABEL=y
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CONFIG_SOLARIS_X86_PARTITION=y
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CONFIG_ARCH_PRIMA2=y
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CONFIG_NO_HZ=y
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CONFIG_HIGH_RES_TIMERS=y
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CONFIG_ARCH_SIRF=y
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CONFIG_PREEMPT=y
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CONFIG_AEABI=y
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CONFIG_KEXEC=y
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@ -36,7 +36,6 @@ CONFIG_SPI=y
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CONFIG_SPI_SIRF=y
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CONFIG_SPI_SPIDEV=y
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# CONFIG_HWMON is not set
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# CONFIG_HID_SUPPORT is not set
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CONFIG_USB_GADGET=y
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CONFIG_USB_FILE_STORAGE=m
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CONFIG_USB_MASS_STORAGE=m
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@ -0,0 +1,19 @@
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if ARCH_SIRF
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menu "CSR SiRF primaII/Marco/Polo Specific Features"
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config ARCH_PRIMA2
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bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
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default y
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select CPU_V7
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select ZONE_DMA
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select SIRF_IRQ
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help
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Support for CSR SiRFSoC ARM Cortex A9 Platform
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endmenu
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config SIRF_IRQ
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bool
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endif
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@ -1,9 +1,8 @@
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obj-y := timer.o
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obj-y += irq.o
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obj-y += clock.o
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obj-y += rstc.o
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obj-y += prima2.o
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obj-y += common.o
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obj-y += rtciobrg.o
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obj-$(CONFIG_DEBUG_LL) += lluart.o
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obj-$(CONFIG_CACHE_L2X0) += l2x0.o
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obj-$(CONFIG_SUSPEND) += pm.o sleep.o
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obj-$(CONFIG_SIRF_IRQ) += irq.o
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@ -1,510 +0,0 @@
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/*
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* Clock tree for CSR SiRFprimaII
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*
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/module.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/clkdev.h>
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#include <linux/clk.h>
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#include <linux/spinlock.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <asm/mach/map.h>
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#include <mach/map.h>
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#define SIRFSOC_CLKC_CLK_EN0 0x0000
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#define SIRFSOC_CLKC_CLK_EN1 0x0004
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#define SIRFSOC_CLKC_REF_CFG 0x0014
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#define SIRFSOC_CLKC_CPU_CFG 0x0018
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#define SIRFSOC_CLKC_MEM_CFG 0x001c
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#define SIRFSOC_CLKC_SYS_CFG 0x0020
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#define SIRFSOC_CLKC_IO_CFG 0x0024
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#define SIRFSOC_CLKC_DSP_CFG 0x0028
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#define SIRFSOC_CLKC_GFX_CFG 0x002c
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#define SIRFSOC_CLKC_MM_CFG 0x0030
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#define SIRFSOC_LKC_LCD_CFG 0x0034
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#define SIRFSOC_CLKC_MMC_CFG 0x0038
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#define SIRFSOC_CLKC_PLL1_CFG0 0x0040
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#define SIRFSOC_CLKC_PLL2_CFG0 0x0044
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#define SIRFSOC_CLKC_PLL3_CFG0 0x0048
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#define SIRFSOC_CLKC_PLL1_CFG1 0x004c
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#define SIRFSOC_CLKC_PLL2_CFG1 0x0050
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#define SIRFSOC_CLKC_PLL3_CFG1 0x0054
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#define SIRFSOC_CLKC_PLL1_CFG2 0x0058
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#define SIRFSOC_CLKC_PLL2_CFG2 0x005c
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#define SIRFSOC_CLKC_PLL3_CFG2 0x0060
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#define SIRFSOC_CLOCK_VA_BASE SIRFSOC_VA(0x005000)
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#define KHZ 1000
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#define MHZ (KHZ * KHZ)
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struct clk_ops {
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unsigned long (*get_rate)(struct clk *clk);
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long (*round_rate)(struct clk *clk, unsigned long rate);
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int (*set_rate)(struct clk *clk, unsigned long rate);
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int (*enable)(struct clk *clk);
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int (*disable)(struct clk *clk);
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struct clk *(*get_parent)(struct clk *clk);
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int (*set_parent)(struct clk *clk, struct clk *parent);
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};
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struct clk {
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struct clk *parent; /* parent clk */
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unsigned long rate; /* clock rate in Hz */
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signed char usage; /* clock enable count */
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signed char enable_bit; /* enable bit: 0 ~ 63 */
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unsigned short regofs; /* register offset */
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struct clk_ops *ops; /* clock operation */
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};
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static DEFINE_SPINLOCK(clocks_lock);
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static inline unsigned long clkc_readl(unsigned reg)
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{
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return readl(SIRFSOC_CLOCK_VA_BASE + reg);
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}
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static inline void clkc_writel(u32 val, unsigned reg)
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{
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writel(val, SIRFSOC_CLOCK_VA_BASE + reg);
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}
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/*
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* osc_rtc - real time oscillator - 32.768KHz
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* osc_sys - high speed oscillator - 26MHz
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*/
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static struct clk clk_rtc = {
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.rate = 32768,
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};
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static struct clk clk_osc = {
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.rate = 26 * MHZ,
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};
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/*
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* std pll
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*/
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static unsigned long std_pll_get_rate(struct clk *clk)
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{
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unsigned long fin = clk_get_rate(clk->parent);
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u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -
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SIRFSOC_CLKC_PLL1_CFG0;
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if (clkc_readl(regcfg2) & BIT(2)) {
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/* pll bypass mode */
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clk->rate = fin;
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} else {
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/* fout = fin * nf / nr / od */
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u32 cfg0 = clkc_readl(clk->regofs);
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u32 nf = (cfg0 & (BIT(13) - 1)) + 1;
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u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1;
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u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1;
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WARN_ON(fin % MHZ);
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clk->rate = fin / MHZ * nf / nr / od * MHZ;
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}
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return clk->rate;
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}
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static int std_pll_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long fin, nf, nr, od, reg;
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/*
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* fout = fin * nf / (nr * od);
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* set od = 1, nr = fin/MHz, so fout = nf * MHz
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*/
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nf = rate / MHZ;
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if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1))
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return -EINVAL;
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fin = clk_get_rate(clk->parent);
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BUG_ON(fin < MHZ);
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nr = fin / MHZ;
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BUG_ON((fin % MHZ) || nr > BIT(6));
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od = 1;
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reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19);
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clkc_writel(reg, clk->regofs);
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reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0;
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clkc_writel((nf >> 1) - 1, reg);
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reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0;
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while (!(clkc_readl(reg) & BIT(6)))
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cpu_relax();
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clk->rate = 0; /* set to zero will force recalculation */
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return 0;
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}
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static struct clk_ops std_pll_ops = {
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.get_rate = std_pll_get_rate,
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.set_rate = std_pll_set_rate,
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};
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static struct clk clk_pll1 = {
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.parent = &clk_osc,
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.regofs = SIRFSOC_CLKC_PLL1_CFG0,
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.ops = &std_pll_ops,
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};
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static struct clk clk_pll2 = {
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.parent = &clk_osc,
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.regofs = SIRFSOC_CLKC_PLL2_CFG0,
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.ops = &std_pll_ops,
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};
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static struct clk clk_pll3 = {
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.parent = &clk_osc,
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.regofs = SIRFSOC_CLKC_PLL3_CFG0,
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.ops = &std_pll_ops,
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};
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/*
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* clock domains - cpu, mem, sys/io
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*/
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static struct clk clk_mem;
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static struct clk *dmn_get_parent(struct clk *clk)
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{
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struct clk *clks[] = {
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&clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3
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};
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u32 cfg = clkc_readl(clk->regofs);
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WARN_ON((cfg & (BIT(3) - 1)) > 4);
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return clks[cfg & (BIT(3) - 1)];
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}
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static int dmn_set_parent(struct clk *clk, struct clk *parent)
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{
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const struct clk *clks[] = {
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&clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3
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};
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u32 cfg = clkc_readl(clk->regofs);
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int i;
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for (i = 0; i < ARRAY_SIZE(clks); i++) {
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if (clks[i] == parent) {
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cfg &= ~(BIT(3) - 1);
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clkc_writel(cfg | i, clk->regofs);
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/* BIT(3) - switching status: 1 - busy, 0 - done */
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while (clkc_readl(clk->regofs) & BIT(3))
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cpu_relax();
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return 0;
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}
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}
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return -EINVAL;
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}
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static unsigned long dmn_get_rate(struct clk *clk)
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{
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unsigned long fin = clk_get_rate(clk->parent);
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u32 cfg = clkc_readl(clk->regofs);
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if (cfg & BIT(24)) {
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/* fcd bypass mode */
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clk->rate = fin;
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} else {
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/*
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* wait count: bit[19:16], hold count: bit[23:20]
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*/
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u32 wait = (cfg >> 16) & (BIT(4) - 1);
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u32 hold = (cfg >> 20) & (BIT(4) - 1);
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clk->rate = fin / (wait + hold + 2);
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}
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return clk->rate;
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}
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static int dmn_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long fin;
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unsigned ratio, wait, hold, reg;
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unsigned bits = (clk == &clk_mem) ? 3 : 4;
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fin = clk_get_rate(clk->parent);
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ratio = fin / rate;
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if (unlikely(ratio < 2 || ratio > BIT(bits + 1)))
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return -EINVAL;
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||||
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WARN_ON(fin % rate);
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wait = (ratio >> 1) - 1;
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hold = ratio - wait - 2;
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reg = clkc_readl(clk->regofs);
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reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20));
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reg |= (wait << 16) | (hold << 20) | BIT(25);
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clkc_writel(reg, clk->regofs);
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/* waiting FCD been effective */
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while (clkc_readl(clk->regofs) & BIT(25))
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cpu_relax();
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clk->rate = 0; /* set to zero will force recalculation */
|
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|
||||
return 0;
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||||
}
|
||||
|
||||
/*
|
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* cpu clock has no FCD register in Prima2, can only change pll
|
||||
*/
|
||||
static int cpu_set_rate(struct clk *clk, unsigned long rate)
|
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{
|
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int ret1, ret2;
|
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struct clk *cur_parent, *tmp_parent;
|
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|
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cur_parent = dmn_get_parent(clk);
|
||||
BUG_ON(cur_parent == NULL || cur_parent->usage > 1);
|
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|
||||
/* switch to tmp pll before setting parent clock's rate */
|
||||
tmp_parent = cur_parent == &clk_pll1 ? &clk_pll2 : &clk_pll1;
|
||||
ret1 = dmn_set_parent(clk, tmp_parent);
|
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BUG_ON(ret1);
|
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|
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ret2 = clk_set_rate(cur_parent, rate);
|
||||
|
||||
ret1 = dmn_set_parent(clk, cur_parent);
|
||||
|
||||
clk->rate = 0; /* set to zero will force recalculation */
|
||||
|
||||
return ret2 ? ret2 : ret1;
|
||||
}
|
||||
|
||||
static struct clk_ops cpu_ops = {
|
||||
.get_parent = dmn_get_parent,
|
||||
.set_parent = dmn_set_parent,
|
||||
.set_rate = cpu_set_rate,
|
||||
};
|
||||
|
||||
static struct clk clk_cpu = {
|
||||
.parent = &clk_pll1,
|
||||
.regofs = SIRFSOC_CLKC_CPU_CFG,
|
||||
.ops = &cpu_ops,
|
||||
};
|
||||
|
||||
|
||||
static struct clk_ops msi_ops = {
|
||||
.set_rate = dmn_set_rate,
|
||||
.get_rate = dmn_get_rate,
|
||||
.set_parent = dmn_set_parent,
|
||||
.get_parent = dmn_get_parent,
|
||||
};
|
||||
|
||||
static struct clk clk_mem = {
|
||||
.parent = &clk_pll2,
|
||||
.regofs = SIRFSOC_CLKC_MEM_CFG,
|
||||
.ops = &msi_ops,
|
||||
};
|
||||
|
||||
static struct clk clk_sys = {
|
||||
.parent = &clk_pll3,
|
||||
.regofs = SIRFSOC_CLKC_SYS_CFG,
|
||||
.ops = &msi_ops,
|
||||
};
|
||||
|
||||
static struct clk clk_io = {
|
||||
.parent = &clk_pll3,
|
||||
.regofs = SIRFSOC_CLKC_IO_CFG,
|
||||
.ops = &msi_ops,
|
||||
};
|
||||
|
||||
/*
|
||||
* on-chip clock sets
|
||||
*/
|
||||
static struct clk_lookup onchip_clks[] = {
|
||||
{
|
||||
.dev_id = "rtc",
|
||||
.clk = &clk_rtc,
|
||||
}, {
|
||||
.dev_id = "osc",
|
||||
.clk = &clk_osc,
|
||||
}, {
|
||||
.dev_id = "pll1",
|
||||
.clk = &clk_pll1,
|
||||
}, {
|
||||
.dev_id = "pll2",
|
||||
.clk = &clk_pll2,
|
||||
}, {
|
||||
.dev_id = "pll3",
|
||||
.clk = &clk_pll3,
|
||||
}, {
|
||||
.dev_id = "cpu",
|
||||
.clk = &clk_cpu,
|
||||
}, {
|
||||
.dev_id = "mem",
|
||||
.clk = &clk_mem,
|
||||
}, {
|
||||
.dev_id = "sys",
|
||||
.clk = &clk_sys,
|
||||
}, {
|
||||
.dev_id = "io",
|
||||
.clk = &clk_io,
|
||||
},
|
||||
};
|
||||
|
||||
int clk_enable(struct clk *clk)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
if (unlikely(IS_ERR_OR_NULL(clk)))
|
||||
return -EINVAL;
|
||||
|
||||
if (clk->parent)
|
||||
clk_enable(clk->parent);
|
||||
|
||||
spin_lock_irqsave(&clocks_lock, flags);
|
||||
if (!clk->usage++ && clk->ops && clk->ops->enable)
|
||||
clk->ops->enable(clk);
|
||||
spin_unlock_irqrestore(&clocks_lock, flags);
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_enable);
|
||||
|
||||
void clk_disable(struct clk *clk)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
if (unlikely(IS_ERR_OR_NULL(clk)))
|
||||
return;
|
||||
|
||||
WARN_ON(!clk->usage);
|
||||
|
||||
spin_lock_irqsave(&clocks_lock, flags);
|
||||
if (--clk->usage == 0 && clk->ops && clk->ops->disable)
|
||||
clk->ops->disable(clk);
|
||||
spin_unlock_irqrestore(&clocks_lock, flags);
|
||||
|
||||
if (clk->parent)
|
||||
clk_disable(clk->parent);
|
||||
}
|
||||
EXPORT_SYMBOL(clk_disable);
|
||||
|
||||
unsigned long clk_get_rate(struct clk *clk)
|
||||
{
|
||||
if (unlikely(IS_ERR_OR_NULL(clk)))
|
||||
return 0;
|
||||
|
||||
if (clk->rate)
|
||||
return clk->rate;
|
||||
|
||||
if (clk->ops && clk->ops->get_rate)
|
||||
return clk->ops->get_rate(clk);
|
||||
|
||||
return clk_get_rate(clk->parent);
|
||||
}
|
||||
EXPORT_SYMBOL(clk_get_rate);
|
||||
|
||||
long clk_round_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
if (unlikely(IS_ERR_OR_NULL(clk)))
|
||||
return 0;
|
||||
|
||||
if (clk->ops && clk->ops->round_rate)
|
||||
return clk->ops->round_rate(clk, rate);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_round_rate);
|
||||
|
||||
int clk_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
if (unlikely(IS_ERR_OR_NULL(clk)))
|
||||
return -EINVAL;
|
||||
|
||||
if (!clk->ops || !clk->ops->set_rate)
|
||||
return -EINVAL;
|
||||
|
||||
return clk->ops->set_rate(clk, rate);
|
||||
}
|
||||
EXPORT_SYMBOL(clk_set_rate);
|
||||
|
||||
int clk_set_parent(struct clk *clk, struct clk *parent)
|
||||
{
|
||||
int ret;
|
||||
unsigned long flags;
|
||||
|
||||
if (unlikely(IS_ERR_OR_NULL(clk)))
|
||||
return -EINVAL;
|
||||
|
||||
if (!clk->ops || !clk->ops->set_parent)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&clocks_lock, flags);
|
||||
ret = clk->ops->set_parent(clk, parent);
|
||||
if (!ret) {
|
||||
parent->usage += clk->usage;
|
||||
clk->parent->usage -= clk->usage;
|
||||
BUG_ON(clk->parent->usage < 0);
|
||||
clk->parent = parent;
|
||||
}
|
||||
spin_unlock_irqrestore(&clocks_lock, flags);
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_set_parent);
|
||||
|
||||
struct clk *clk_get_parent(struct clk *clk)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
if (unlikely(IS_ERR_OR_NULL(clk)))
|
||||
return NULL;
|
||||
|
||||
if (!clk->ops || !clk->ops->get_parent)
|
||||
return clk->parent;
|
||||
|
||||
spin_lock_irqsave(&clocks_lock, flags);
|
||||
clk->parent = clk->ops->get_parent(clk);
|
||||
spin_unlock_irqrestore(&clocks_lock, flags);
|
||||
return clk->parent;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_get_parent);
|
||||
|
||||
static void __init sirfsoc_clk_init(void)
|
||||
{
|
||||
clkdev_add_table(onchip_clks, ARRAY_SIZE(onchip_clks));
|
||||
}
|
||||
|
||||
static struct of_device_id clkc_ids[] = {
|
||||
{ .compatible = "sirf,prima2-clkc" },
|
||||
{},
|
||||
};
|
||||
|
||||
void __init sirfsoc_of_clk_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct resource res;
|
||||
struct map_desc sirfsoc_clkc_iodesc = {
|
||||
.virtual = SIRFSOC_CLOCK_VA_BASE,
|
||||
.type = MT_DEVICE,
|
||||
};
|
||||
|
||||
np = of_find_matching_node(NULL, clkc_ids);
|
||||
if (!np)
|
||||
panic("unable to find compatible clkc node in dtb\n");
|
||||
|
||||
if (of_address_to_resource(np, 0, &res))
|
||||
panic("unable to find clkc range in dtb");
|
||||
of_node_put(np);
|
||||
|
||||
sirfsoc_clkc_iodesc.pfn = __phys_to_pfn(res.start);
|
||||
sirfsoc_clkc_iodesc.length = 1 + res.end - res.start;
|
||||
|
||||
iotable_init(&sirfsoc_clkc_iodesc, 1);
|
||||
|
||||
sirfsoc_clk_init();
|
||||
}
|
||||
|
|
@ -30,21 +30,21 @@ void __init sirfsoc_init_late(void)
|
|||
sirfsoc_pm_init();
|
||||
}
|
||||
|
||||
static const char *prima2cb_dt_match[] __initdata = {
|
||||
"sirf,prima2-cb",
|
||||
#ifdef CONFIG_ARCH_PRIMA2
|
||||
static const char *prima2_dt_match[] __initdata = {
|
||||
"sirf,prima2",
|
||||
NULL
|
||||
};
|
||||
|
||||
MACHINE_START(PRIMA2_EVB, "prima2cb")
|
||||
DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
|
||||
/* Maintainer: Barry Song <baohua.song@csr.com> */
|
||||
.atag_offset = 0x100,
|
||||
.init_early = sirfsoc_of_clk_init,
|
||||
.map_io = sirfsoc_map_lluart,
|
||||
.init_irq = sirfsoc_of_irq_init,
|
||||
.timer = &sirfsoc_timer,
|
||||
.dma_zone_size = SZ_256M,
|
||||
.init_machine = sirfsoc_mach_init,
|
||||
.init_late = sirfsoc_init_late,
|
||||
.dt_compat = prima2cb_dt_match,
|
||||
.dt_compat = prima2_dt_match,
|
||||
.restart = sirfsoc_restart,
|
||||
MACHINE_END
|
||||
#endif
|
||||
|
|
@ -63,7 +63,7 @@ void __init sirfsoc_of_irq_init(void)
|
|||
|
||||
np = of_find_matching_node(NULL, intc_ids);
|
||||
if (!np)
|
||||
panic("unable to find compatible intc node in dtb\n");
|
||||
return;
|
||||
|
||||
sirfsoc_intc_base = of_iomap(np, 0);
|
||||
if (!sirfsoc_intc_base)
|
||||
|
|
|
|||
|
|
@ -21,6 +21,8 @@
|
|||
#include <asm/sched_clock.h>
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
#define SIRFSOC_TIMER_COUNTER_LO 0x0000
|
||||
#define SIRFSOC_TIMER_COUNTER_HI 0x0004
|
||||
#define SIRFSOC_TIMER_MATCH_0 0x0008
|
||||
|
|
@ -188,9 +190,13 @@ static void __init sirfsoc_clockevent_init(void)
|
|||
static void __init sirfsoc_timer_init(void)
|
||||
{
|
||||
unsigned long rate;
|
||||
struct clk *clk;
|
||||
|
||||
/* initialize clocking early, we want to set the OS timer */
|
||||
sirfsoc_of_clk_init();
|
||||
|
||||
/* timer's input clock is io clock */
|
||||
struct clk *clk = clk_get_sys("io", NULL);
|
||||
clk = clk_get_sys("io", NULL);
|
||||
|
||||
BUG_ON(IS_ERR(clk));
|
||||
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
|
|||
obj-$(CONFIG_PLAT_SPEAR) += spear/
|
||||
obj-$(CONFIG_ARCH_U300) += clk-u300.o
|
||||
obj-$(CONFIG_ARCH_INTEGRATOR) += versatile/
|
||||
obj-$(CONFIG_ARCH_PRIMA2) += clk-prima2.o
|
||||
|
||||
# Chip specific
|
||||
obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
|
||||
|
|
|
|||
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