Merge branches 'clk-mediatek', 'clk-imx', 'clk-amlogic' and 'clk-at91' into clk-next
* clk-mediatek: clk: mediatek: mux: Update parent at enable time clk: mediatek: mux: Drop unused clock ops clk: mediatek: Select all the MT8183 clocks by default * clk-imx: dt-bindings: clock: imx: Switch to my personal address MAINTAINERS: Add section for NXP i.MX clock drivers clk: imx: Move 'imx6sl_set_wait_clk()'s prototype out to accessible header clk: imx8mn: add clkout1/2 support clk: imx8mm: add clkout1/2 support clk: imx8mq: add PLL monitor output clk: imx: clk-imx31: Remove unused static const table 'uart_clks' clk: imx6q: demote warning about pre-boot ldb_di_clk reparenting clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS subsystems clk: imx: clk-imx8qxp: Register DC0 display clocks with imx_clk_scu2() clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocks clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocks * clk-amlogic: clk: meson: axg: Remove MIPI enable clock gate clk: meson-axg: remove CLKID_MIPI_ENABLE dt-bindings: clock: meson8b: remove non-existing clock macros clk: meson: meson8b: remove compatibility code for old .dtbs clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate() clk: meson: clk-pll: make "ret" a signed integer clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLL * clk-at91: clk: at91: Fix the declaration of the clocks
This commit is contained in:
Stephen Boyd
Коммит
242d8cf626
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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|||
title: Clock bindings for Freescale i.MX27
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||||
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||||
maintainers:
|
||||
- Fabio Estevam <fabio.estevam@nxp.com>
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||||
- Fabio Estevam <festevam@gmail.com>
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||||
|
||||
description: |
|
||||
The clock consumer should specify the desired clock by having the clock
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||||
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|
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|
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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|||
title: Clock bindings for Freescale i.MX31
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||||
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||||
maintainers:
|
||||
- Fabio Estevam <fabio.estevam@nxp.com>
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||||
- Fabio Estevam <festevam@gmail.com>
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||||
|
||||
description: |
|
||||
The clock consumer should specify the desired clock by having the clock
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||||
|
|
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|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
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|||
title: Clock bindings for Freescale i.MX5
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||||
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||||
maintainers:
|
||||
- Fabio Estevam <fabio.estevam@nxp.com>
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- Fabio Estevam <festevam@gmail.com>
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||||
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description: |
|
||||
The clock consumer should specify the desired clock by having the clock
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|
|
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@ -12751,6 +12751,13 @@ F: drivers/iio/gyro/fxas21002c_core.c
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F: drivers/iio/gyro/fxas21002c_i2c.c
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F: drivers/iio/gyro/fxas21002c_spi.c
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NXP i.MX CLOCK DRIVERS
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M: Abel Vesa <abel.vesa@nxp.com>
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L: linux-clk@vger.kernel.org
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L: linux-imx@nxp.com
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S: Maintained
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F: drivers/clk/imx/
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NXP i.MX 8MQ DCSS DRIVER
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M: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
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R: Lucas Stach <l.stach@pengutronix.de>
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|
|
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@ -85,7 +85,6 @@ void imx_anatop_pre_suspend(void);
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void imx_anatop_post_resume(void);
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int imx6_set_lpm(enum mxc_cpu_pwr_mode mode);
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void imx6_set_int_mem_clk_lpm(bool enable);
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void imx6sl_set_wait_clk(bool enter);
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int imx_mmdc_get_ddr_type(void);
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int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode);
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@ -3,6 +3,7 @@
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* Copyright (C) 2014 Freescale Semiconductor, Inc.
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*/
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#include <linux/clk/imx.h>
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#include <linux/cpuidle.h>
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#include <linux/module.h>
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#include <asm/cpuidle.h>
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|
|
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@ -4,6 +4,7 @@
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* Copyright 2011 Linaro Ltd.
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*/
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#include <linux/clk/imx.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/io.h>
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@ -215,5 +215,4 @@ err_free:
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* deferring properly. Once this is fixed, this can be switched to a platform
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* driver.
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*/
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CLK_OF_DECLARE_DRIVER(at91rm9200_pmc, "atmel,at91rm9200-pmc",
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at91rm9200_pmc_setup);
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CLK_OF_DECLARE(at91rm9200_pmc, "atmel,at91rm9200-pmc", at91rm9200_pmc_setup);
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@ -491,26 +491,26 @@ static void __init at91sam9260_pmc_setup(struct device_node *np)
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{
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at91sam926x_pmc_setup(np, &at91sam9260_data);
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}
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CLK_OF_DECLARE_DRIVER(at91sam9260_pmc, "atmel,at91sam9260-pmc",
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at91sam9260_pmc_setup);
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CLK_OF_DECLARE(at91sam9260_pmc, "atmel,at91sam9260-pmc", at91sam9260_pmc_setup);
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static void __init at91sam9261_pmc_setup(struct device_node *np)
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{
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at91sam926x_pmc_setup(np, &at91sam9261_data);
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}
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CLK_OF_DECLARE_DRIVER(at91sam9261_pmc, "atmel,at91sam9261-pmc",
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at91sam9261_pmc_setup);
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CLK_OF_DECLARE(at91sam9261_pmc, "atmel,at91sam9261-pmc", at91sam9261_pmc_setup);
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static void __init at91sam9263_pmc_setup(struct device_node *np)
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{
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at91sam926x_pmc_setup(np, &at91sam9263_data);
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}
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CLK_OF_DECLARE_DRIVER(at91sam9263_pmc, "atmel,at91sam9263-pmc",
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at91sam9263_pmc_setup);
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CLK_OF_DECLARE(at91sam9263_pmc, "atmel,at91sam9263-pmc", at91sam9263_pmc_setup);
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static void __init at91sam9g20_pmc_setup(struct device_node *np)
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{
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at91sam926x_pmc_setup(np, &at91sam9g20_data);
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}
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CLK_OF_DECLARE_DRIVER(at91sam9g20_pmc, "atmel,at91sam9g20-pmc",
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at91sam9g20_pmc_setup);
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CLK_OF_DECLARE(at91sam9g20_pmc, "atmel,at91sam9g20-pmc", at91sam9g20_pmc_setup);
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|
|
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|||
|
|
@ -228,5 +228,4 @@ err_free:
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* The TCB is used as the clocksource so its clock is needed early. This means
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* this can't be a platform driver.
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*/
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CLK_OF_DECLARE_DRIVER(at91sam9g45_pmc, "atmel,at91sam9g45-pmc",
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at91sam9g45_pmc_setup);
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CLK_OF_DECLARE(at91sam9g45_pmc, "atmel,at91sam9g45-pmc", at91sam9g45_pmc_setup);
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|
|
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|||
|
|
@ -255,5 +255,4 @@ err_free:
|
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* The TCB is used as the clocksource so its clock is needed early. This means
|
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* this can't be a platform driver.
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||||
*/
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CLK_OF_DECLARE_DRIVER(at91sam9n12_pmc, "atmel,at91sam9n12-pmc",
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at91sam9n12_pmc_setup);
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CLK_OF_DECLARE(at91sam9n12_pmc, "atmel,at91sam9n12-pmc", at91sam9n12_pmc_setup);
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@ -186,4 +186,5 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np)
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err_free:
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kfree(at91sam9rl_pmc);
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}
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CLK_OF_DECLARE_DRIVER(at91sam9rl_pmc, "atmel,at91sam9rl-pmc", at91sam9rl_pmc_setup);
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CLK_OF_DECLARE(at91sam9rl_pmc, "atmel,at91sam9rl-pmc", at91sam9rl_pmc_setup);
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|
@ -302,33 +302,33 @@ static void __init at91sam9g15_pmc_setup(struct device_node *np)
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{
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at91sam9x5_pmc_setup(np, at91sam9g15_periphck, true);
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}
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CLK_OF_DECLARE_DRIVER(at91sam9g15_pmc, "atmel,at91sam9g15-pmc",
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at91sam9g15_pmc_setup);
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CLK_OF_DECLARE(at91sam9g15_pmc, "atmel,at91sam9g15-pmc", at91sam9g15_pmc_setup);
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static void __init at91sam9g25_pmc_setup(struct device_node *np)
|
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{
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at91sam9x5_pmc_setup(np, at91sam9g25_periphck, false);
|
||||
}
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CLK_OF_DECLARE_DRIVER(at91sam9g25_pmc, "atmel,at91sam9g25-pmc",
|
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at91sam9g25_pmc_setup);
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|
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CLK_OF_DECLARE(at91sam9g25_pmc, "atmel,at91sam9g25-pmc", at91sam9g25_pmc_setup);
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static void __init at91sam9g35_pmc_setup(struct device_node *np)
|
||||
{
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at91sam9x5_pmc_setup(np, at91sam9g35_periphck, true);
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}
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CLK_OF_DECLARE_DRIVER(at91sam9g35_pmc, "atmel,at91sam9g35-pmc",
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at91sam9g35_pmc_setup);
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CLK_OF_DECLARE(at91sam9g35_pmc, "atmel,at91sam9g35-pmc", at91sam9g35_pmc_setup);
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static void __init at91sam9x25_pmc_setup(struct device_node *np)
|
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{
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at91sam9x5_pmc_setup(np, at91sam9x25_periphck, false);
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}
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CLK_OF_DECLARE_DRIVER(at91sam9x25_pmc, "atmel,at91sam9x25-pmc",
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at91sam9x25_pmc_setup);
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CLK_OF_DECLARE(at91sam9x25_pmc, "atmel,at91sam9x25-pmc", at91sam9x25_pmc_setup);
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static void __init at91sam9x35_pmc_setup(struct device_node *np)
|
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{
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at91sam9x5_pmc_setup(np, at91sam9x35_periphck, true);
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}
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CLK_OF_DECLARE_DRIVER(at91sam9x35_pmc, "atmel,at91sam9x35-pmc",
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at91sam9x35_pmc_setup);
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CLK_OF_DECLARE(at91sam9x35_pmc, "atmel,at91sam9x35-pmc", at91sam9x35_pmc_setup);
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|
@ -372,4 +372,5 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
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err_free:
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kfree(sama5d2_pmc);
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||||
}
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CLK_OF_DECLARE_DRIVER(sama5d2_pmc, "atmel,sama5d2-pmc", sama5d2_pmc_setup);
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CLK_OF_DECLARE(sama5d2_pmc, "atmel,sama5d2-pmc", sama5d2_pmc_setup);
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|
|
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|||
|
|
@ -255,4 +255,4 @@ err_free:
|
|||
* The TCB is used as the clocksource so its clock is needed early. This means
|
||||
* this can't be a platform driver.
|
||||
*/
|
||||
CLK_OF_DECLARE_DRIVER(sama5d3_pmc, "atmel,sama5d3-pmc", sama5d3_pmc_setup);
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CLK_OF_DECLARE(sama5d3_pmc, "atmel,sama5d3-pmc", sama5d3_pmc_setup);
|
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|
|
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|||
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|
@ -286,4 +286,5 @@ static void __init sama5d4_pmc_setup(struct device_node *np)
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err_free:
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kfree(sama5d4_pmc);
|
||||
}
|
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CLK_OF_DECLARE_DRIVER(sama5d4_pmc, "atmel,sama5d4-pmc", sama5d4_pmc_setup);
|
||||
|
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CLK_OF_DECLARE(sama5d4_pmc, "atmel,sama5d4-pmc", sama5d4_pmc_setup);
|
||||
|
|
|
|||
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|
@ -51,16 +51,6 @@ enum mx31_clks {
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static struct clk *clk[clk_max];
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static struct clk_onecell_data clk_data;
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|
||||
static struct clk ** const uart_clks[] __initconst = {
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&clk[ipg],
|
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&clk[uart1_gate],
|
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&clk[uart2_gate],
|
||||
&clk[uart3_gate],
|
||||
&clk[uart4_gate],
|
||||
&clk[uart5_gate],
|
||||
NULL
|
||||
};
|
||||
|
||||
static void __init _mx31_clocks_init(void __iomem *base, unsigned long fref)
|
||||
{
|
||||
clk[dummy] = imx_clk_fixed("dummy", 0);
|
||||
|
|
|
|||
|
|
@ -338,10 +338,10 @@ static void init_ldb_clks(struct device_node *np, void __iomem *ccm_base)
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of_assigned_ldb_sels(np, &sel[0][3], &sel[1][3]);
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
/* Warn if a glitch might have been introduced already */
|
||||
/* Print a notice if a glitch might have been introduced already */
|
||||
if (sel[i][0] != 3) {
|
||||
pr_warn("ccm: ldb_di%d_sel already changed from reset value: %d\n",
|
||||
i, sel[i][0]);
|
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pr_notice("ccm: possible glitch: ldb_di%d_sel already changed from reset value: %d\n",
|
||||
i, sel[i][0]);
|
||||
}
|
||||
|
||||
if (sel[i][0] == sel[i][3])
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@
|
|||
#include <linux/bits.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk/imx.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
|
|
|||
|
|
@ -288,6 +288,11 @@ static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "dummy", "
|
|||
static const char *imx8mm_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m", "sys_pll2_166m",
|
||||
"sys_pll3_out", "audio_pll1_out", "video_pll1_out", "osc_32k", };
|
||||
|
||||
static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
|
||||
"dummy", "dummy", "gpu_pll_out", "vpu_pll_out",
|
||||
"arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
|
||||
"dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
|
||||
|
||||
static struct clk_hw_onecell_data *clk_hw_data;
|
||||
static struct clk_hw **hws;
|
||||
|
||||
|
|
@ -410,6 +415,13 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MM_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
|
||||
hws[IMX8MM_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
|
||||
|
||||
hws[IMX8MM_CLK_CLKOUT1_SEL] = imx_clk_hw_mux("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
|
||||
hws[IMX8MM_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, 0, 4);
|
||||
hws[IMX8MM_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
|
||||
hws[IMX8MM_CLK_CLKOUT2_SEL] = imx_clk_hw_mux("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
|
||||
hws[IMX8MM_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, 16, 4);
|
||||
hws[IMX8MM_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);
|
||||
|
||||
np = dev->of_node;
|
||||
base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (WARN_ON(IS_ERR(base)))
|
||||
|
|
|
|||
|
|
@ -281,6 +281,11 @@ static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sy
|
|||
"sys_pll2_166m", "sys_pll3_out", "audio_pll1_out",
|
||||
"video_pll1_out", "osc_32k", };
|
||||
|
||||
static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
|
||||
"dummy", "dummy", "gpu_pll_out", "dummy",
|
||||
"arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
|
||||
"dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
|
||||
|
||||
static struct clk_hw_onecell_data *clk_hw_data;
|
||||
static struct clk_hw **hws;
|
||||
|
||||
|
|
@ -405,6 +410,13 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MN_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
|
||||
hws[IMX8MN_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
|
||||
|
||||
hws[IMX8MN_CLK_CLKOUT1_SEL] = imx_clk_hw_mux("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
|
||||
hws[IMX8MN_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, 0, 4);
|
||||
hws[IMX8MN_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
|
||||
hws[IMX8MN_CLK_CLKOUT2_SEL] = imx_clk_hw_mux("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
|
||||
hws[IMX8MN_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, 16, 4);
|
||||
hws[IMX8MN_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);
|
||||
|
||||
np = dev->of_node;
|
||||
base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (WARN_ON(IS_ERR(base))) {
|
||||
|
|
|
|||
|
|
@ -270,6 +270,14 @@ static const char * const imx8mq_clko1_sels[] = {"osc_25m", "sys1_pll_800m", "os
|
|||
static const char * const imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_400m", "sys2_pll_166m",
|
||||
"sys3_pll_out", "audio_pll1_out", "video_pll1_out", "ckil", };
|
||||
|
||||
static const char * const pllout_monitor_sels[] = {"osc_25m", "osc_27m", "dummy", "dummy", "ckil",
|
||||
"audio_pll1_out_monitor", "audio_pll2_out_monitor",
|
||||
"video_pll1_out_monitor", "gpu_pll_out_monitor",
|
||||
"vpu_pll_out_monitor", "arm_pll_out_monitor",
|
||||
"sys_pll1_out_monitor", "sys_pll2_out_monitor",
|
||||
"sys_pll3_out_monitor", "dram_pll_out_monitor",
|
||||
"video_pll2_out_monitor", };
|
||||
|
||||
static struct clk_hw_onecell_data *clk_hw_data;
|
||||
static struct clk_hw **hws;
|
||||
|
||||
|
|
@ -399,6 +407,20 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MQ_SYS2_PLL_500M] = imx_clk_hw_fixed_factor("sys2_pll_500m", "sys2_pll_500m_cg", 1, 2);
|
||||
hws[IMX8MQ_SYS2_PLL_1000M] = imx_clk_hw_fixed_factor("sys2_pll_1000m", "sys2_pll_1000m_cg", 1, 1);
|
||||
|
||||
hws[IMX8MQ_CLK_MON_AUDIO_PLL1_DIV] = imx_clk_hw_divider("audio_pll1_out_monitor", "audio_pll1_bypass", base + 0x78, 0, 3);
|
||||
hws[IMX8MQ_CLK_MON_AUDIO_PLL2_DIV] = imx_clk_hw_divider("audio_pll2_out_monitor", "audio_pll2_bypass", base + 0x78, 4, 3);
|
||||
hws[IMX8MQ_CLK_MON_VIDEO_PLL1_DIV] = imx_clk_hw_divider("video_pll1_out_monitor", "video_pll1_bypass", base + 0x78, 8, 3);
|
||||
hws[IMX8MQ_CLK_MON_GPU_PLL_DIV] = imx_clk_hw_divider("gpu_pll_out_monitor", "gpu_pll_bypass", base + 0x78, 12, 3);
|
||||
hws[IMX8MQ_CLK_MON_VPU_PLL_DIV] = imx_clk_hw_divider("vpu_pll_out_monitor", "vpu_pll_bypass", base + 0x78, 16, 3);
|
||||
hws[IMX8MQ_CLK_MON_ARM_PLL_DIV] = imx_clk_hw_divider("arm_pll_out_monitor", "arm_pll_bypass", base + 0x78, 20, 3);
|
||||
hws[IMX8MQ_CLK_MON_SYS_PLL1_DIV] = imx_clk_hw_divider("sys_pll1_out_monitor", "sys1_pll_out", base + 0x7c, 0, 3);
|
||||
hws[IMX8MQ_CLK_MON_SYS_PLL2_DIV] = imx_clk_hw_divider("sys_pll2_out_monitor", "sys2_pll_out", base + 0x7c, 4, 3);
|
||||
hws[IMX8MQ_CLK_MON_SYS_PLL3_DIV] = imx_clk_hw_divider("sys_pll3_out_monitor", "sys3_pll_out", base + 0x7c, 8, 3);
|
||||
hws[IMX8MQ_CLK_MON_DRAM_PLL_DIV] = imx_clk_hw_divider("dram_pll_out_monitor", "dram_pll_out", base + 0x7c, 12, 3);
|
||||
hws[IMX8MQ_CLK_MON_VIDEO_PLL2_DIV] = imx_clk_hw_divider("video_pll2_out_monitor", "video2_pll_out", base + 0x7c, 16, 3);
|
||||
hws[IMX8MQ_CLK_MON_SEL] = imx_clk_hw_mux("pllout_monitor_sel", base + 0x74, 0, 4, pllout_monitor_sels, ARRAY_SIZE(pllout_monitor_sels));
|
||||
hws[IMX8MQ_CLK_MON_CLK2_OUT] = imx_clk_hw_gate("pllout_monitor_clk2", "pllout_monitor_sel", base + 0x74, 4);
|
||||
|
||||
np = dev->of_node;
|
||||
base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (WARN_ON(IS_ERR(base)))
|
||||
|
|
|
|||
|
|
@ -17,6 +17,14 @@
|
|||
#include <dt-bindings/clock/imx8-clock.h>
|
||||
#include <dt-bindings/firmware/imx/rsrc.h>
|
||||
|
||||
static const char *dc0_sels[] = {
|
||||
"clk_dummy",
|
||||
"clk_dummy",
|
||||
"dc0_pll0_clk",
|
||||
"dc0_pll1_clk",
|
||||
"dc0_bypass0_clk",
|
||||
};
|
||||
|
||||
static int imx8qxp_clk_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *ccm_node = pdev->dev.of_node;
|
||||
|
|
@ -115,12 +123,26 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
|
|||
clks[IMX_CONN_USB2_LPM_CLK] = imx_clk_scu("usb3_lpm_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MISC, clk_cells);
|
||||
|
||||
/* Display controller SS */
|
||||
clks[IMX_DC0_DISP0_CLK] = imx_clk_scu("dc0_disp0_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0, clk_cells);
|
||||
clks[IMX_DC0_DISP1_CLK] = imx_clk_scu("dc0_disp1_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1, clk_cells);
|
||||
clks[IMX_DC0_DISP0_CLK] = imx_clk_scu2("dc0_disp0_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0, clk_cells);
|
||||
clks[IMX_DC0_DISP1_CLK] = imx_clk_scu2("dc0_disp1_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1, clk_cells);
|
||||
clks[IMX_DC0_PLL0_CLK] = imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL, clk_cells);
|
||||
clks[IMX_DC0_PLL1_CLK] = imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL, clk_cells);
|
||||
clks[IMX_DC0_BYPASS0_CLK] = imx_clk_scu("dc0_bypass0_clk", IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS, clk_cells);
|
||||
clks[IMX_DC0_BYPASS1_CLK] = imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS, clk_cells);
|
||||
|
||||
/* MIPI-LVDS SS */
|
||||
clks[IMX_MIPI0_LVDS_PIXEL_CLK] = imx_clk_scu("mipi0_lvds_pixel_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2, clk_cells);
|
||||
clks[IMX_MIPI0_LVDS_BYPASS_CLK] = imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS, clk_cells);
|
||||
clks[IMX_MIPI0_LVDS_PHY_CLK] = imx_clk_scu("mipi0_lvds_phy_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3, clk_cells);
|
||||
clks[IMX_MIPI0_I2C0_CLK] = imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells);
|
||||
clks[IMX_MIPI0_I2C1_CLK] = imx_clk_scu("mipi0_i2c1_clk", IMX_SC_R_MIPI_0_I2C_1, IMX_SC_PM_CLK_MISC2, clk_cells);
|
||||
clks[IMX_MIPI0_PWM0_CLK] = imx_clk_scu("mipi0_pwm0_clk", IMX_SC_R_MIPI_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
clks[IMX_MIPI1_LVDS_PIXEL_CLK] = imx_clk_scu("mipi1_lvds_pixel_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2, clk_cells);
|
||||
clks[IMX_MIPI1_LVDS_BYPASS_CLK] = imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS, clk_cells);
|
||||
clks[IMX_MIPI1_LVDS_PHY_CLK] = imx_clk_scu("mipi1_lvds_phy_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3, clk_cells);
|
||||
clks[IMX_MIPI1_I2C0_CLK] = imx_clk_scu("mipi1_i2c0_clk", IMX_SC_R_MIPI_1_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells);
|
||||
clks[IMX_MIPI1_I2C1_CLK] = imx_clk_scu("mipi1_i2c1_clk", IMX_SC_R_MIPI_1_I2C_1, IMX_SC_PM_CLK_MISC2, clk_cells);
|
||||
clks[IMX_MIPI1_PWM0_CLK] = imx_clk_scu("mipi1_pwm0_clk", IMX_SC_R_MIPI_1_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
|
||||
/* MIPI CSI SS */
|
||||
clks[IMX_CSI0_CORE_CLK] = imx_clk_scu("mipi_csi0_core_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_PER, clk_cells);
|
||||
|
|
|
|||
|
|
@ -426,66 +426,77 @@ config COMMON_CLK_MT8183
|
|||
config COMMON_CLK_MT8183_AUDIOSYS
|
||||
bool "Clock driver for MediaTek MT8183 audiosys"
|
||||
depends on COMMON_CLK_MT8183
|
||||
default COMMON_CLK_MT8183
|
||||
help
|
||||
This driver supports MediaTek MT8183 audiosys clocks.
|
||||
|
||||
config COMMON_CLK_MT8183_CAMSYS
|
||||
bool "Clock driver for MediaTek MT8183 camsys"
|
||||
depends on COMMON_CLK_MT8183
|
||||
default COMMON_CLK_MT8183
|
||||
help
|
||||
This driver supports MediaTek MT8183 camsys clocks.
|
||||
|
||||
config COMMON_CLK_MT8183_IMGSYS
|
||||
bool "Clock driver for MediaTek MT8183 imgsys"
|
||||
depends on COMMON_CLK_MT8183
|
||||
default COMMON_CLK_MT8183
|
||||
help
|
||||
This driver supports MediaTek MT8183 imgsys clocks.
|
||||
|
||||
config COMMON_CLK_MT8183_IPU_CORE0
|
||||
bool "Clock driver for MediaTek MT8183 ipu_core0"
|
||||
depends on COMMON_CLK_MT8183
|
||||
default COMMON_CLK_MT8183
|
||||
help
|
||||
This driver supports MediaTek MT8183 ipu_core0 clocks.
|
||||
|
||||
config COMMON_CLK_MT8183_IPU_CORE1
|
||||
bool "Clock driver for MediaTek MT8183 ipu_core1"
|
||||
depends on COMMON_CLK_MT8183
|
||||
default COMMON_CLK_MT8183
|
||||
help
|
||||
This driver supports MediaTek MT8183 ipu_core1 clocks.
|
||||
|
||||
config COMMON_CLK_MT8183_IPU_ADL
|
||||
bool "Clock driver for MediaTek MT8183 ipu_adl"
|
||||
depends on COMMON_CLK_MT8183
|
||||
default COMMON_CLK_MT8183
|
||||
help
|
||||
This driver supports MediaTek MT8183 ipu_adl clocks.
|
||||
|
||||
config COMMON_CLK_MT8183_IPU_CONN
|
||||
bool "Clock driver for MediaTek MT8183 ipu_conn"
|
||||
depends on COMMON_CLK_MT8183
|
||||
default COMMON_CLK_MT8183
|
||||
help
|
||||
This driver supports MediaTek MT8183 ipu_conn clocks.
|
||||
|
||||
config COMMON_CLK_MT8183_MFGCFG
|
||||
bool "Clock driver for MediaTek MT8183 mfgcfg"
|
||||
depends on COMMON_CLK_MT8183
|
||||
default COMMON_CLK_MT8183
|
||||
help
|
||||
This driver supports MediaTek MT8183 mfgcfg clocks.
|
||||
|
||||
config COMMON_CLK_MT8183_MMSYS
|
||||
bool "Clock driver for MediaTek MT8183 mmsys"
|
||||
depends on COMMON_CLK_MT8183
|
||||
default COMMON_CLK_MT8183
|
||||
help
|
||||
This driver supports MediaTek MT8183 mmsys clocks.
|
||||
|
||||
config COMMON_CLK_MT8183_VDECSYS
|
||||
bool "Clock driver for MediaTek MT8183 vdecsys"
|
||||
depends on COMMON_CLK_MT8183
|
||||
default COMMON_CLK_MT8183
|
||||
help
|
||||
This driver supports MediaTek MT8183 vdecsys clocks.
|
||||
|
||||
config COMMON_CLK_MT8183_VENCSYS
|
||||
bool "Clock driver for MediaTek MT8183 vencsys"
|
||||
depends on COMMON_CLK_MT8183
|
||||
default COMMON_CLK_MT8183
|
||||
help
|
||||
This driver supports MediaTek MT8183 vencsys clocks.
|
||||
|
||||
|
|
|
|||
|
|
@ -17,29 +17,36 @@ static inline struct mtk_clk_mux *to_mtk_clk_mux(struct clk_hw *hw)
|
|||
return container_of(hw, struct mtk_clk_mux, hw);
|
||||
}
|
||||
|
||||
static int mtk_clk_mux_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
|
||||
u32 mask = BIT(mux->data->gate_shift);
|
||||
|
||||
return regmap_update_bits(mux->regmap, mux->data->mux_ofs,
|
||||
mask, ~mask);
|
||||
}
|
||||
|
||||
static void mtk_clk_mux_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
|
||||
u32 mask = BIT(mux->data->gate_shift);
|
||||
|
||||
regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask, mask);
|
||||
}
|
||||
|
||||
static int mtk_clk_mux_enable_setclr(struct clk_hw *hw)
|
||||
{
|
||||
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
|
||||
unsigned long flags = 0;
|
||||
|
||||
return regmap_write(mux->regmap, mux->data->clr_ofs,
|
||||
BIT(mux->data->gate_shift));
|
||||
if (mux->lock)
|
||||
spin_lock_irqsave(mux->lock, flags);
|
||||
else
|
||||
__acquire(mux->lock);
|
||||
|
||||
regmap_write(mux->regmap, mux->data->clr_ofs,
|
||||
BIT(mux->data->gate_shift));
|
||||
|
||||
/*
|
||||
* If the parent has been changed when the clock was disabled, it will
|
||||
* not be effective yet. Set the update bit to ensure the mux gets
|
||||
* updated.
|
||||
*/
|
||||
if (mux->reparent && mux->data->upd_shift >= 0) {
|
||||
regmap_write(mux->regmap, mux->data->upd_ofs,
|
||||
BIT(mux->data->upd_shift));
|
||||
mux->reparent = false;
|
||||
}
|
||||
|
||||
if (mux->lock)
|
||||
spin_unlock_irqrestore(mux->lock, flags);
|
||||
else
|
||||
__release(mux->lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mtk_clk_mux_disable_setclr(struct clk_hw *hw)
|
||||
|
|
@ -72,28 +79,6 @@ static u8 mtk_clk_mux_get_parent(struct clk_hw *hw)
|
|||
return val;
|
||||
}
|
||||
|
||||
static int mtk_clk_mux_set_parent_lock(struct clk_hw *hw, u8 index)
|
||||
{
|
||||
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
|
||||
u32 mask = GENMASK(mux->data->mux_width - 1, 0);
|
||||
unsigned long flags = 0;
|
||||
|
||||
if (mux->lock)
|
||||
spin_lock_irqsave(mux->lock, flags);
|
||||
else
|
||||
__acquire(mux->lock);
|
||||
|
||||
regmap_update_bits(mux->regmap, mux->data->mux_ofs, mask,
|
||||
index << mux->data->mux_shift);
|
||||
|
||||
if (mux->lock)
|
||||
spin_unlock_irqrestore(mux->lock, flags);
|
||||
else
|
||||
__release(mux->lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index)
|
||||
{
|
||||
struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
|
||||
|
|
@ -116,9 +101,11 @@ static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index)
|
|||
regmap_write(mux->regmap, mux->data->set_ofs,
|
||||
index << mux->data->mux_shift);
|
||||
|
||||
if (mux->data->upd_shift >= 0)
|
||||
if (mux->data->upd_shift >= 0) {
|
||||
regmap_write(mux->regmap, mux->data->upd_ofs,
|
||||
BIT(mux->data->upd_shift));
|
||||
mux->reparent = true;
|
||||
}
|
||||
}
|
||||
|
||||
if (mux->lock)
|
||||
|
|
@ -129,25 +116,7 @@ static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index)
|
|||
return 0;
|
||||
}
|
||||
|
||||
const struct clk_ops mtk_mux_ops = {
|
||||
.get_parent = mtk_clk_mux_get_parent,
|
||||
.set_parent = mtk_clk_mux_set_parent_lock,
|
||||
};
|
||||
|
||||
const struct clk_ops mtk_mux_clr_set_upd_ops = {
|
||||
.get_parent = mtk_clk_mux_get_parent,
|
||||
.set_parent = mtk_clk_mux_set_parent_setclr_lock,
|
||||
};
|
||||
|
||||
const struct clk_ops mtk_mux_gate_ops = {
|
||||
.enable = mtk_clk_mux_enable,
|
||||
.disable = mtk_clk_mux_disable,
|
||||
.is_enabled = mtk_clk_mux_is_enabled,
|
||||
.get_parent = mtk_clk_mux_get_parent,
|
||||
.set_parent = mtk_clk_mux_set_parent_lock,
|
||||
};
|
||||
|
||||
const struct clk_ops mtk_mux_gate_clr_set_upd_ops = {
|
||||
static const struct clk_ops mtk_mux_ops = {
|
||||
.enable = mtk_clk_mux_enable_setclr,
|
||||
.disable = mtk_clk_mux_disable_setclr,
|
||||
.is_enabled = mtk_clk_mux_is_enabled,
|
||||
|
|
@ -171,7 +140,7 @@ static struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
|
|||
init.flags = mux->flags | CLK_SET_RATE_PARENT;
|
||||
init.parent_names = mux->parent_names;
|
||||
init.num_parents = mux->num_parents;
|
||||
init.ops = mux->ops;
|
||||
init.ops = &mtk_mux_ops;
|
||||
|
||||
clk_mux->regmap = regmap;
|
||||
clk_mux->data = mux;
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@ struct mtk_clk_mux {
|
|||
struct regmap *regmap;
|
||||
const struct mtk_mux *data;
|
||||
spinlock_t *lock;
|
||||
bool reparent;
|
||||
};
|
||||
|
||||
struct mtk_mux {
|
||||
|
|
@ -32,19 +33,12 @@ struct mtk_mux {
|
|||
u8 gate_shift;
|
||||
s8 upd_shift;
|
||||
|
||||
const struct clk_ops *ops;
|
||||
|
||||
signed char num_parents;
|
||||
};
|
||||
|
||||
extern const struct clk_ops mtk_mux_ops;
|
||||
extern const struct clk_ops mtk_mux_clr_set_upd_ops;
|
||||
extern const struct clk_ops mtk_mux_gate_ops;
|
||||
extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
|
||||
|
||||
#define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
|
||||
_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
|
||||
_gate, _upd_ofs, _upd, _flags, _ops) { \
|
||||
_gate, _upd_ofs, _upd, _flags) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.mux_ofs = _mux_ofs, \
|
||||
|
|
@ -58,7 +52,6 @@ extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
|
|||
.parent_names = _parents, \
|
||||
.num_parents = ARRAY_SIZE(_parents), \
|
||||
.flags = _flags, \
|
||||
.ops = &_ops, \
|
||||
}
|
||||
|
||||
#define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
|
||||
|
|
@ -66,8 +59,7 @@ extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
|
|||
_gate, _upd_ofs, _upd, _flags) \
|
||||
GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
|
||||
_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
|
||||
_gate, _upd_ofs, _upd, _flags, \
|
||||
mtk_mux_gate_clr_set_upd_ops)
|
||||
_gate, _upd_ofs, _upd, _flags) \
|
||||
|
||||
#define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \
|
||||
_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
|
||||
|
|
|
|||
|
|
@ -1879,7 +1879,6 @@ static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11);
|
|||
static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25);
|
||||
static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
|
||||
static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30);
|
||||
static MESON_GATE(axg_mipi_enable, HHI_MIPI_CNTL0, 29);
|
||||
|
||||
/* Always On (AO) domain gates */
|
||||
|
||||
|
|
@ -1974,7 +1973,6 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = {
|
|||
[CLKID_PCIE_REF] = &axg_pcie_ref.hw,
|
||||
[CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw,
|
||||
[CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw,
|
||||
[CLKID_MIPI_ENABLE] = &axg_mipi_enable.hw,
|
||||
[CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw,
|
||||
[CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw,
|
||||
[CLKID_GEN_CLK] = &axg_gen_clk.hw,
|
||||
|
|
@ -2115,7 +2113,6 @@ static struct clk_regmap *const axg_clk_regmaps[] = {
|
|||
&axg_pcie_ref,
|
||||
&axg_pcie_cml_en0,
|
||||
&axg_pcie_cml_en1,
|
||||
&axg_mipi_enable,
|
||||
&axg_gen_clk_sel,
|
||||
&axg_gen_clk_div,
|
||||
&axg_gen_clk,
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@
|
|||
* Register offsets from the data sheet must be multiplied by 4 before
|
||||
* adding them to the base address to get the right value.
|
||||
*/
|
||||
#define HHI_MIPI_CNTL0 0x00
|
||||
#define HHI_GP0_PLL_CNTL 0x40
|
||||
#define HHI_GP0_PLL_CNTL2 0x44
|
||||
#define HHI_GP0_PLL_CNTL3 0x48
|
||||
|
|
|
|||
|
|
@ -365,13 +365,14 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
{
|
||||
struct clk_regmap *clk = to_clk_regmap(hw);
|
||||
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
|
||||
unsigned int enabled, m, n, frac = 0, ret;
|
||||
unsigned int enabled, m, n, frac = 0;
|
||||
unsigned long old_rate;
|
||||
int ret;
|
||||
|
||||
if (parent_rate == 0 || rate == 0)
|
||||
return -EINVAL;
|
||||
|
||||
old_rate = rate;
|
||||
old_rate = clk_hw_get_rate(hw);
|
||||
|
||||
ret = meson_clk_get_pll_settings(rate, parent_rate, &m, &n, pll);
|
||||
if (ret)
|
||||
|
|
@ -393,7 +394,8 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
if (!enabled)
|
||||
return 0;
|
||||
|
||||
if (meson_clk_pll_enable(hw)) {
|
||||
ret = meson_clk_pll_enable(hw);
|
||||
if (ret) {
|
||||
pr_warn("%s: pll did not lock, trying to restore old rate %lu\n",
|
||||
__func__, old_rate);
|
||||
/*
|
||||
|
|
@ -405,7 +407,7 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
meson_clk_pll_set_rate(hw, old_rate, parent_rate);
|
||||
}
|
||||
|
||||
return 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -52,15 +52,6 @@ static const struct pll_params_table sys_pll_params_table[] = {
|
|||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static struct clk_fixed_rate meson8b_xtal = {
|
||||
.fixed_rate = 24000000,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "xtal",
|
||||
.num_parents = 0,
|
||||
.ops = &clk_fixed_rate_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap meson8b_fixed_pll_dco = {
|
||||
.data = &(struct meson_clk_pll_data){
|
||||
.en = {
|
||||
|
|
@ -2715,7 +2706,6 @@ static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
|
|||
|
||||
static struct clk_hw_onecell_data meson8_hw_onecell_data = {
|
||||
.hws = {
|
||||
[CLKID_XTAL] = &meson8b_xtal.hw,
|
||||
[CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
|
||||
[CLKID_PLL_VID] = &meson8b_vid_pll.hw,
|
||||
[CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
|
||||
|
|
@ -2922,7 +2912,6 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = {
|
|||
|
||||
static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
|
||||
.hws = {
|
||||
[CLKID_XTAL] = &meson8b_xtal.hw,
|
||||
[CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
|
||||
[CLKID_PLL_VID] = &meson8b_vid_pll.hw,
|
||||
[CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
|
||||
|
|
@ -3140,7 +3129,6 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
|
|||
|
||||
static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
|
||||
.hws = {
|
||||
[CLKID_XTAL] = &meson8b_xtal.hw,
|
||||
[CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
|
||||
[CLKID_PLL_VID] = &meson8b_vid_pll.hw,
|
||||
[CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
|
||||
|
|
@ -3725,36 +3713,19 @@ static struct meson8b_nb_data meson8b_cpu_nb_data = {
|
|||
.nb.notifier_call = meson8b_cpu_clk_notifier_cb,
|
||||
};
|
||||
|
||||
static const struct regmap_config clkc_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.val_bits = 32,
|
||||
.reg_stride = 4,
|
||||
};
|
||||
|
||||
static void __init meson8b_clkc_init_common(struct device_node *np,
|
||||
struct clk_hw_onecell_data *clk_hw_onecell_data)
|
||||
{
|
||||
struct meson8b_clk_reset *rstc;
|
||||
const char *notifier_clk_name;
|
||||
struct clk *notifier_clk;
|
||||
void __iomem *clk_base;
|
||||
struct regmap *map;
|
||||
int i, ret;
|
||||
|
||||
map = syscon_node_to_regmap(of_get_parent(np));
|
||||
if (IS_ERR(map)) {
|
||||
pr_info("failed to get HHI regmap - Trying obsolete regs\n");
|
||||
|
||||
/* Generic clocks, PLLs and some of the reset-bits */
|
||||
clk_base = of_iomap(np, 1);
|
||||
if (!clk_base) {
|
||||
pr_err("%s: Unable to map clk base\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
map = regmap_init_mmio(NULL, clk_base, &clkc_regmap_config);
|
||||
if (IS_ERR(map))
|
||||
return;
|
||||
pr_err("failed to get HHI regmap - Trying obsolete regs\n");
|
||||
return;
|
||||
}
|
||||
|
||||
rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
|
||||
|
|
@ -3778,16 +3749,10 @@ static void __init meson8b_clkc_init_common(struct device_node *np,
|
|||
meson8b_clk_regmaps[i]->map = map;
|
||||
|
||||
/*
|
||||
* always skip CLKID_UNUSED and also skip XTAL if the .dtb provides the
|
||||
* XTAL clock as input.
|
||||
* register all clks and start with the first used ID (which is
|
||||
* CLKID_PLL_FIXED)
|
||||
*/
|
||||
if (!IS_ERR(of_clk_get_by_name(np, "xtal")))
|
||||
i = CLKID_PLL_FIXED;
|
||||
else
|
||||
i = CLKID_XTAL;
|
||||
|
||||
/* register all clks */
|
||||
for (; i < CLK_NR_CLKS; i++) {
|
||||
for (i = CLKID_PLL_FIXED; i < CLK_NR_CLKS; i++) {
|
||||
/* array might be sparse */
|
||||
if (!clk_hw_onecell_data->hws[i])
|
||||
continue;
|
||||
|
|
|
|||
|
|
@ -70,7 +70,6 @@
|
|||
#define CLKID_HIFI_PLL 69
|
||||
#define CLKID_PCIE_CML_EN0 79
|
||||
#define CLKID_PCIE_CML_EN1 80
|
||||
#define CLKID_MIPI_ENABLE 81
|
||||
#define CLKID_GEN_CLK 84
|
||||
#define CLKID_VPU_0_SEL 92
|
||||
#define CLKID_VPU_0 93
|
||||
|
|
|
|||
|
|
@ -64,6 +64,8 @@
|
|||
#define IMX_DC0_PLL1_CLK 81
|
||||
#define IMX_DC0_DISP0_CLK 82
|
||||
#define IMX_DC0_DISP1_CLK 83
|
||||
#define IMX_DC0_BYPASS0_CLK 84
|
||||
#define IMX_DC0_BYPASS1_CLK 85
|
||||
|
||||
/* MIPI-LVDS SS */
|
||||
#define IMX_MIPI_IPG_CLK 90
|
||||
|
|
|
|||
|
|
@ -274,6 +274,14 @@
|
|||
|
||||
#define IMX8MM_CLK_A53_CORE 251
|
||||
|
||||
#define IMX8MM_CLK_END 252
|
||||
#define IMX8MM_CLK_CLKOUT1_SEL 252
|
||||
#define IMX8MM_CLK_CLKOUT1_DIV 253
|
||||
#define IMX8MM_CLK_CLKOUT1 254
|
||||
#define IMX8MM_CLK_CLKOUT2_SEL 255
|
||||
#define IMX8MM_CLK_CLKOUT2_DIV 256
|
||||
#define IMX8MM_CLK_CLKOUT2 257
|
||||
|
||||
|
||||
#define IMX8MM_CLK_END 258
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -234,6 +234,13 @@
|
|||
|
||||
#define IMX8MN_CLK_A53_CORE 214
|
||||
|
||||
#define IMX8MN_CLK_END 215
|
||||
#define IMX8MN_CLK_CLKOUT1_SEL 215
|
||||
#define IMX8MN_CLK_CLKOUT1_DIV 216
|
||||
#define IMX8MN_CLK_CLKOUT1 217
|
||||
#define IMX8MN_CLK_CLKOUT2_SEL 218
|
||||
#define IMX8MN_CLK_CLKOUT2_DIV 219
|
||||
#define IMX8MN_CLK_CLKOUT2 220
|
||||
|
||||
#define IMX8MN_CLK_END 221
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -431,6 +431,20 @@
|
|||
|
||||
#define IMX8MQ_CLK_A53_CORE 289
|
||||
|
||||
#define IMX8MQ_CLK_END 290
|
||||
#define IMX8MQ_CLK_MON_AUDIO_PLL1_DIV 290
|
||||
#define IMX8MQ_CLK_MON_AUDIO_PLL2_DIV 291
|
||||
#define IMX8MQ_CLK_MON_VIDEO_PLL1_DIV 292
|
||||
#define IMX8MQ_CLK_MON_GPU_PLL_DIV 293
|
||||
#define IMX8MQ_CLK_MON_VPU_PLL_DIV 294
|
||||
#define IMX8MQ_CLK_MON_ARM_PLL_DIV 295
|
||||
#define IMX8MQ_CLK_MON_SYS_PLL1_DIV 296
|
||||
#define IMX8MQ_CLK_MON_SYS_PLL2_DIV 297
|
||||
#define IMX8MQ_CLK_MON_SYS_PLL3_DIV 298
|
||||
#define IMX8MQ_CLK_MON_DRAM_PLL_DIV 299
|
||||
#define IMX8MQ_CLK_MON_VIDEO_PLL2_DIV 300
|
||||
#define IMX8MQ_CLK_MON_SEL 301
|
||||
#define IMX8MQ_CLK_MON_CLK2_OUT 302
|
||||
|
||||
#define IMX8MQ_CLK_END 303
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
|
||||
|
|
|
|||
|
|
@ -6,8 +6,6 @@
|
|||
#ifndef __MESON8B_CLKC_H
|
||||
#define __MESON8B_CLKC_H
|
||||
|
||||
#define CLKID_UNUSED 0
|
||||
#define CLKID_XTAL 1
|
||||
#define CLKID_PLL_FIXED 2
|
||||
#define CLKID_PLL_VID 3
|
||||
#define CLKID_PLL_SYS 4
|
||||
|
|
|
|||
|
|
@ -0,0 +1,15 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2020 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Author: Lee Jones <lee.jones@linaro.org>
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_CLK_IMX_H
|
||||
#define __LINUX_CLK_IMX_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
void imx6sl_set_wait_clk(bool enter);
|
||||
|
||||
#endif
|
||||
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