[PATCH] PCI: add pci_find_next_capability()
Some devices have more than one capability of the same type. For example, the PCI header for the PathScale InfiniPath looks like: 04:01.0 InfiniBand: Unknown device 1fc1:000d (rev 02) Subsystem: Unknown device 1fc1:000d Flags: bus master, fast devsel, latency 0, IRQ 193 Memory at fea00000 (64-bit, non-prefetchable) [size=2M] Capabilities: [c0] HyperTransport: Slave or Primary Interface Capabilities: [f8] HyperTransport: Interrupt Discovery and Configuration There are _two_ HyperTransport capabilities, and the PathScale driver wants to look at both of them. The current pci_find_capability() API doesn't work for this, since it only allows us to get to the first capability of a given type. The patch below introduces a new pci_find_next_capability(), which can be used in a loop like for (pos = pci_find_capability(pdev, <ID>); pos; pos = pci_find_next_capability(pdev, pos, <ID>)) { /* ... */ } Signed-off-by: Roland Dreier <rolandd@cisco.com> Signed-off-by: Matthew Wilcox <matthew@wil.cx> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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24a4e37706
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@ -63,11 +63,38 @@ pci_max_busnr(void)
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return max;
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}
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static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, u8 pos, int cap)
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{
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u8 id;
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int ttl = 48;
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while (ttl--) {
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pci_bus_read_config_byte(bus, devfn, pos, &pos);
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if (pos < 0x40)
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break;
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pos &= ~3;
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pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
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&id);
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if (id == 0xff)
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break;
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if (id == cap)
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return pos;
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pos += PCI_CAP_LIST_NEXT;
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}
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return 0;
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}
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int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
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{
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return __pci_find_next_cap(dev->bus, dev->devfn,
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pos + PCI_CAP_LIST_NEXT, cap);
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}
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EXPORT_SYMBOL_GPL(pci_find_next_capability);
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static int __pci_bus_find_cap(struct pci_bus *bus, unsigned int devfn, u8 hdr_type, int cap)
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{
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u16 status;
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u8 pos, id;
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int ttl = 48;
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u8 pos;
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pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
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if (!(status & PCI_STATUS_CAP_LIST))
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@ -76,24 +103,15 @@ static int __pci_bus_find_cap(struct pci_bus *bus, unsigned int devfn, u8 hdr_ty
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switch (hdr_type) {
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case PCI_HEADER_TYPE_NORMAL:
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case PCI_HEADER_TYPE_BRIDGE:
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pci_bus_read_config_byte(bus, devfn, PCI_CAPABILITY_LIST, &pos);
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pos = PCI_CAPABILITY_LIST;
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break;
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case PCI_HEADER_TYPE_CARDBUS:
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pci_bus_read_config_byte(bus, devfn, PCI_CB_CAPABILITY_LIST, &pos);
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pos = PCI_CB_CAPABILITY_LIST;
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break;
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default:
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return 0;
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}
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while (ttl-- && pos >= 0x40) {
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pos &= ~3;
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pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, &id);
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if (id == 0xff)
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break;
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if (id == cap)
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return pos;
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pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_NEXT, &pos);
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}
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return 0;
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return __pci_find_next_cap(bus, devfn, pos, cap);
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}
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/**
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@ -338,6 +338,7 @@ struct pci_dev *pci_find_device (unsigned int vendor, unsigned int device, const
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struct pci_dev *pci_find_device_reverse (unsigned int vendor, unsigned int device, const struct pci_dev *from);
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struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn);
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int pci_find_capability (struct pci_dev *dev, int cap);
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int pci_find_next_capability (struct pci_dev *dev, u8 pos, int cap);
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int pci_find_ext_capability (struct pci_dev *dev, int cap);
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struct pci_bus * pci_find_next_bus(const struct pci_bus *from);
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@ -550,6 +551,7 @@ static inline int pci_assign_resource(struct pci_dev *dev, int i) { return -EBUS
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static inline int pci_register_driver(struct pci_driver *drv) { return 0;}
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static inline void pci_unregister_driver(struct pci_driver *drv) { }
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static inline int pci_find_capability (struct pci_dev *dev, int cap) {return 0; }
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static inline int pci_find_next_capability (struct pci_dev *dev, u8 post, int cap) { return 0; }
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static inline int pci_find_ext_capability (struct pci_dev *dev, int cap) {return 0; }
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static inline const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev) { return NULL; }
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