spi: Fixes for v3.16
A few driver specific fixes, the biggest one being a fix for the newly added Qualcomm SPI controller driver to make it not use its internal chip select due to hardware bugs, replacing it with GPIOs. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJTrr4lAAoJELSic+t+oim9/30P/3wie8c4eNjRQLPYrNmq9y1t S9sF6U6ur3mDD1GXol1hoe3FU3aaF9TiNU8sq8wtj2TCvmB6BLlH70uKdIIbKB4B b1WVNoclBTZYE3v8FdsJce5eyBjaNY90cRJ5TGwwIWowSNuWwo0/+1zWWzzyH9AF u2STutPSZAJL99RRnUZj+5zx9cspTnc+TNX5UFIXbRcvLPnYkg8TeQvXFUAH9CgL p0sbveu8C3ZS2es5h1Py/f9v0/Pv00fGCVNW073JA82I5viUAogI5+63e65kKZcm xjdY4yIrIrsORjbpUny7YjkgdxdpAWjO4IFnFdPT4GZBe9Ad7ACYKfiox/q/EO7O H8z8v6Ebq/6+wV9uvZtSTIWd2PRV7YUsYijTZGFN02+f4QQq5OckgQMD0ODOBb4k uI1qiTcd11g1gXlExne23fzvBzpCfD1h2N8h/DyXRBhlyb9NupaABjqVP/fkds5g k5j6VuYcGy3UZeGmSOrx85d5pWgOBp/hDJ8DwWo9AUGPrnDx9HgAerxhNMXaJcQA PFypfT2L23ACxbTSZmAj2uRbKv4zyiqM+xtxdLmY/KrvpuDoKAlDGtZV1TFeNo7c 4H3c96fAc/i0BsinY3b1weQ+oGNcNWv9nvdqVGxuBvWs862HkvUcP5mB5ki5BGxh h3uVSfQeETPizC+3w52A =Jdak -----END PGP SIGNATURE----- Merge tag 'spi-v3.16-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fixes from Mark Brown: "A few driver specific fixes, the biggest one being a fix for the newly added Qualcomm SPI controller driver to make it not use its internal chip select due to hardware bugs, replacing it with GPIOs" * tag 'spi-v3.16-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: qup: Remove chip select function spi: qup: Fix order of spi_register_master spi: sh-sci: fix use-after-free in sh_sci_spi_remove() spi/pxa2xx: fix incorrect SW mode chipselect setting for BayTrail LPSS SPI
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24b414d5a7
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@ -23,6 +23,12 @@ Optional properties:
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- spi-max-frequency: Specifies maximum SPI clock frequency,
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Units - Hz. Definition as per
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Documentation/devicetree/bindings/spi/spi-bus.txt
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- num-cs: total number of chipselects
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- cs-gpios: should specify GPIOs used for chipselects.
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The gpios will be referred to as reg = <index> in the SPI child
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nodes. If unspecified, a single SPI device without a chip
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select can be used.
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SPI slave nodes must be children of the SPI master node and can contain
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properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
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@ -118,6 +118,7 @@ static void lpss_ssp_setup(struct driver_data *drv_data)
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*/
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orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
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/* Test SPI_CS_CONTROL_SW_MODE bit enabling */
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value = orig | SPI_CS_CONTROL_SW_MODE;
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writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
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value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
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@ -126,10 +127,13 @@ static void lpss_ssp_setup(struct driver_data *drv_data)
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goto detection_done;
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}
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value &= ~SPI_CS_CONTROL_SW_MODE;
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orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
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/* Test SPI_CS_CONTROL_SW_MODE bit disabling */
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value = orig & ~SPI_CS_CONTROL_SW_MODE;
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writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
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value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
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if (value != orig) {
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if (value != (orig & ~SPI_CS_CONTROL_SW_MODE)) {
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offset = 0x800;
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goto detection_done;
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}
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@ -424,31 +424,6 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
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return 0;
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}
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static void spi_qup_set_cs(struct spi_device *spi, bool enable)
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{
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struct spi_qup *controller = spi_master_get_devdata(spi->master);
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u32 iocontol, mask;
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iocontol = readl_relaxed(controller->base + SPI_IO_CONTROL);
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/* Disable auto CS toggle and use manual */
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iocontol &= ~SPI_IO_C_MX_CS_MODE;
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iocontol |= SPI_IO_C_FORCE_CS;
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iocontol &= ~SPI_IO_C_CS_SELECT_MASK;
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iocontol |= SPI_IO_C_CS_SELECT(spi->chip_select);
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mask = SPI_IO_C_CS_N_POLARITY_0 << spi->chip_select;
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if (enable)
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iocontol |= mask;
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else
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iocontol &= ~mask;
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writel_relaxed(iocontol, controller->base + SPI_IO_CONTROL);
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}
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static int spi_qup_transfer_one(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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@ -571,12 +546,16 @@ static int spi_qup_probe(struct platform_device *pdev)
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return -ENOMEM;
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}
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/* use num-cs unless not present or out of range */
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if (of_property_read_u16(dev->of_node, "num-cs",
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&master->num_chipselect) ||
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(master->num_chipselect > SPI_NUM_CHIPSELECTS))
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master->num_chipselect = SPI_NUM_CHIPSELECTS;
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master->bus_num = pdev->id;
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master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
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master->num_chipselect = SPI_NUM_CHIPSELECTS;
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master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
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master->max_speed_hz = max_freq;
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master->set_cs = spi_qup_set_cs;
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master->transfer_one = spi_qup_transfer_one;
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master->dev.of_node = pdev->dev.of_node;
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master->auto_runtime_pm = true;
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@ -640,16 +619,19 @@ static int spi_qup_probe(struct platform_device *pdev)
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if (ret)
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goto error;
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ret = devm_spi_register_master(dev, master);
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if (ret)
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goto error;
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pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC);
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pm_runtime_use_autosuspend(dev);
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pm_runtime_set_active(dev);
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pm_runtime_enable(dev);
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ret = devm_spi_register_master(dev, master);
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if (ret)
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goto disable_pm;
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return 0;
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disable_pm:
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pm_runtime_disable(&pdev->dev);
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error:
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clk_disable_unprepare(cclk);
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clk_disable_unprepare(iclk);
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@ -175,9 +175,9 @@ static int sh_sci_spi_remove(struct platform_device *dev)
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{
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struct sh_sci_spi *sp = platform_get_drvdata(dev);
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iounmap(sp->membase);
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setbits(sp, PIN_INIT, 0);
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spi_bitbang_stop(&sp->bitbang);
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setbits(sp, PIN_INIT, 0);
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iounmap(sp->membase);
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spi_master_put(sp->bitbang.master);
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return 0;
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}
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