clk: tegra: Add aclk
This clock clocks the ADSP Cortex-A9. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Коммит
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@ -2308,6 +2308,11 @@ static struct tegra_audio_clk_info tegra210_audio_plls[] = {
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static struct clk **clks;
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static const char * const aclk_parents[] = {
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"pll_a1", "pll_c", "pll_p", "pll_a_out0", "pll_c2", "pll_c3",
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"clk_m"
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};
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static __init void tegra210_periph_clk_init(void __iomem *clk_base,
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void __iomem *pmc_base)
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{
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@ -2369,6 +2374,11 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
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clk_register_clkdev(clk, "cml1", NULL);
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clks[TEGRA210_CLK_CML1] = clk;
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clk = tegra_clk_register_super_clk("aclk", aclk_parents,
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ARRAY_SIZE(aclk_parents), 0, clk_base + 0x6e0,
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0, NULL);
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clks[TEGRA210_CLK_ACLK] = clk;
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tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params);
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}
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@ -396,6 +396,8 @@
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#define TEGRA210_CLK_PLL_C_UD 364
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#define TEGRA210_CLK_SCLK_MUX 365
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#define TEGRA210_CLK_ACLK 370
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#define TEGRA210_CLK_DMIC1_SYNC_CLK 388
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#define TEGRA210_CLK_DMIC1_SYNC_CLK_MUX 389
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#define TEGRA210_CLK_DMIC2_SYNC_CLK 390
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