nand/denali: use iowrite32() to replace denali_write32()
denali_write32() just implements a debug function for iowrite32(), only print out the write value. Remove this function since it's useless Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
Chuanxiao Dong
David Woodhouse
Родитель
5c0eb90094
Коммит
24c3fa36de
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@ -132,20 +132,6 @@ static uint32_t read_interrupt_status(struct denali_nand_info *denali);
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#define DEBUG_DENALI 0
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/* This is a wrapper for writing to the denali registers.
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* this allows us to create debug information so we can
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* observe how the driver is programming the device.
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* it uses standard linux convention for (val, addr) */
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static void denali_write32(uint32_t value, void *addr)
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{
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iowrite32(value, addr);
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#if DEBUG_DENALI
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printk(KERN_INFO "wrote: 0x%x -> 0x%x\n", value,
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(uint32_t)((uint32_t)addr & 0x1fff));
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#endif
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}
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/* Certain operations for the denali NAND controller use
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* an indexed mode to read/write data. The operation is
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* performed by writing the address value of the command
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@ -155,15 +141,15 @@ static void denali_write32(uint32_t value, void *addr)
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static void index_addr(struct denali_nand_info *denali,
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uint32_t address, uint32_t data)
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{
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denali_write32(address, denali->flash_mem);
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denali_write32(data, denali->flash_mem + 0x10);
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iowrite32(address, denali->flash_mem);
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iowrite32(data, denali->flash_mem + 0x10);
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}
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/* Perform an indexed read of the device */
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static void index_addr_read_data(struct denali_nand_info *denali,
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uint32_t address, uint32_t *pdata)
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{
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denali_write32(address, denali->flash_mem);
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iowrite32(address, denali->flash_mem);
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*pdata = ioread32(denali->flash_mem + 0x10);
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}
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@ -191,7 +177,7 @@ static void read_status(struct denali_nand_info *denali)
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/* initiate a device status read */
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cmd = MODE_11 | BANK(denali->flash_bank);
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index_addr(denali, cmd | COMMAND_CYCLE, 0x70);
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denali_write32(cmd | STATUS_CYCLE, denali->flash_mem);
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iowrite32(cmd | STATUS_CYCLE, denali->flash_mem);
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/* update buffer with status value */
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write_byte_to_buf(denali, ioread32(denali->flash_mem + 0x10));
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@ -213,7 +199,7 @@ static void reset_bank(struct denali_nand_info *denali)
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clear_interrupts(denali);
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bank = device_reset_banks[denali->flash_bank];
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denali_write32(bank, denali->flash_reg + DEVICE_RESET);
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iowrite32(bank, denali->flash_reg + DEVICE_RESET);
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irq_status = wait_for_irq(denali, irq_mask);
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@ -230,11 +216,11 @@ static uint16_t denali_nand_reset(struct denali_nand_info *denali)
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__FILE__, __LINE__, __func__);
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for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++)
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denali_write32(reset_complete[i] | operation_timeout[i],
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iowrite32(reset_complete[i] | operation_timeout[i],
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denali->flash_reg + intr_status_addresses[i]);
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for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) {
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denali_write32(device_reset_banks[i],
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iowrite32(device_reset_banks[i],
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denali->flash_reg + DEVICE_RESET);
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while (!(ioread32(denali->flash_reg +
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intr_status_addresses[i]) &
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@ -247,7 +233,7 @@ static uint16_t denali_nand_reset(struct denali_nand_info *denali)
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}
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for (i = 0; i < LLD_MAX_FLASH_BANKS; i++)
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denali_write32(reset_complete[i] | operation_timeout[i],
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iowrite32(reset_complete[i] | operation_timeout[i],
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denali->flash_reg + intr_status_addresses[i]);
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return PASS;
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@ -345,14 +331,14 @@ static void nand_onfi_timing_set(struct denali_nand_info *denali,
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(ioread32(denali->flash_reg + DEVICE_ID) == 0x88))
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acc_clks = 6;
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denali_write32(acc_clks, denali->flash_reg + ACC_CLKS);
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denali_write32(re_2_we, denali->flash_reg + RE_2_WE);
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denali_write32(re_2_re, denali->flash_reg + RE_2_RE);
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denali_write32(we_2_re, denali->flash_reg + WE_2_RE);
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denali_write32(addr_2_data, denali->flash_reg + ADDR_2_DATA);
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denali_write32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
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denali_write32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
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denali_write32(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
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iowrite32(acc_clks, denali->flash_reg + ACC_CLKS);
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iowrite32(re_2_we, denali->flash_reg + RE_2_WE);
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iowrite32(re_2_re, denali->flash_reg + RE_2_RE);
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iowrite32(we_2_re, denali->flash_reg + WE_2_RE);
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iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA);
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iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
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iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
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iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
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}
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/* queries the NAND device to see what ONFI modes it supports. */
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@ -387,13 +373,13 @@ static void get_samsung_nand_para(struct denali_nand_info *denali,
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{
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if (device_id == 0xd3) { /* Samsung K9WAG08U1A */
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/* Set timing register values according to datasheet */
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denali_write32(5, denali->flash_reg + ACC_CLKS);
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denali_write32(20, denali->flash_reg + RE_2_WE);
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denali_write32(12, denali->flash_reg + WE_2_RE);
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denali_write32(14, denali->flash_reg + ADDR_2_DATA);
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denali_write32(3, denali->flash_reg + RDWR_EN_LO_CNT);
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denali_write32(2, denali->flash_reg + RDWR_EN_HI_CNT);
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denali_write32(2, denali->flash_reg + CS_SETUP_CNT);
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iowrite32(5, denali->flash_reg + ACC_CLKS);
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iowrite32(20, denali->flash_reg + RE_2_WE);
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iowrite32(12, denali->flash_reg + WE_2_RE);
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iowrite32(14, denali->flash_reg + ADDR_2_DATA);
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iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT);
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iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT);
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iowrite32(2, denali->flash_reg + CS_SETUP_CNT);
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}
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}
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@ -405,15 +391,15 @@ static void get_toshiba_nand_para(struct denali_nand_info *denali)
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/* spare area size for some kind of Toshiba NAND device */
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if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
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(ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {
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denali_write32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
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iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
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tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) *
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ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
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denali_write32(tmp,
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iowrite32(tmp,
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denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
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#if SUPPORT_15BITECC
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denali_write32(15, denali->flash_reg + ECC_CORRECTION);
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iowrite32(15, denali->flash_reg + ECC_CORRECTION);
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#elif SUPPORT_8BITECC
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denali_write32(8, denali->flash_reg + ECC_CORRECTION);
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iowrite32(8, denali->flash_reg + ECC_CORRECTION);
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#endif
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}
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}
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@ -426,22 +412,22 @@ static void get_hynix_nand_para(struct denali_nand_info *denali,
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switch (device_id) {
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case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
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case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
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denali_write32(128, denali->flash_reg + PAGES_PER_BLOCK);
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denali_write32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
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denali_write32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
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iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK);
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iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
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iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
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main_size = 4096 *
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ioread32(denali->flash_reg + DEVICES_CONNECTED);
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spare_size = 224 *
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ioread32(denali->flash_reg + DEVICES_CONNECTED);
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denali_write32(main_size,
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iowrite32(main_size,
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denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
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denali_write32(spare_size,
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iowrite32(spare_size,
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denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
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denali_write32(0, denali->flash_reg + DEVICE_WIDTH);
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iowrite32(0, denali->flash_reg + DEVICE_WIDTH);
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#if SUPPORT_15BITECC
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denali_write32(15, denali->flash_reg + ECC_CORRECTION);
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iowrite32(15, denali->flash_reg + ECC_CORRECTION);
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#elif SUPPORT_8BITECC
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denali_write32(8, denali->flash_reg + ECC_CORRECTION);
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iowrite32(8, denali->flash_reg + ECC_CORRECTION);
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#endif
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break;
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default:
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@ -586,9 +572,9 @@ static void denali_set_intr_modes(struct denali_nand_info *denali,
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__FILE__, __LINE__, __func__);
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if (INT_ENABLE)
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denali_write32(1, denali->flash_reg + GLOBAL_INT_ENABLE);
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iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE);
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else
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denali_write32(0, denali->flash_reg + GLOBAL_INT_ENABLE);
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iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE);
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}
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/* validation function to verify that the controlling software is making
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@ -609,10 +595,10 @@ static void denali_irq_init(struct denali_nand_info *denali)
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int_mask = DENALI_IRQ_ALL;
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/* Clear all status bits */
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denali_write32(0xFFFF, denali->flash_reg + INTR_STATUS0);
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denali_write32(0xFFFF, denali->flash_reg + INTR_STATUS1);
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denali_write32(0xFFFF, denali->flash_reg + INTR_STATUS2);
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denali_write32(0xFFFF, denali->flash_reg + INTR_STATUS3);
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iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS0);
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iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS1);
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iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS2);
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iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS3);
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denali_irq_enable(denali, int_mask);
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}
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@ -626,10 +612,10 @@ static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali)
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static void denali_irq_enable(struct denali_nand_info *denali,
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uint32_t int_mask)
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{
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denali_write32(int_mask, denali->flash_reg + INTR_EN0);
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denali_write32(int_mask, denali->flash_reg + INTR_EN1);
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denali_write32(int_mask, denali->flash_reg + INTR_EN2);
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denali_write32(int_mask, denali->flash_reg + INTR_EN3);
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iowrite32(int_mask, denali->flash_reg + INTR_EN0);
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iowrite32(int_mask, denali->flash_reg + INTR_EN1);
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iowrite32(int_mask, denali->flash_reg + INTR_EN2);
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iowrite32(int_mask, denali->flash_reg + INTR_EN3);
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}
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/* This function only returns when an interrupt that this driver cares about
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@ -648,7 +634,7 @@ static inline void clear_interrupt(struct denali_nand_info *denali,
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intr_status_reg = intr_status_addresses[denali->flash_bank];
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denali_write32(irq_mask, denali->flash_reg + intr_status_reg);
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iowrite32(irq_mask, denali->flash_reg + intr_status_reg);
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}
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static void clear_interrupts(struct denali_nand_info *denali)
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@ -800,8 +786,8 @@ static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
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transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;
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/* Enable spare area/ECC per user's request. */
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denali_write32(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
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denali_write32(transfer_spare_flag,
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iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
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iowrite32(transfer_spare_flag,
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denali->flash_reg + TRANSFER_SPARE_REG);
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}
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@ -844,14 +830,14 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
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if (op == DENALI_WRITE && access_type != SPARE_ACCESS) {
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cmd = MODE_01 | addr;
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denali_write32(cmd, denali->flash_mem);
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iowrite32(cmd, denali->flash_mem);
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} else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) {
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/* read spare area */
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cmd = MODE_10 | addr;
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index_addr(denali, (uint32_t)cmd, access_type);
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cmd = MODE_01 | addr;
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denali_write32(cmd, denali->flash_mem);
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iowrite32(cmd, denali->flash_mem);
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} else if (op == DENALI_READ) {
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/* setup page read request for access type */
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cmd = MODE_10 | addr;
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@ -863,7 +849,7 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
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*/
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if (access_type == SPARE_ACCESS) {
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cmd = MODE_01 | addr;
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denali_write32(cmd, denali->flash_mem);
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iowrite32(cmd, denali->flash_mem);
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} else {
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index_addr(denali, (uint32_t)cmd,
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0x2000 | op | page_count);
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@ -881,7 +867,7 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
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status = FAIL;
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} else {
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cmd = MODE_01 | addr;
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denali_write32(cmd, denali->flash_mem);
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iowrite32(cmd, denali->flash_mem);
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}
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}
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}
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@ -902,7 +888,7 @@ static int write_data_to_flash_mem(struct denali_nand_info *denali,
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/* write the data to the flash memory */
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buf32 = (uint32_t *)buf;
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for (i = 0; i < len / 4; i++)
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denali_write32(*buf32++, denali->flash_mem + 0x10);
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iowrite32(*buf32++, denali->flash_mem + 0x10);
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return i*4; /* intent is to return the number of bytes read */
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}
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@ -1100,7 +1086,7 @@ static void denali_enable_dma(struct denali_nand_info *denali, bool en)
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if (en)
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reg_val = DMA_ENABLE__FLAG;
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denali_write32(reg_val, denali->flash_reg + DMA_ENABLE);
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iowrite32(reg_val, denali->flash_reg + DMA_ENABLE);
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ioread32(denali->flash_reg + DMA_ENABLE);
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}
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@ -1447,16 +1433,16 @@ static void denali_hw_init(struct denali_nand_info *denali)
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SPARE_AREA_SKIP_BYTES);
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denali_irq_init(denali);
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denali_nand_reset(denali);
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denali_write32(0x0F, denali->flash_reg + RB_PIN_ENABLED);
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denali_write32(CHIP_EN_DONT_CARE__FLAG,
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iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED);
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iowrite32(CHIP_EN_DONT_CARE__FLAG,
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denali->flash_reg + CHIP_ENABLE_DONT_CARE);
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denali_write32(0x0, denali->flash_reg + SPARE_AREA_SKIP_BYTES);
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denali_write32(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
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iowrite32(0x0, denali->flash_reg + SPARE_AREA_SKIP_BYTES);
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iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
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/* Should set value for these registers when init */
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denali_write32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
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denali_write32(1, denali->flash_reg + ECC_ENABLE);
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iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
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iowrite32(1, denali->flash_reg + ECC_ENABLE);
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}
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/* Althogh controller spec said SLC ECC is forceb to be 4bit,
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@ -1718,7 +1704,7 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
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/* if MLC OOB size is large enough, use 15bit ECC*/
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denali->nand.ecc.layout = &nand_15bit_oob;
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denali->nand.ecc.bytes = ECC_15BITS;
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denali_write32(15, denali->flash_reg + ECC_CORRECTION);
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iowrite32(15, denali->flash_reg + ECC_CORRECTION);
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} else if (denali->mtd.oobsize < (denali->bbtskipbytes +
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ECC_8BITS * (denali->mtd.writesize /
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ECC_SECTOR_SIZE))) {
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@ -1728,7 +1714,7 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
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} else {
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denali->nand.ecc.layout = &nand_8bit_oob;
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denali->nand.ecc.bytes = ECC_8BITS;
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denali_write32(8, denali->flash_reg + ECC_CORRECTION);
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iowrite32(8, denali->flash_reg + ECC_CORRECTION);
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}
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||||
|
||||
denali->nand.ecc.bytes *= denali->devnum;
|
||||
|
|
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|||
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