net: mvpp2: use resolved link config in mac_link_up()
Convert the Marvell mvpp2 ethernet driver to use the finalised link parameters in mac_link_up() rather than the parameters in mac_config(). Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Russell King
David S. Miller
Родитель
ff03f0b152
Коммит
24cb72df1a
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@ -4976,15 +4976,13 @@ static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
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old_ctrl2 = ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
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old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
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an &= ~(MVPP2_GMAC_CONFIG_MII_SPEED | MVPP2_GMAC_CONFIG_GMII_SPEED |
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MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FC_ADV_EN |
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an &= ~(MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FC_ADV_EN |
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MVPP2_GMAC_FC_ADV_ASM_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG |
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MVPP2_GMAC_CONFIG_FULL_DUPLEX | MVPP2_GMAC_AN_DUPLEX_EN |
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MVPP2_GMAC_IN_BAND_AUTONEG | MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS);
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MVPP2_GMAC_AN_DUPLEX_EN | MVPP2_GMAC_IN_BAND_AUTONEG |
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MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS);
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ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK;
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ctrl2 &= ~(MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PORT_RESET_MASK |
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MVPP2_GMAC_PCS_ENABLE_MASK);
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ctrl4 &= ~(MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN);
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/* Configure port type */
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if (phy_interface_mode_is_8023z(state->interface)) {
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@ -5014,31 +5012,20 @@ static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
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/* Configure negotiation style */
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if (!phylink_autoneg_inband(mode)) {
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/* Phy or fixed speed - no in-band AN */
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if (state->duplex)
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an |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
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if (state->speed == SPEED_1000 || state->speed == SPEED_2500)
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an |= MVPP2_GMAC_CONFIG_GMII_SPEED;
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else if (state->speed == SPEED_100)
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an |= MVPP2_GMAC_CONFIG_MII_SPEED;
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if (state->pause & MLO_PAUSE_TX)
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ctrl4 |= MVPP22_CTRL4_TX_FC_EN;
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if (state->pause & MLO_PAUSE_RX)
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ctrl4 |= MVPP22_CTRL4_RX_FC_EN;
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/* Phy or fixed speed - no in-band AN, nothing to do, leave the
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* configured speed, duplex and flow control as-is.
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*/
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} else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
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/* SGMII in-band mode receives the speed and duplex from
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* the PHY. Flow control information is not received. */
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an &= ~(MVPP2_GMAC_FORCE_LINK_DOWN | MVPP2_GMAC_FORCE_LINK_PASS);
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an &= ~(MVPP2_GMAC_FORCE_LINK_DOWN |
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MVPP2_GMAC_FORCE_LINK_PASS |
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MVPP2_GMAC_CONFIG_MII_SPEED |
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MVPP2_GMAC_CONFIG_GMII_SPEED |
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MVPP2_GMAC_CONFIG_FULL_DUPLEX);
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an |= MVPP2_GMAC_IN_BAND_AUTONEG |
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MVPP2_GMAC_AN_SPEED_EN |
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MVPP2_GMAC_AN_DUPLEX_EN;
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if (state->pause & MLO_PAUSE_TX)
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ctrl4 |= MVPP22_CTRL4_TX_FC_EN;
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if (state->pause & MLO_PAUSE_RX)
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ctrl4 |= MVPP22_CTRL4_RX_FC_EN;
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} else if (phy_interface_mode_is_8023z(state->interface)) {
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/* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can
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* they negotiate duplex: they are always operating with a fixed
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@ -5046,19 +5033,17 @@ static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
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* speed and full duplex here.
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*/
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ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK;
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an &= ~(MVPP2_GMAC_FORCE_LINK_DOWN | MVPP2_GMAC_FORCE_LINK_PASS);
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an &= ~(MVPP2_GMAC_FORCE_LINK_DOWN |
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MVPP2_GMAC_FORCE_LINK_PASS |
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MVPP2_GMAC_CONFIG_MII_SPEED |
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MVPP2_GMAC_CONFIG_GMII_SPEED |
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MVPP2_GMAC_CONFIG_FULL_DUPLEX);
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an |= MVPP2_GMAC_IN_BAND_AUTONEG |
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MVPP2_GMAC_CONFIG_GMII_SPEED |
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MVPP2_GMAC_CONFIG_FULL_DUPLEX;
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if (state->pause & MLO_PAUSE_AN && state->an_enabled) {
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if (state->pause & MLO_PAUSE_AN && state->an_enabled)
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an |= MVPP2_GMAC_FLOW_CTRL_AUTONEG;
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} else {
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if (state->pause & MLO_PAUSE_TX)
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ctrl4 |= MVPP22_CTRL4_TX_FC_EN;
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if (state->pause & MLO_PAUSE_RX)
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ctrl4 |= MVPP22_CTRL4_RX_FC_EN;
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}
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}
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/* Some fields of the auto-negotiation register require the port to be down when
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@ -5155,18 +5140,44 @@ static void mvpp2_mac_link_up(struct phylink_config *config,
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struct mvpp2_port *port = netdev_priv(dev);
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u32 val;
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if (!phylink_autoneg_inband(mode)) {
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if (mvpp2_is_xlg(interface)) {
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if (mvpp2_is_xlg(interface)) {
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if (!phylink_autoneg_inband(mode)) {
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val = readl(port->base + MVPP22_XLG_CTRL0_REG);
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val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_DOWN;
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val |= MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
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writel(val, port->base + MVPP22_XLG_CTRL0_REG);
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} else {
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}
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} else {
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if (!phylink_autoneg_inband(mode)) {
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val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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val &= ~MVPP2_GMAC_FORCE_LINK_DOWN;
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val &= ~(MVPP2_GMAC_FORCE_LINK_DOWN |
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MVPP2_GMAC_CONFIG_MII_SPEED |
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MVPP2_GMAC_CONFIG_GMII_SPEED |
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MVPP2_GMAC_CONFIG_FULL_DUPLEX);
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val |= MVPP2_GMAC_FORCE_LINK_PASS;
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if (speed == SPEED_1000 || speed == SPEED_2500)
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val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
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else if (speed == SPEED_100)
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val |= MVPP2_GMAC_CONFIG_MII_SPEED;
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if (duplex == DUPLEX_FULL)
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val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
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writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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}
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/* We can always update the flow control enable bits;
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* these will only be effective if flow control AN
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* (MVPP2_GMAC_FLOW_CTRL_AUTONEG) is disabled.
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*/
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val = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
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val &= ~(MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN);
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if (tx_pause)
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val |= MVPP22_CTRL4_TX_FC_EN;
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if (rx_pause)
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val |= MVPP22_CTRL4_RX_FC_EN;
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writel(val, port->base + MVPP22_GMAC_CTRL_4_REG);
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}
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mvpp2_port_enable(port);
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