Merge branch 'dm814x-soc' into omap-for-v4.3/soc
Update dm814x changes for sparse fixes to make data structures static. Conflicts: arch/arm/mach-omap2/omap_hwmod_81xx_data.c
This commit is contained in:
Коммит
24da741c67
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@ -169,7 +169,7 @@ static const char *const ti814x_boards_compat[] __initconst = {
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NULL,
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};
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DT_MACHINE_START(TI81XX_DT, "Generic ti814x (Flattened Device Tree)")
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DT_MACHINE_START(TI814X_DT, "Generic ti814x (Flattened Device Tree)")
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.reserve = omap_reserve,
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.map_io = ti81xx_map_io,
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.init_early = ti814x_init_early,
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@ -216,7 +216,8 @@ extern void __init omap242x_clockdomains_init(void);
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extern void __init omap243x_clockdomains_init(void);
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extern void __init omap3xxx_clockdomains_init(void);
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extern void __init am33xx_clockdomains_init(void);
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extern void __init ti81xx_clockdomains_init(void);
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extern void __init ti814x_clockdomains_init(void);
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extern void __init ti816x_clockdomains_init(void);
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extern void __init omap44xx_clockdomains_init(void);
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extern void __init omap54xx_clockdomains_init(void);
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extern void __init dra7xx_clockdomains_init(void);
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@ -165,7 +165,24 @@ static struct clockdomain default_l3_slow_816x_clkdm = {
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.flags = CLKDM_CAN_SWSUP,
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};
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static struct clockdomain *clockdomains_ti81xx[] __initdata = {
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static struct clockdomain *clockdomains_ti814x[] __initdata = {
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&alwon_l3_slow_81xx_clkdm,
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&alwon_l3_med_81xx_clkdm,
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&alwon_l3_fast_81xx_clkdm,
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&alwon_ethernet_81xx_clkdm,
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&mmu_81xx_clkdm,
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&mmu_cfg_81xx_clkdm,
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NULL,
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};
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void __init ti814x_clockdomains_init(void)
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{
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clkdm_register_platform_funcs(&am33xx_clkdm_operations);
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clkdm_register_clkdms(clockdomains_ti814x);
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clkdm_complete_init();
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}
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static struct clockdomain *clockdomains_ti816x[] __initdata = {
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&alwon_mpu_816x_clkdm,
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&alwon_l3_slow_81xx_clkdm,
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&alwon_l3_med_81xx_clkdm,
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@ -185,10 +202,10 @@ static struct clockdomain *clockdomains_ti81xx[] __initdata = {
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NULL,
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};
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void __init ti81xx_clockdomains_init(void)
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void __init ti816x_clockdomains_init(void)
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{
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clkdm_register_platform_funcs(&am33xx_clkdm_operations);
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clkdm_register_clkdms(clockdomains_ti81xx);
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clkdm_register_clkdms(clockdomains_ti816x);
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clkdm_complete_init();
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}
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#endif
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@ -652,6 +652,7 @@ static const struct of_device_id omap_scrm_dt_match_table[] = {
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{ .compatible = "ti,am4-scm", .data = &ctrl_data },
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{ .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data },
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{ .compatible = "ti,omap3-scm", .data = &omap2_ctrl_data },
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{ .compatible = "ti,dm814-scm", .data = &ctrl_data },
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{ .compatible = "ti,dm816-scrm", .data = &ctrl_data },
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{ .compatible = "ti,omap4-scm-core", .data = &ctrl_data },
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{ .compatible = "ti,omap5-scm-core", .data = &ctrl_data },
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@ -608,11 +608,11 @@ void __init ti814x_init_early(void)
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omap2_prcm_base_init();
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omap3xxx_voltagedomains_init();
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omap3xxx_powerdomains_init();
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ti81xx_clockdomains_init();
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ti81xx_hwmod_init();
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ti814x_clockdomains_init();
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dm814x_hwmod_init();
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omap_hwmod_init_postsetup();
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if (of_have_populated_dt())
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omap_clk_soc_init = ti81xx_dt_clk_init;
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omap_clk_soc_init = dm814x_dt_clk_init;
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}
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void __init ti816x_init_early(void)
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@ -625,11 +625,11 @@ void __init ti816x_init_early(void)
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omap2_prcm_base_init();
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omap3xxx_voltagedomains_init();
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omap3xxx_powerdomains_init();
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ti81xx_clockdomains_init();
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ti81xx_hwmod_init();
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ti816x_clockdomains_init();
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dm816x_hwmod_init();
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omap_hwmod_init_postsetup();
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if (of_have_populated_dt())
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omap_clk_soc_init = ti81xx_dt_clk_init;
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omap_clk_soc_init = dm816x_dt_clk_init;
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}
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#endif
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@ -3891,7 +3891,8 @@ void __init omap_hwmod_init(void)
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soc_ops.init_clkdm = _init_clkdm;
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soc_ops.update_context_lost = _omap4_update_context_lost;
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soc_ops.get_context_lost = _omap4_get_context_lost;
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} else if (cpu_is_ti816x() || soc_is_am33xx() || soc_is_am43xx()) {
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} else if (cpu_is_ti814x() || cpu_is_ti816x() || soc_is_am33xx() ||
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soc_is_am43xx()) {
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soc_ops.enable_module = _omap4_enable_module;
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soc_ops.disable_module = _omap4_disable_module;
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soc_ops.wait_target_ready = _omap4_wait_target_ready;
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@ -759,7 +759,8 @@ extern int omap3xxx_hwmod_init(void);
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extern int omap44xx_hwmod_init(void);
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extern int omap54xx_hwmod_init(void);
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extern int am33xx_hwmod_init(void);
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extern int ti81xx_hwmod_init(void);
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extern int dm814x_hwmod_init(void);
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extern int dm816x_hwmod_init(void);
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extern int dra7xx_hwmod_init(void);
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int am43xx_hwmod_init(void);
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Разница между файлами не показана из-за своего большого размера
Загрузить разницу
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@ -349,6 +349,41 @@ static struct powerdomain device_81xx_pwrdm = {
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.voltdm = { .name = "core" },
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};
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static struct powerdomain gem_814x_pwrdm = {
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.name = "gem_pwrdm",
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.prcm_offs = TI814X_PRM_DSP_MOD,
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.pwrsts = PWRSTS_OFF_ON,
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.voltdm = { .name = "dsp" },
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};
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static struct powerdomain ivahd_814x_pwrdm = {
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.name = "ivahd_pwrdm",
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.prcm_offs = TI814X_PRM_HDVICP_MOD,
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.pwrsts = PWRSTS_OFF_ON,
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.voltdm = { .name = "iva" },
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};
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static struct powerdomain hdvpss_814x_pwrdm = {
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.name = "hdvpss_pwrdm",
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.prcm_offs = TI814X_PRM_HDVPSS_MOD,
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.pwrsts = PWRSTS_OFF_ON,
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.voltdm = { .name = "dsp" },
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};
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static struct powerdomain sgx_814x_pwrdm = {
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.name = "sgx_pwrdm",
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.prcm_offs = TI814X_PRM_GFX_MOD,
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.pwrsts = PWRSTS_OFF_ON,
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.voltdm = { .name = "core" },
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};
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static struct powerdomain isp_814x_pwrdm = {
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.name = "isp_pwrdm",
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.prcm_offs = TI814X_PRM_ISP_MOD,
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.pwrsts = PWRSTS_OFF_ON,
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.voltdm = { .name = "core" },
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};
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static struct powerdomain active_816x_pwrdm = {
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.name = "active_pwrdm",
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.prcm_offs = TI816X_PRM_ACTIVE_MOD,
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@ -448,7 +483,18 @@ static struct powerdomain *powerdomains_am35x[] __initdata = {
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NULL
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};
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static struct powerdomain *powerdomains_ti81xx[] __initdata = {
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static struct powerdomain *powerdomains_ti814x[] __initdata = {
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&alwon_81xx_pwrdm,
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&device_81xx_pwrdm,
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&gem_814x_pwrdm,
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&ivahd_814x_pwrdm,
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&hdvpss_814x_pwrdm,
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&sgx_814x_pwrdm,
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&isp_814x_pwrdm,
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NULL
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};
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static struct powerdomain *powerdomains_ti816x[] __initdata = {
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&alwon_81xx_pwrdm,
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&device_81xx_pwrdm,
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&active_816x_pwrdm,
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@ -460,6 +506,73 @@ static struct powerdomain *powerdomains_ti81xx[] __initdata = {
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NULL
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};
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/* TI81XX specific ops */
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#define TI81XX_PM_PWSTCTRL 0x0000
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#define TI81XX_RM_RSTCTRL 0x0010
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#define TI81XX_PM_PWSTST 0x0004
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static int ti81xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
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{
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omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
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(pwrst << OMAP_POWERSTATE_SHIFT),
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pwrdm->prcm_offs, TI81XX_PM_PWSTCTRL);
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return 0;
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}
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static int ti81xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
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{
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return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
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TI81XX_PM_PWSTCTRL,
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OMAP_POWERSTATE_MASK);
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}
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static int ti81xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
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{
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return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
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(pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL :
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TI81XX_PM_PWSTST,
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OMAP_POWERSTATEST_MASK);
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}
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static int ti81xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
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{
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return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
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(pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL :
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TI81XX_PM_PWSTST,
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OMAP3430_LOGICSTATEST_MASK);
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}
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static int ti81xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
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{
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u32 c = 0;
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while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs,
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(pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL :
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TI81XX_PM_PWSTST) &
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OMAP_INTRANSITION_MASK) &&
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(c++ < PWRDM_TRANSITION_BAILOUT))
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udelay(1);
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if (c > PWRDM_TRANSITION_BAILOUT) {
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pr_err("powerdomain: %s timeout waiting for transition\n",
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pwrdm->name);
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return -EAGAIN;
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}
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pr_debug("powerdomain: completed transition in %d loops\n", c);
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return 0;
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}
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/* For dm814x we need to fix up fix GFX pwstst and rstctrl reg offsets */
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static struct pwrdm_ops ti81xx_pwrdm_operations = {
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.pwrdm_set_next_pwrst = ti81xx_pwrdm_set_next_pwrst,
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.pwrdm_read_next_pwrst = ti81xx_pwrdm_read_next_pwrst,
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.pwrdm_read_pwrst = ti81xx_pwrdm_read_pwrst,
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.pwrdm_read_logic_pwrst = ti81xx_pwrdm_read_logic_pwrst,
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.pwrdm_wait_transition = ti81xx_pwrdm_wait_transition,
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};
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void __init omap3xxx_powerdomains_init(void)
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{
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unsigned int rev;
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@ -467,15 +580,18 @@ void __init omap3xxx_powerdomains_init(void)
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if (!cpu_is_omap34xx() && !cpu_is_ti81xx())
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return;
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pwrdm_register_platform_funcs(&omap3_pwrdm_operations);
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pwrdm_register_platform_funcs(&ti81xx_pwrdm_operations);
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rev = omap_rev();
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if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
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pwrdm_register_pwrdms(powerdomains_am35x);
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} else if (rev == TI8148_REV_ES1_0 || rev == TI8148_REV_ES2_0 ||
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rev == TI8148_REV_ES2_1) {
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pwrdm_register_pwrdms(powerdomains_ti814x);
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} else if (rev == TI8168_REV_ES1_0 || rev == TI8168_REV_ES1_1
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|| rev == TI8168_REV_ES2_0 || rev == TI8168_REV_ES2_1) {
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pwrdm_register_pwrdms(powerdomains_ti81xx);
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pwrdm_register_pwrdms(powerdomains_ti816x);
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} else {
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pwrdm_register_pwrdms(powerdomains_omap3430_common);
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@ -51,6 +51,12 @@
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/*
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* TI81XX PRM module offsets
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*/
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#define TI814X_PRM_DSP_MOD 0x0a00
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#define TI814X_PRM_HDVICP_MOD 0x0c00
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#define TI814X_PRM_ISP_MOD 0x0d00
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#define TI814X_PRM_HDVPSS_MOD 0x0e00
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#define TI814X_PRM_GFX_MOD 0x0f00
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#define TI81XX_PRM_DEVICE_MOD 0x0000
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#define TI816X_PRM_ACTIVE_MOD 0x0a00
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#define TI81XX_PRM_DEFAULT_MOD 0x0b00
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@ -2,7 +2,7 @@ obj-y += clk.o autoidle.o clockdomain.o
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clk-common = dpll.o composite.o divider.o gate.o \
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fixed-factor.o mux.o apll.o
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obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o
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obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-816x.o
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obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-814x.o clk-816x.o
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obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o
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obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \
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clk-3xxx.o
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@ -0,0 +1,31 @@
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/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*/
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#include <linux/kernel.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/ti.h>
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static struct ti_dt_clk dm814_clks[] = {
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DT_CLK(NULL, "devosc_ck", "devosc_ck"),
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DT_CLK(NULL, "mpu_ck", "mpu_ck"),
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DT_CLK(NULL, "sysclk4_ck", "sysclk4_ck"),
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DT_CLK(NULL, "sysclk6_ck", "sysclk6_ck"),
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DT_CLK(NULL, "sysclk10_ck", "sysclk10_ck"),
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DT_CLK(NULL, "sysclk18_ck", "sysclk18_ck"),
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DT_CLK(NULL, "timer_sys_ck", "devosc_ck"),
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DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
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DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
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{ .node_name = NULL },
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};
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int __init dm814x_dt_clk_init(void)
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{
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ti_dt_clocks_register(dm814_clks);
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omap2_clk_disable_autoidle_all();
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omap2_clk_enable_init_clocks(NULL, 0);
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return 0;
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}
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@ -42,7 +42,7 @@ static const char *enable_init_clks[] = {
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"ddr_pll_clk3",
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};
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int __init ti81xx_dt_clk_init(void)
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int __init dm816x_dt_clk_init(void)
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{
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ti_dt_clocks_register(dm816x_clks);
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omap2_clk_disable_autoidle_all();
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@ -329,7 +329,8 @@ int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
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int omap3430_dt_clk_init(void);
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int omap3630_dt_clk_init(void);
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int am35xx_dt_clk_init(void);
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int ti81xx_dt_clk_init(void);
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int dm814x_dt_clk_init(void);
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int dm816x_dt_clk_init(void);
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int omap4xxx_dt_clk_init(void);
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int omap5xxx_dt_clk_init(void);
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int dra7xx_dt_clk_init(void);
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||||
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