ARM: SoC platform updates
SoC platform changes. Main theme this merge window: - The Netx platform (Netx 100/500) platform is removed by Linus Walleij-- the SoC doesn't have active maintainers with hardware, and in discussions with the vendor the agreement was that it's OK to remove. - Russell King has a series of patches that cleans up and refactors SA1101 and RiscPC support. -----BEGIN PGP SIGNATURE----- iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAl0yKOgPHG9sb2ZAbGl4 b20ubmV0AAoJEIwa5zzehBx3SNEP/iJsMeeunX0P7Ym3zNFjykhspkkUmo7sEKuz NBcexnQpkm+OLgjfwT7j3kXvOs4mzMzH56J6h7dEDSHbQP1MDIgpMw6OEzMMsQTV XL1AWz1IO7Sq/mG17daPs9c75o6NYQ7pSEd/ncbjKuJQOpGsi4DyrVrhk9WdzYl2 hcs4XOzOMZgDTsXHVdWkfpHazpWxEXPCD7v5bt6ueU0YnT3csUbzOTTvw+55JxRV fYz0lg4wTMRYMQMOejpx1HXwdmbVOHLUYkCxcLUaVqMnm88q/IddJVklBbPGWAU5 Z4gFpL+FxcFhEZtu28CoubPYzf/mHDk8Ry2UWwBiRwiGoKfblomI1fpnbyrX53aE lpO5p7MfOVVV2WNxpbUND+ilbgKOREfRHd314GLPUjwudp2sTuDRZ1GAbt3JwsIM L1HesyjCtb6itCSwGsmmGsX2Wvu+WT7slpsYwHs2qklE/X1zQq0R4Jf2xUNpwqPb FqGZAtc6CCQtyF/Mcpp6OQd+cV0tgQVIw7teKol/xR1dSzN/+1zO1J9UHk9/dWUU sb5lGa/AtBrIbWxS1qLuA5bgyDqxXYDZi0y/Bu1qMHYebRW37z9kvomtzBiMNX2o SAxvr9iGPlTxTjGjRCyBVFmsbCMYLabNoL9tuuXvo+DnjFoOilTef+qePOv7ZYZX kwUyS2eu =FX6e -----END PGP SIGNATURE----- Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC platform updates from Olof Johansson: "SoC platform changes. Main theme this merge window: - The Netx platform (Netx 100/500) platform is removed by Linus Walleij-- the SoC doesn't have active maintainers with hardware, and in discussions with the vendor the agreement was that it's OK to remove. - Russell King has a series of patches that cleans up and refactors SA1101 and RiscPC support" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (47 commits) ARM: stm32: use "depends on" instead of "if" after prompt ARM: sa1100: convert to common clock framework ARM: exynos: Cleanup cppcheck shifting warning ARM: pxa/lubbock: remove lubbock_set_misc_wr() from global view ARM: exynos: Only build MCPM support if used arm: add missing include platform-data/atmel.h ARM: davinci: Use GPIO lookup table for DA850 LEDs ARM: OMAP2: drop explicit assembler architecture ARM: use arch_extension directive instead of arch argument ARM: imx: Switch imx7d to imx-cpufreq-dt for speed-grading ARM: bcm: Enable PINCTRL for ARCH_BRCMSTB ARM: bcm: Enable ARCH_HAS_RESET_CONTROLLER for ARCH_BRCMSTB ARM: riscpc: enable chained scatterlist support ARM: riscpc: reduce IRQ handling code ARM: riscpc: move RiscPC assembly files from arch/arm/lib to mach-rpc ARM: riscpc: parse video information from tagged list ARM: riscpc: add ecard quirk for Atomwide 3port serial card MAINTAINERS: mvebu: Add git entry soc: ti: pm33xx: Add a print while entering RTC only mode with DDR in self-refresh ARM: OMAP2+: Make some variables static ...
This commit is contained in:
Коммит
24e44913aa
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@ -1264,7 +1264,7 @@ F: include/uapi/drm/panfrost_drm.h
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|||
ARM MFM AND FLOPPY DRIVERS
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M: Ian Molton <spyro@f2s.com>
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S: Maintained
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F: arch/arm/lib/floppydma.S
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F: arch/arm/mach-rpc/floppydma.S
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F: arch/arm/include/asm/floppy.h
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ARM PMU PROFILING AND DEBUGGING
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|
@ -1863,6 +1863,7 @@ F: arch/arm/mach-orion5x/
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F: arch/arm/plat-orion/
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F: arch/arm/boot/dts/dove*
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F: arch/arm/boot/dts/orion5x*
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T: git git://git.infradead.org/linux-mvebu.git
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ARM/Marvell Kirkwood and Armada 370, 375, 38x, 39x, XP, 3700, 7K/8K SOC support
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M: Jason Cooper <jason@lakedaemon.net>
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@ -1883,6 +1884,7 @@ F: drivers/irqchip/irq-armada-370-xp.c
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F: drivers/irqchip/irq-mvebu-*
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F: drivers/pinctrl/mvebu/
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F: drivers/rtc/rtc-armada38x.c
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T: git git://git.infradead.org/linux-mvebu.git
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ARM/Mediatek RTC DRIVER
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M: Eddie Huang <eddie.huang@mediatek.com>
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|
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@ -377,15 +377,6 @@ config ARCH_FOOTBRIDGE
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Support for systems based on the DC21285 companion chip
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("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
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config ARCH_NETX
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bool "Hilscher NetX based"
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select ARM_VIC
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select CLKSRC_MMIO
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select CPU_ARM926T
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select GENERIC_CLOCKEVENTS
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help
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This enables support for systems based on the Hilscher NetX Soc
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config ARCH_IOP13XX
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bool "IOP13xx-based"
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depends on MMU
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@ -531,7 +522,7 @@ config ARCH_RPC
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select ARCH_ACORN
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select ARCH_MAY_HAVE_PC_FDC
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select ARCH_SPARSEMEM_ENABLE
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select ARCH_USES_GETTIMEOFFSET
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select ARM_HAS_SG_CHAIN
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select CPU_SA110
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select FIQ
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select HAVE_IDE
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|
@ -552,6 +543,7 @@ config ARCH_SA1100
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select CLKSRC_MMIO
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select CLKSRC_PXA
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select TIMER_OF if OF
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select COMMON_CLK
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select CPU_FREQ
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select CPU_SA1100
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select GENERIC_CLOCKEVENTS
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|
@ -770,8 +762,6 @@ source "arch/arm/mach-mvebu/Kconfig"
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source "arch/arm/mach-mxs/Kconfig"
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source "arch/arm/mach-netx/Kconfig"
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source "arch/arm/mach-nomadik/Kconfig"
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source "arch/arm/mach-npcm/Kconfig"
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|
|
|
@ -638,13 +638,6 @@ choice
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Say Y here if you want kernel low-level debugging support
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for Mediatek mt8135 based platforms on UART3.
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config DEBUG_NETX_UART
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bool "Kernel low-level debugging messages via NetX UART"
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depends on ARCH_NETX
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help
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Say Y here if you want kernel low-level debugging support
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on Hilscher NetX based platforms.
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config DEBUG_NOMADIK_UART
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bool "Kernel low-level debugging messages via NOMADIK UART"
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depends on ARCH_NOMADIK
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|
|
|
@ -191,7 +191,6 @@ machine-$(CONFIG_ARCH_MXC) += imx
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machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
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machine-$(CONFIG_ARCH_MILBEAUT) += milbeaut
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machine-$(CONFIG_ARCH_MXS) += mxs
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machine-$(CONFIG_ARCH_NETX) += netx
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machine-$(CONFIG_ARCH_NOMADIK) += nomadik
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machine-$(CONFIG_ARCH_NPCM) += npcm
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machine-$(CONFIG_ARCH_NSPIRE) += nspire
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|
|
|
@ -1,80 +0,0 @@
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CONFIG_SYSVIPC=y
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CONFIG_POSIX_MQUEUE=y
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CONFIG_BSD_PROCESS_ACCT=y
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CONFIG_IKCONFIG=y
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CONFIG_IKCONFIG_PROC=y
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CONFIG_SLAB=y
|
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CONFIG_MODULES=y
|
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CONFIG_MODULE_UNLOAD=y
|
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CONFIG_MODULE_FORCE_UNLOAD=y
|
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CONFIG_ARCH_NETX=y
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CONFIG_MACH_NXDKN=y
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CONFIG_MACH_NXDB500=y
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CONFIG_MACH_NXEB500HMI=y
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CONFIG_PREEMPT=y
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CONFIG_ZBOOT_ROM_TEXT=0x0
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CONFIG_ZBOOT_ROM_BSS=0x0
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CONFIG_CMDLINE="console=ttySMX0,115200"
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CONFIG_NET=y
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CONFIG_PACKET=y
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CONFIG_UNIX=y
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CONFIG_XFRM_USER=m
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CONFIG_NET_KEY=y
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CONFIG_INET=y
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CONFIG_IP_MULTICAST=y
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CONFIG_IP_PNP=y
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CONFIG_IP_PNP_DHCP=y
|
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CONFIG_NET_IPGRE=m
|
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CONFIG_SYN_COOKIES=y
|
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CONFIG_INET_AH=y
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CONFIG_INET_ESP=y
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CONFIG_INET_IPCOMP=y
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CONFIG_INET6_AH=m
|
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CONFIG_INET6_ESP=m
|
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CONFIG_INET6_IPCOMP=m
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CONFIG_NETFILTER=y
|
||||
CONFIG_NET_PKTGEN=m
|
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CONFIG_MTD=y
|
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CONFIG_MTD_CMDLINE_PARTS=y
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CONFIG_MTD_BLOCK=y
|
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CONFIG_MTD_CFI=y
|
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CONFIG_MTD_CFI_INTELEXT=y
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CONFIG_MTD_PLATRAM=y
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CONFIG_BLK_DEV_LOOP=m
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CONFIG_BLK_DEV_CRYPTOLOOP=m
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CONFIG_NETDEVICES=y
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CONFIG_NET_ETHERNET=y
|
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CONFIG_NET_NETX=y
|
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# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
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# CONFIG_INPUT_KEYBOARD is not set
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# CONFIG_INPUT_MOUSE is not set
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CONFIG_SERIAL_NETX=y
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CONFIG_SERIAL_NETX_CONSOLE=y
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# CONFIG_HWMON is not set
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CONFIG_FB=y
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CONFIG_FB_ARMCLCD=y
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# CONFIG_VGA_CONSOLE is not set
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CONFIG_FRAMEBUFFER_CONSOLE=y
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CONFIG_LOGO=y
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CONFIG_RTC_CLASS=y
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CONFIG_TMPFS=y
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CONFIG_JFFS2_FS=y
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CONFIG_NFS_FS=y
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CONFIG_NFS_V3=y
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CONFIG_NFS_V4=y
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CONFIG_ROOT_NFS=y
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CONFIG_MAGIC_SYSRQ=y
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CONFIG_DEBUG_KERNEL=y
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CONFIG_CRYPTO_NULL=m
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CONFIG_CRYPTO_MD4=m
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CONFIG_CRYPTO_MICHAEL_MIC=m
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CONFIG_CRYPTO_SHA256=m
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CONFIG_CRYPTO_SHA512=m
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CONFIG_CRYPTO_ARC4=m
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CONFIG_CRYPTO_BLOWFISH=m
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CONFIG_CRYPTO_CAST5=m
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CONFIG_CRYPTO_CAST6=m
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CONFIG_CRYPTO_SERPENT=m
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CONFIG_CRYPTO_TWOFISH=m
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CONFIG_CRC_CCITT=m
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CONFIG_LIBCRC32C=m
|
|
@ -1,32 +0,0 @@
|
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Debugging macro include header
|
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*
|
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* Copyright (C) 1994-1999 Russell King
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* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
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*/
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|
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#define UART_DATA 0
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#define UART_FLAG 0x18
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#define UART_FLAG_BUSY (1 << 3)
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|
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.macro addruart, rp, rv, tmp
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ldr \rp, =CONFIG_DEBUG_UART_PHYS
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ldr \rv, =CONFIG_DEBUG_UART_VIRT
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.endm
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|
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.macro senduart,rd,rx
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str \rd, [\rx, #UART_DATA]
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.endm
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.macro busyuart,rd,rx
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1002: ldr \rd, [\rx, #UART_FLAG]
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tst \rd, #UART_FLAG_BUSY
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bne 1002b
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.endm
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.macro waituart,rd,rx
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1001: ldr \rd, [\rx, #UART_FLAG]
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tst \rd, #UART_FLAG_BUSY
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bne 1001b
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.endm
|
|
@ -31,7 +31,6 @@ else
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endif
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ifeq ($(CONFIG_ARCH_RPC),y)
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lib-y += ecard.o io-acorn.o floppydma.o
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AFLAGS_delay-loop.o += -march=armv4
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endif
|
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|
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|
|
|
@ -15,6 +15,7 @@
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#include <linux/suspend.h>
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|
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#include <linux/clk/at91_pmc.h>
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#include <linux/platform_data/atmel.h>
|
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|
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#include <asm/cacheflush.h>
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#include <asm/fncpy.h>
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|
|
|
@ -208,6 +208,7 @@ config ARCH_BCM_63XX
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config ARCH_BRCMSTB
|
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bool "Broadcom BCM7XXX based boards"
|
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depends on ARCH_MULTI_V7
|
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select ARCH_HAS_RESET_CONTROLLER
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select ARM_GIC
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select ARM_ERRATA_798181 if SMP
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select HAVE_ARM_ARCH_TIMER
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|
@ -217,6 +218,7 @@ config ARCH_BRCMSTB
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select ZONE_DMA if ARM_LPAE
|
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select SOC_BRCMSTB
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select SOC_BUS
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select PINCTRL
|
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help
|
||||
Say Y if you intend to run the kernel on a Broadcom ARM-based STB
|
||||
chipset.
|
||||
|
|
|
@ -40,9 +40,6 @@ obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o
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|||
|
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# Support for secure monitor traps
|
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obj-$(CONFIG_ARCH_BCM_MOBILE_SMC) += bcm_kona_smc.o
|
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ifeq ($(call as-instr,.arch_extension sec,as_has_sec),as_has_sec)
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CFLAGS_bcm_kona_smc.o += -Wa,-march=armv7-a+sec -DREQUIRES_SEC
|
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endif
|
||||
|
||||
# BCM2835
|
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obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o
|
||||
|
|
|
@ -141,6 +141,7 @@ static int bcm63138_smp_boot_secondary(unsigned int cpu,
|
|||
* return
|
||||
*/
|
||||
ret = bcm63xx_pmb_power_on_cpu(dn);
|
||||
of_node_put(dn);
|
||||
if (ret)
|
||||
goto out;
|
||||
out:
|
||||
|
|
|
@ -125,9 +125,7 @@ static int bcm_kona_do_smc(u32 service_id, u32 buffer_phys)
|
|||
__asmeq("%2", "r4")
|
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__asmeq("%3", "r5")
|
||||
__asmeq("%4", "r6")
|
||||
#ifdef REQUIRES_SEC
|
||||
".arch_extension sec\n"
|
||||
#endif
|
||||
" smc #0\n"
|
||||
: "=r" (ip), "=r" (r0)
|
||||
: "r" (r4), "r" (r5), "r" (r6)
|
||||
|
|
|
@ -38,6 +38,7 @@ static void bcm281xx_restart(enum reboot_mode mode, const char *cmd)
|
|||
return;
|
||||
}
|
||||
base = of_iomap(np_wdog, 0);
|
||||
of_node_put(np_wdog);
|
||||
if (!base) {
|
||||
pr_emerg("Couldn't map brcm,kona-wdt\n");
|
||||
return;
|
||||
|
|
|
@ -334,11 +334,14 @@ static void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus)
|
|||
|
||||
rc = setup_hifcpubiuctrl_regs(np);
|
||||
if (rc)
|
||||
return;
|
||||
goto out_put_node;
|
||||
|
||||
rc = setup_hifcont_regs(np);
|
||||
if (rc)
|
||||
return;
|
||||
goto out_put_node;
|
||||
|
||||
out_put_node:
|
||||
of_node_put(np);
|
||||
}
|
||||
|
||||
static int brcmstb_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
|
|
|
@ -631,13 +631,12 @@ static void da850_evm_bb_keys_init(unsigned gpio)
|
|||
}
|
||||
}
|
||||
|
||||
#define DA850_N_BB_USER_LED 2
|
||||
|
||||
static struct gpio_led da850_evm_bb_leds[] = {
|
||||
[0 ... DA850_N_BB_USER_LED - 1] = {
|
||||
.active_low = 1,
|
||||
.gpio = -1, /* assigned at runtime */
|
||||
.name = NULL, /* assigned at runtime */
|
||||
{
|
||||
.name = "user_led2",
|
||||
},
|
||||
{
|
||||
.name = "user_led1",
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -646,6 +645,20 @@ static struct gpio_led_platform_data da850_evm_bb_leds_pdata = {
|
|||
.num_leds = ARRAY_SIZE(da850_evm_bb_leds),
|
||||
};
|
||||
|
||||
static struct gpiod_lookup_table da850_evm_bb_leds_gpio_table = {
|
||||
.dev_id = "leds-gpio",
|
||||
.table = {
|
||||
GPIO_LOOKUP_IDX("i2c-bb-expander",
|
||||
DA850_EVM_BB_EXP_USER_LED2, NULL,
|
||||
0, GPIO_ACTIVE_LOW),
|
||||
GPIO_LOOKUP_IDX("i2c-bb-expander",
|
||||
DA850_EVM_BB_EXP_USER_LED2 + 1, NULL,
|
||||
1, GPIO_ACTIVE_LOW),
|
||||
|
||||
{ },
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device da850_evm_bb_leds_device = {
|
||||
.name = "leds-gpio",
|
||||
.id = -1,
|
||||
|
@ -654,20 +667,6 @@ static struct platform_device da850_evm_bb_leds_device = {
|
|||
}
|
||||
};
|
||||
|
||||
static void da850_evm_bb_leds_init(unsigned gpio)
|
||||
{
|
||||
int i;
|
||||
struct gpio_led *led;
|
||||
|
||||
for (i = 0; i < DA850_N_BB_USER_LED; i++) {
|
||||
led = &da850_evm_bb_leds[i];
|
||||
|
||||
led->gpio = gpio + DA850_EVM_BB_EXP_USER_LED2 + i;
|
||||
led->name =
|
||||
da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_LED2 + i];
|
||||
}
|
||||
}
|
||||
|
||||
static int da850_evm_bb_expander_setup(struct i2c_client *client,
|
||||
unsigned gpio, unsigned ngpio,
|
||||
void *c)
|
||||
|
@ -685,7 +684,7 @@ static int da850_evm_bb_expander_setup(struct i2c_client *client,
|
|||
goto io_exp_setup_sw_fail;
|
||||
}
|
||||
|
||||
da850_evm_bb_leds_init(gpio);
|
||||
gpiod_add_lookup_table(&da850_evm_bb_leds_gpio_table);
|
||||
ret = platform_device_register(&da850_evm_bb_leds_device);
|
||||
if (ret) {
|
||||
pr_warn("Could not register baseboard GPIO expander LEDs");
|
||||
|
@ -729,10 +728,12 @@ static struct i2c_board_info __initdata da850_evm_i2c_devices[] = {
|
|||
},
|
||||
{
|
||||
I2C_BOARD_INFO("tca6416", 0x20),
|
||||
.dev_name = "ui-expander",
|
||||
.platform_data = &da850_evm_ui_expander_info,
|
||||
},
|
||||
{
|
||||
I2C_BOARD_INFO("tca6416", 0x21),
|
||||
.dev_name = "bb-expander",
|
||||
.platform_data = &da850_evm_bb_expander_info,
|
||||
},
|
||||
};
|
||||
|
|
|
@ -49,6 +49,7 @@ config S5P_DEV_MFC
|
|||
|
||||
config ARCH_EXYNOS3
|
||||
bool "SAMSUNG EXYNOS3"
|
||||
default y
|
||||
select ARM_CPU_SUSPEND if PM
|
||||
help
|
||||
Samsung EXYNOS3 (Cortex-A7) SoC based systems
|
||||
|
@ -106,7 +107,7 @@ config SOC_EXYNOS5420
|
|||
bool "SAMSUNG EXYNOS5420"
|
||||
default y
|
||||
depends on ARCH_EXYNOS5
|
||||
select MCPM if SMP
|
||||
select EXYNOS_MCPM if SMP
|
||||
select ARM_CCI400_PORT_CTRL
|
||||
select ARM_CPU_SUSPEND
|
||||
|
||||
|
@ -115,6 +116,10 @@ config SOC_EXYNOS5800
|
|||
default y
|
||||
depends on SOC_EXYNOS5420
|
||||
|
||||
config EXYNOS_MCPM
|
||||
bool
|
||||
select MCPM
|
||||
|
||||
config EXYNOS_CPU_SUSPEND
|
||||
bool
|
||||
select ARM_CPU_SUSPEND
|
||||
|
|
|
@ -14,9 +14,5 @@ obj-$(CONFIG_PM_SLEEP) += suspend.o
|
|||
|
||||
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
|
||||
|
||||
plus_sec := $(call as-instr,.arch_extension sec,+sec)
|
||||
AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec)
|
||||
AFLAGS_sleep.o :=-Wa,-march=armv7-a$(plus_sec)
|
||||
|
||||
obj-$(CONFIG_MCPM) += mcpm-exynos.o
|
||||
obj-$(CONFIG_EXYNOS_MCPM) += mcpm-exynos.o
|
||||
CFLAGS_mcpm-exynos.o += -march=armv7-a
|
||||
|
|
|
@ -10,7 +10,8 @@
|
|||
/*
|
||||
* Function signature: void exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32 arg3)
|
||||
*/
|
||||
|
||||
.arch armv7-a
|
||||
.arch_extension sec
|
||||
ENTRY(exynos_smc)
|
||||
stmfd sp!, {r4-r11, lr}
|
||||
dsb
|
||||
|
|
|
@ -44,7 +44,8 @@ ENTRY(exynos_cpu_resume)
|
|||
ENDPROC(exynos_cpu_resume)
|
||||
|
||||
.align
|
||||
|
||||
.arch armv7-a
|
||||
.arch_extension sec
|
||||
ENTRY(exynos_cpu_resume_ns)
|
||||
mrc p15, 0, r0, c0, c0, 0
|
||||
ldr r1, =CPU_MASK
|
||||
|
|
|
@ -268,7 +268,7 @@ static int exynos5420_cpu_suspend(unsigned long arg)
|
|||
unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
|
||||
unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
|
||||
|
||||
if (IS_ENABLED(CONFIG_MCPM)) {
|
||||
if (IS_ENABLED(CONFIG_EXYNOS_MCPM)) {
|
||||
mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
|
||||
mcpm_cpu_suspend();
|
||||
}
|
||||
|
@ -285,7 +285,7 @@ static void exynos_pm_set_wakeup_mask(void)
|
|||
* Set wake-up mask registers
|
||||
* EXYNOS_EINT_WAKEUP_MASK is set by pinctrl driver in late suspend.
|
||||
*/
|
||||
pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
|
||||
pmu_raw_writel(exynos_irqwake_intmask & ~BIT(31), S5P_WAKEUP_MASK);
|
||||
}
|
||||
|
||||
static void exynos_pm_enter_sleep_mode(void)
|
||||
|
@ -351,7 +351,7 @@ static void exynos5420_pm_prepare(void)
|
|||
exynos_pm_enter_sleep_mode();
|
||||
|
||||
/* ensure at least INFORM0 has the resume address */
|
||||
if (IS_ENABLED(CONFIG_MCPM))
|
||||
if (IS_ENABLED(CONFIG_EXYNOS_MCPM))
|
||||
pmu_raw_writel(__pa_symbol(mcpm_entry_point), S5P_INFORM0);
|
||||
|
||||
tmp = pmu_raw_readl(EXYNOS_L2_OPTION(0));
|
||||
|
@ -455,7 +455,7 @@ static void exynos5420_prepare_pm_resume(void)
|
|||
mpidr = read_cpuid_mpidr();
|
||||
cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
|
||||
|
||||
if (IS_ENABLED(CONFIG_MCPM))
|
||||
if (IS_ENABLED(CONFIG_EXYNOS_MCPM))
|
||||
WARN_ON(mcpm_cpu_powered_up());
|
||||
|
||||
if (IS_ENABLED(CONFIG_HW_PERF_EVENTS) && cluster != 0) {
|
||||
|
|
|
@ -1,7 +1,4 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
obj-y := highbank.o system.o smc.o
|
||||
|
||||
plus_sec := $(call as-instr,.arch_extension sec,+sec)
|
||||
AFLAGS_smc.o :=-Wa,-march=armv7-a$(plus_sec)
|
||||
|
||||
obj-$(CONFIG_PM_SLEEP) += pm.o
|
||||
|
|
|
@ -13,7 +13,8 @@
|
|||
* the monitor API number.
|
||||
* Function signature : void highbank_smc1(u32 fn, u32 arg)
|
||||
*/
|
||||
|
||||
.arch armv7-a
|
||||
.arch_extension sec
|
||||
ENTRY(highbank_smc1)
|
||||
stmfd sp!, {r4-r11, lr}
|
||||
mov r12, r0
|
||||
|
|
|
@ -14,22 +14,22 @@
|
|||
#include "hardware.h"
|
||||
|
||||
static int num_idle_cpus = 0;
|
||||
static DEFINE_SPINLOCK(cpuidle_lock);
|
||||
static DEFINE_RAW_SPINLOCK(cpuidle_lock);
|
||||
|
||||
static int imx6q_enter_wait(struct cpuidle_device *dev,
|
||||
struct cpuidle_driver *drv, int index)
|
||||
{
|
||||
spin_lock(&cpuidle_lock);
|
||||
raw_spin_lock(&cpuidle_lock);
|
||||
if (++num_idle_cpus == num_online_cpus())
|
||||
imx6_set_lpm(WAIT_UNCLOCKED);
|
||||
spin_unlock(&cpuidle_lock);
|
||||
raw_spin_unlock(&cpuidle_lock);
|
||||
|
||||
cpu_do_idle();
|
||||
|
||||
spin_lock(&cpuidle_lock);
|
||||
raw_spin_lock(&cpuidle_lock);
|
||||
if (num_idle_cpus-- == num_online_cpus())
|
||||
imx6_set_lpm(WAIT_CLOCKED);
|
||||
spin_unlock(&cpuidle_lock);
|
||||
raw_spin_unlock(&cpuidle_lock);
|
||||
|
||||
return index;
|
||||
}
|
||||
|
|
|
@ -94,6 +94,12 @@ static void __init imx7d_init_machine(void)
|
|||
imx7d_enet_init();
|
||||
}
|
||||
|
||||
static void __init imx7d_init_late(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT))
|
||||
platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0);
|
||||
}
|
||||
|
||||
static void __init imx7d_init_irq(void)
|
||||
{
|
||||
imx_init_revision_from_anatop();
|
||||
|
@ -110,5 +116,6 @@ static const char *const imx7d_dt_compat[] __initconst = {
|
|||
DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual (Device Tree)")
|
||||
.init_irq = imx7d_init_irq,
|
||||
.init_machine = imx7d_init_machine,
|
||||
.init_late = imx7d_init_late,
|
||||
.dt_compat = imx7d_dt_compat,
|
||||
MACHINE_END
|
||||
|
|
|
@ -1,9 +1,6 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
obj-y := keystone.o smc.o
|
||||
|
||||
plus_sec := $(call as-instr,.arch_extension sec,+sec)
|
||||
AFLAGS_smc.o :=-Wa,-march=armv7-a$(plus_sec)
|
||||
|
||||
obj-$(CONFIG_SMP) += platsmp.o
|
||||
|
||||
# PM domain driver for Keystone SOCs
|
||||
|
|
|
@ -18,6 +18,7 @@
|
|||
*
|
||||
* Return: Non zero value on failure
|
||||
*/
|
||||
.arch_extension sec
|
||||
ENTRY(keystone_cpu_smc)
|
||||
stmfd sp!, {r4-r11, lr}
|
||||
smc #0
|
||||
|
|
|
@ -41,18 +41,10 @@ obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) $(smp-y) sleep44xx.o
|
|||
obj-$(CONFIG_SOC_AM43XX) += $(omap-4-5-common)
|
||||
obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-common) $(smp-y) sleep44xx.o
|
||||
|
||||
plus_sec := $(call as-instr,.arch_extension sec,+sec)
|
||||
AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
|
||||
AFLAGS_omap-smc.o :=-Wa,-march=armv7-a$(plus_sec)
|
||||
AFLAGS_sleep44xx.o :=-Wa,-march=armv7-a$(plus_sec)
|
||||
|
||||
# Functions loaded to SRAM
|
||||
obj-$(CONFIG_SOC_OMAP2420) += sram242x.o
|
||||
obj-$(CONFIG_SOC_OMAP2430) += sram243x.o
|
||||
|
||||
AFLAGS_sram242x.o :=-Wa,-march=armv6
|
||||
AFLAGS_sram243x.o :=-Wa,-march=armv6
|
||||
|
||||
# Restart code (OMAP4/5 currently in omap4-common.c)
|
||||
obj-$(CONFIG_SOC_OMAP2420) += omap2-restart.o
|
||||
obj-$(CONFIG_SOC_OMAP2430) += omap2-restart.o
|
||||
|
@ -94,11 +86,6 @@ obj-$(CONFIG_PM_DEBUG) += pm-debug.o
|
|||
obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o
|
||||
obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o
|
||||
|
||||
AFLAGS_sleep24xx.o :=-Wa,-march=armv6
|
||||
AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec)
|
||||
AFLAGS_sleep33xx.o :=-Wa,-march=armv7-a$(plus_sec)
|
||||
AFLAGS_sleep43xx.o :=-Wa,-march=armv7-a$(plus_sec)
|
||||
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_CPU_IDLE),y)
|
||||
|
|
|
@ -55,6 +55,8 @@ ENDPROC(omap5_secondary_startup)
|
|||
* omap5_secondary_startup if the primary CPU was put into HYP mode by
|
||||
* the boot loader.
|
||||
*/
|
||||
.arch armv7-a
|
||||
.arch_extension sec
|
||||
ENTRY(omap5_secondary_hyp_startup)
|
||||
wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
|
||||
ldr r0, [r2]
|
||||
|
|
|
@ -20,7 +20,8 @@
|
|||
* link register "lr".
|
||||
* Function signature : void omap_smc1(u32 fn, u32 arg)
|
||||
*/
|
||||
|
||||
.arch armv7-a
|
||||
.arch_extension sec
|
||||
ENTRY(omap_smc1)
|
||||
stmfd sp!, {r2-r12, lr}
|
||||
mov r12, r0
|
||||
|
|
|
@ -529,7 +529,7 @@ static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
|
|||
.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
};
|
||||
|
||||
struct omap_hwmod_class am33xx_gpio_hwmod_class = {
|
||||
static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
|
||||
.name = "gpio",
|
||||
.sysc = &am33xx_gpio_sysc,
|
||||
};
|
||||
|
@ -539,7 +539,7 @@ static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
|
|||
{ .role = "dbclk", .clk = "gpio1_dbclk" },
|
||||
};
|
||||
|
||||
struct omap_hwmod am33xx_gpio1_hwmod = {
|
||||
static struct omap_hwmod am33xx_gpio1_hwmod = {
|
||||
.name = "gpio2",
|
||||
.class = &am33xx_gpio_hwmod_class,
|
||||
.clkdm_name = "l4ls_clkdm",
|
||||
|
@ -559,7 +559,7 @@ static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
|
|||
{ .role = "dbclk", .clk = "gpio2_dbclk" },
|
||||
};
|
||||
|
||||
struct omap_hwmod am33xx_gpio2_hwmod = {
|
||||
static struct omap_hwmod am33xx_gpio2_hwmod = {
|
||||
.name = "gpio3",
|
||||
.class = &am33xx_gpio_hwmod_class,
|
||||
.clkdm_name = "l4ls_clkdm",
|
||||
|
@ -579,7 +579,7 @@ static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
|
|||
{ .role = "dbclk", .clk = "gpio3_dbclk" },
|
||||
};
|
||||
|
||||
struct omap_hwmod am33xx_gpio3_hwmod = {
|
||||
static struct omap_hwmod am33xx_gpio3_hwmod = {
|
||||
.name = "gpio4",
|
||||
.class = &am33xx_gpio_hwmod_class,
|
||||
.clkdm_name = "l4ls_clkdm",
|
||||
|
|
|
@ -24,6 +24,7 @@
|
|||
#define BIT(nr) (1 << (nr))
|
||||
|
||||
.arm
|
||||
.arch armv7-a
|
||||
.align 3
|
||||
|
||||
ENTRY(am33xx_do_wfi)
|
||||
|
|
|
@ -83,6 +83,8 @@ ENDPROC(enable_omap3630_toggle_l2_on_restore)
|
|||
*
|
||||
* r0 = physical address of the parameters
|
||||
*/
|
||||
.arch armv7-a
|
||||
.arch_extension sec
|
||||
ENTRY(save_secure_ram_context)
|
||||
stmfd sp!, {r4 - r11, lr} @ save registers on stack
|
||||
mov r3, r0 @ physical address of parameters
|
||||
|
|
|
@ -56,6 +56,8 @@
|
|||
#define RTC_PMIC_EXT_WAKEUP_EN BIT(0)
|
||||
|
||||
.arm
|
||||
.arch armv7-a
|
||||
.arch_extension sec
|
||||
.align 3
|
||||
|
||||
ENTRY(am43xx_do_wfi)
|
||||
|
|
|
@ -18,8 +18,11 @@
|
|||
#include "omap44xx.h"
|
||||
#include "omap4-sar-layout.h"
|
||||
|
||||
.arch armv7-a
|
||||
|
||||
#if defined(CONFIG_SMP) && defined(CONFIG_PM)
|
||||
|
||||
.arch_extension sec
|
||||
.macro DO_SMC
|
||||
dsb
|
||||
smc #0
|
||||
|
|
|
@ -47,7 +47,3 @@
|
|||
#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6)
|
||||
|
||||
#define LUBBOCK_SA1111_IRQ_BASE (LUBBOCK_NR_IRQS + 32)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set);
|
||||
#endif
|
||||
|
|
|
@ -116,12 +116,11 @@ void lubbock_set_hexled(uint32_t value)
|
|||
|
||||
static struct gpio_chip *lubbock_misc_wr_gc;
|
||||
|
||||
void lubbock_set_misc_wr(unsigned int mask, unsigned int set)
|
||||
static void lubbock_set_misc_wr(unsigned int mask, unsigned int set)
|
||||
{
|
||||
unsigned long m = mask, v = set;
|
||||
lubbock_misc_wr_gc->set_multiple(lubbock_misc_wr_gc, &m, &v);
|
||||
}
|
||||
EXPORT_SYMBOL(lubbock_set_misc_wr);
|
||||
|
||||
static int lubbock_udc_is_connected(void)
|
||||
{
|
||||
|
|
|
@ -269,19 +269,25 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
|
|||
sram_base_addr = of_iomap(node, 0);
|
||||
if (!sram_base_addr) {
|
||||
pr_err("%s: could not map sram registers\n", __func__);
|
||||
of_node_put(node);
|
||||
return;
|
||||
}
|
||||
|
||||
if (has_pmu && rockchip_smp_prepare_pmu())
|
||||
if (has_pmu && rockchip_smp_prepare_pmu()) {
|
||||
of_node_put(node);
|
||||
return;
|
||||
}
|
||||
|
||||
if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
|
||||
if (rockchip_smp_prepare_sram(node))
|
||||
if (rockchip_smp_prepare_sram(node)) {
|
||||
of_node_put(node);
|
||||
return;
|
||||
}
|
||||
|
||||
/* enable the SCU power domain */
|
||||
pmu_set_power_domain(PMU_PWRDN_SCU, true);
|
||||
|
||||
of_node_put(node);
|
||||
node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
|
||||
if (!node) {
|
||||
pr_err("%s: missing scu\n", __func__);
|
||||
|
@ -291,6 +297,7 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
|
|||
scu_base_addr = of_iomap(node, 0);
|
||||
if (!scu_base_addr) {
|
||||
pr_err("%s: could not map scu registers\n", __func__);
|
||||
of_node_put(node);
|
||||
return;
|
||||
}
|
||||
|
||||
|
@ -309,6 +316,7 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
|
|||
asm ("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
|
||||
ncores = ((l2ctlr >> 24) & 0x3) + 1;
|
||||
}
|
||||
of_node_put(node);
|
||||
|
||||
/* Make sure that all cores except the first are really off */
|
||||
for (i = 1; i < ncores; i++)
|
||||
|
|
|
@ -257,12 +257,14 @@ static int __init rk3288_suspend_init(struct device_node *np)
|
|||
rk3288_bootram_base = of_iomap(sram_np, 0);
|
||||
if (!rk3288_bootram_base) {
|
||||
pr_err("%s: could not map bootram base\n", __func__);
|
||||
of_node_put(sram_np);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ret = of_address_to_resource(sram_np, 0, &res);
|
||||
if (ret) {
|
||||
pr_err("%s: could not get bootram phy addr\n", __func__);
|
||||
of_node_put(sram_np);
|
||||
return ret;
|
||||
}
|
||||
rk3288_bootram_phy = res.start;
|
||||
|
|
|
@ -5,4 +5,5 @@
|
|||
|
||||
# Object file lists.
|
||||
|
||||
obj-y := dma.o ecard.o fiq.o irq.o riscpc.o time.o
|
||||
obj-y :=dma.o ecard.o ecard-loader.o fiq.o floppydma.o io-acorn.o irq.o \
|
||||
riscpc.o time.o
|
||||
|
|
|
@ -24,10 +24,11 @@
|
|||
|
||||
struct iomd_dma {
|
||||
struct dma_struct dma;
|
||||
unsigned int state;
|
||||
unsigned long base; /* Controller base address */
|
||||
void __iomem *base; /* Controller base address */
|
||||
int irq; /* Controller IRQ */
|
||||
struct scatterlist cur_sg; /* Current controller buffer */
|
||||
unsigned int state;
|
||||
dma_addr_t cur_addr;
|
||||
unsigned int cur_len;
|
||||
dma_addr_t dma_addr;
|
||||
unsigned int dma_len;
|
||||
};
|
||||
|
@ -50,13 +51,13 @@ typedef enum {
|
|||
#define CR (IOMD_IO0CR - IOMD_IO0CURA)
|
||||
#define ST (IOMD_IO0ST - IOMD_IO0CURA)
|
||||
|
||||
static void iomd_get_next_sg(struct scatterlist *sg, struct iomd_dma *idma)
|
||||
static void iomd_get_next_sg(struct iomd_dma *idma)
|
||||
{
|
||||
unsigned long end, offset, flags = 0;
|
||||
|
||||
if (idma->dma.sg) {
|
||||
sg->dma_address = idma->dma_addr;
|
||||
offset = sg->dma_address & ~PAGE_MASK;
|
||||
idma->cur_addr = idma->dma_addr;
|
||||
offset = idma->cur_addr & ~PAGE_MASK;
|
||||
|
||||
end = offset + idma->dma_len;
|
||||
|
||||
|
@ -66,7 +67,7 @@ static void iomd_get_next_sg(struct scatterlist *sg, struct iomd_dma *idma)
|
|||
if (offset + TRANSFER_SIZE >= end)
|
||||
flags |= DMA_END_L;
|
||||
|
||||
sg->length = end - TRANSFER_SIZE;
|
||||
idma->cur_len = end - TRANSFER_SIZE;
|
||||
|
||||
idma->dma_len -= end - offset;
|
||||
idma->dma_addr += end - offset;
|
||||
|
@ -84,52 +85,49 @@ static void iomd_get_next_sg(struct scatterlist *sg, struct iomd_dma *idma)
|
|||
}
|
||||
} else {
|
||||
flags = DMA_END_S | DMA_END_L;
|
||||
sg->dma_address = 0;
|
||||
sg->length = 0;
|
||||
idma->cur_addr = 0;
|
||||
idma->cur_len = 0;
|
||||
}
|
||||
|
||||
sg->length |= flags;
|
||||
idma->cur_len |= flags;
|
||||
}
|
||||
|
||||
static irqreturn_t iomd_dma_handle(int irq, void *dev_id)
|
||||
{
|
||||
struct iomd_dma *idma = dev_id;
|
||||
unsigned long base = idma->base;
|
||||
void __iomem *base = idma->base;
|
||||
unsigned int state = idma->state;
|
||||
unsigned int status, cur, end;
|
||||
|
||||
do {
|
||||
unsigned int status;
|
||||
|
||||
status = iomd_readb(base + ST);
|
||||
status = readb(base + ST);
|
||||
if (!(status & DMA_ST_INT))
|
||||
return IRQ_HANDLED;
|
||||
goto out;
|
||||
|
||||
if ((idma->state ^ status) & DMA_ST_AB)
|
||||
iomd_get_next_sg(&idma->cur_sg, idma);
|
||||
if ((state ^ status) & DMA_ST_AB)
|
||||
iomd_get_next_sg(idma);
|
||||
|
||||
switch (status & (DMA_ST_OFL | DMA_ST_AB)) {
|
||||
case DMA_ST_OFL: /* OIA */
|
||||
case DMA_ST_AB: /* .IB */
|
||||
iomd_writel(idma->cur_sg.dma_address, base + CURA);
|
||||
iomd_writel(idma->cur_sg.length, base + ENDA);
|
||||
idma->state = DMA_ST_AB;
|
||||
break;
|
||||
|
||||
case DMA_ST_OFL | DMA_ST_AB: /* OIB */
|
||||
case 0: /* .IA */
|
||||
iomd_writel(idma->cur_sg.dma_address, base + CURB);
|
||||
iomd_writel(idma->cur_sg.length, base + ENDB);
|
||||
idma->state = 0;
|
||||
break;
|
||||
// This efficiently implements state = OFL != AB ? AB : 0
|
||||
state = ((status >> 2) ^ status) & DMA_ST_AB;
|
||||
if (state) {
|
||||
cur = CURA;
|
||||
end = ENDA;
|
||||
} else {
|
||||
cur = CURB;
|
||||
end = ENDB;
|
||||
}
|
||||
writel(idma->cur_addr, base + cur);
|
||||
writel(idma->cur_len, base + end);
|
||||
|
||||
if (status & DMA_ST_OFL &&
|
||||
idma->cur_sg.length == (DMA_END_S|DMA_END_L))
|
||||
idma->cur_len == (DMA_END_S|DMA_END_L))
|
||||
break;
|
||||
} while (1);
|
||||
|
||||
idma->state = ~DMA_ST_AB;
|
||||
disable_irq(irq);
|
||||
|
||||
state = ~DMA_ST_AB;
|
||||
disable_irq_nosync(irq);
|
||||
out:
|
||||
idma->state = state;
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
|
@ -157,7 +155,7 @@ static struct device isa_dma_dev = {
|
|||
static void iomd_enable_dma(unsigned int chan, dma_t *dma)
|
||||
{
|
||||
struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
|
||||
unsigned long dma_base = idma->base;
|
||||
void __iomem *base = idma->base;
|
||||
unsigned int ctrl = TRANSFER_SIZE | DMA_CR_E;
|
||||
|
||||
if (idma->dma.invalid) {
|
||||
|
@ -177,27 +175,30 @@ static void iomd_enable_dma(unsigned int chan, dma_t *dma)
|
|||
DMA_FROM_DEVICE : DMA_TO_DEVICE);
|
||||
}
|
||||
|
||||
iomd_writeb(DMA_CR_C, dma_base + CR);
|
||||
idma->dma_addr = idma->dma.sg->dma_address;
|
||||
idma->dma_len = idma->dma.sg->length;
|
||||
|
||||
writeb(DMA_CR_C, base + CR);
|
||||
idma->state = DMA_ST_AB;
|
||||
}
|
||||
|
||||
if (idma->dma.dma_mode == DMA_MODE_READ)
|
||||
ctrl |= DMA_CR_D;
|
||||
|
||||
iomd_writeb(ctrl, dma_base + CR);
|
||||
writeb(ctrl, base + CR);
|
||||
enable_irq(idma->irq);
|
||||
}
|
||||
|
||||
static void iomd_disable_dma(unsigned int chan, dma_t *dma)
|
||||
{
|
||||
struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
|
||||
unsigned long dma_base = idma->base;
|
||||
void __iomem *base = idma->base;
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
if (idma->state != ~DMA_ST_AB)
|
||||
disable_irq(idma->irq);
|
||||
iomd_writeb(0, dma_base + CR);
|
||||
writeb(0, base + CR);
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
|
@ -360,17 +361,17 @@ static int __init rpc_dma_init(void)
|
|||
*/
|
||||
iomd_writeb(DMA_EXT_IO3|DMA_EXT_IO2, IOMD_DMAEXT);
|
||||
|
||||
iomd_dma[DMA_0].base = IOMD_IO0CURA;
|
||||
iomd_dma[DMA_0].base = IOMD_BASE + IOMD_IO0CURA;
|
||||
iomd_dma[DMA_0].irq = IRQ_DMA0;
|
||||
iomd_dma[DMA_1].base = IOMD_IO1CURA;
|
||||
iomd_dma[DMA_1].base = IOMD_BASE + IOMD_IO1CURA;
|
||||
iomd_dma[DMA_1].irq = IRQ_DMA1;
|
||||
iomd_dma[DMA_2].base = IOMD_IO2CURA;
|
||||
iomd_dma[DMA_2].base = IOMD_BASE + IOMD_IO2CURA;
|
||||
iomd_dma[DMA_2].irq = IRQ_DMA2;
|
||||
iomd_dma[DMA_3].base = IOMD_IO3CURA;
|
||||
iomd_dma[DMA_3].base = IOMD_BASE + IOMD_IO3CURA;
|
||||
iomd_dma[DMA_3].irq = IRQ_DMA3;
|
||||
iomd_dma[DMA_S0].base = IOMD_SD0CURA;
|
||||
iomd_dma[DMA_S0].base = IOMD_BASE + IOMD_SD0CURA;
|
||||
iomd_dma[DMA_S0].irq = IRQ_DMAS0;
|
||||
iomd_dma[DMA_S1].base = IOMD_SD1CURA;
|
||||
iomd_dma[DMA_S1].base = IOMD_BASE + IOMD_SD1CURA;
|
||||
iomd_dma[DMA_S1].irq = IRQ_DMAS1;
|
||||
|
||||
for (i = DMA_0; i <= DMA_S1; i++) {
|
||||
|
|
|
@ -67,17 +67,21 @@ struct expcard_blacklist {
|
|||
unsigned short manufacturer;
|
||||
unsigned short product;
|
||||
const char *type;
|
||||
void (*init)(ecard_t *ec);
|
||||
};
|
||||
|
||||
static ecard_t *cards;
|
||||
static ecard_t *slot_to_expcard[MAX_ECARDS];
|
||||
static unsigned int ectcr;
|
||||
|
||||
static void atomwide_3p_quirk(ecard_t *ec);
|
||||
|
||||
/* List of descriptions of cards which don't have an extended
|
||||
* identification, or chunk directories containing a description.
|
||||
*/
|
||||
static struct expcard_blacklist __initdata blacklist[] = {
|
||||
{ MANU_ACORN, PROD_ACORN_ETHER1, "Acorn Ether1" }
|
||||
{ MANU_ACORN, PROD_ACORN_ETHER1, "Acorn Ether1" },
|
||||
{ MANU_ATOMWIDE, PROD_ATOMWIDE_3PSERIAL, NULL, atomwide_3p_quirk },
|
||||
};
|
||||
|
||||
asmlinkage extern int
|
||||
|
@ -493,18 +497,21 @@ static void ecard_dump_irq_state(void)
|
|||
printk("Expansion card IRQ state:\n");
|
||||
|
||||
for (ec = cards; ec; ec = ec->next) {
|
||||
const char *claimed;
|
||||
|
||||
if (ec->slot_no == 8)
|
||||
continue;
|
||||
|
||||
printk(" %d: %sclaimed, ",
|
||||
ec->slot_no, ec->claimed ? "" : "not ");
|
||||
claimed = ec->claimed ? "" : "not ";
|
||||
|
||||
if (ec->ops && ec->ops->irqpending &&
|
||||
ec->ops != &ecard_default_ops)
|
||||
printk("irq %spending\n",
|
||||
printk(" %d: %sclaimed irq %spending\n",
|
||||
ec->slot_no, claimed,
|
||||
ec->ops->irqpending(ec) ? "" : "not ");
|
||||
else
|
||||
printk("irqaddr %p, mask = %02X, status = %02X\n",
|
||||
printk(" %d: %sclaimed irqaddr %p, mask = %02X, status = %02X\n",
|
||||
ec->slot_no, claimed,
|
||||
ec->irqaddr, ec->irqmask, readb(ec->irqaddr));
|
||||
}
|
||||
}
|
||||
|
@ -865,6 +872,16 @@ void __iomem *ecardm_iomap(struct expansion_card *ec, unsigned int res,
|
|||
}
|
||||
EXPORT_SYMBOL(ecardm_iomap);
|
||||
|
||||
static void atomwide_3p_quirk(ecard_t *ec)
|
||||
{
|
||||
void __iomem *addr = __ecard_address(ec, ECARD_IOC, ECARD_SYNC);
|
||||
unsigned int i;
|
||||
|
||||
/* Disable interrupts on each port */
|
||||
for (i = 0x2000; i <= 0x2800; i += 0x0400)
|
||||
writeb(0, addr + i + 4);
|
||||
}
|
||||
|
||||
/*
|
||||
* Probe for an expansion card.
|
||||
*
|
||||
|
@ -921,7 +938,10 @@ static int __init ecard_probe(int slot, unsigned irq, card_type_t type)
|
|||
for (i = 0; i < ARRAY_SIZE(blacklist); i++)
|
||||
if (blacklist[i].manufacturer == ec->cid.manufacturer &&
|
||||
blacklist[i].product == ec->cid.product) {
|
||||
ec->card_desc = blacklist[i].type;
|
||||
if (blacklist[i].type)
|
||||
ec->card_desc = blacklist[i].type;
|
||||
if (blacklist[i].init)
|
||||
blacklist[i].init(ec);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
|
@ -115,29 +115,22 @@ static void arch_decomp_setup(void)
|
|||
struct tag *t = (struct tag *)params;
|
||||
unsigned int nr_pages = 0, page_size = PAGE_SIZE;
|
||||
|
||||
if (t->hdr.tag == ATAG_CORE)
|
||||
{
|
||||
for (; t->hdr.size; t = tag_next(t))
|
||||
{
|
||||
if (t->hdr.tag == ATAG_VIDEOTEXT)
|
||||
{
|
||||
if (t->hdr.tag == ATAG_CORE) {
|
||||
for (; t->hdr.size; t = tag_next(t)) {
|
||||
if (t->hdr.tag == ATAG_VIDEOTEXT) {
|
||||
video_num_rows = t->u.videotext.video_lines;
|
||||
video_num_cols = t->u.videotext.video_cols;
|
||||
bytes_per_char_h = t->u.videotext.video_points;
|
||||
bytes_per_char_v = t->u.videotext.video_points;
|
||||
video_x = t->u.videotext.x;
|
||||
video_y = t->u.videotext.y;
|
||||
}
|
||||
|
||||
if (t->hdr.tag == ATAG_MEM)
|
||||
{
|
||||
} else if (t->hdr.tag == ATAG_VIDEOLFB) {
|
||||
bytes_per_char_h = t->u.videolfb.lfb_depth;
|
||||
bytes_per_char_v = 8;
|
||||
} else if (t->hdr.tag == ATAG_MEM) {
|
||||
page_size = PAGE_SIZE;
|
||||
nr_pages += (t->u.mem.size / PAGE_SIZE);
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
} else {
|
||||
nr_pages = params->nr_pages;
|
||||
page_size = params->page_size;
|
||||
video_num_rows = params->video_num_rows;
|
||||
|
|
|
@ -8,117 +8,71 @@
|
|||
#include <asm/irq.h>
|
||||
#include <asm/fiq.h>
|
||||
|
||||
static void iomd_ack_irq_a(struct irq_data *d)
|
||||
{
|
||||
unsigned int val, mask;
|
||||
// These are offsets from the stat register for each IRQ bank
|
||||
#define STAT 0x00
|
||||
#define REQ 0x04
|
||||
#define CLR 0x04
|
||||
#define MASK 0x08
|
||||
|
||||
mask = 1 << d->irq;
|
||||
val = iomd_readb(IOMD_IRQMASKA);
|
||||
iomd_writeb(val & ~mask, IOMD_IRQMASKA);
|
||||
iomd_writeb(mask, IOMD_IRQCLRA);
|
||||
static void __iomem *iomd_get_base(struct irq_data *d)
|
||||
{
|
||||
void *cd = irq_data_get_irq_chip_data(d);
|
||||
|
||||
return (void __iomem *)(unsigned long)cd;
|
||||
}
|
||||
|
||||
static void iomd_mask_irq_a(struct irq_data *d)
|
||||
static void iomd_set_base_mask(unsigned int irq, void __iomem *base, u32 mask)
|
||||
{
|
||||
unsigned int val, mask;
|
||||
struct irq_data *d = irq_get_irq_data(irq);
|
||||
|
||||
mask = 1 << d->irq;
|
||||
val = iomd_readb(IOMD_IRQMASKA);
|
||||
iomd_writeb(val & ~mask, IOMD_IRQMASKA);
|
||||
d->mask = mask;
|
||||
irq_set_chip_data(irq, (void *)(unsigned long)base);
|
||||
}
|
||||
|
||||
static void iomd_unmask_irq_a(struct irq_data *d)
|
||||
static void iomd_irq_mask_ack(struct irq_data *d)
|
||||
{
|
||||
unsigned int val, mask;
|
||||
void __iomem *base = iomd_get_base(d);
|
||||
unsigned int val, mask = d->mask;
|
||||
|
||||
mask = 1 << d->irq;
|
||||
val = iomd_readb(IOMD_IRQMASKA);
|
||||
iomd_writeb(val | mask, IOMD_IRQMASKA);
|
||||
val = readb(base + MASK);
|
||||
writeb(val & ~mask, base + MASK);
|
||||
writeb(mask, base + CLR);
|
||||
}
|
||||
|
||||
static struct irq_chip iomd_a_chip = {
|
||||
.irq_ack = iomd_ack_irq_a,
|
||||
.irq_mask = iomd_mask_irq_a,
|
||||
.irq_unmask = iomd_unmask_irq_a,
|
||||
static void iomd_irq_mask(struct irq_data *d)
|
||||
{
|
||||
void __iomem *base = iomd_get_base(d);
|
||||
unsigned int val, mask = d->mask;
|
||||
|
||||
val = readb(base + MASK);
|
||||
writeb(val & ~mask, base + MASK);
|
||||
}
|
||||
|
||||
static void iomd_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
void __iomem *base = iomd_get_base(d);
|
||||
unsigned int val, mask = d->mask;
|
||||
|
||||
val = readb(base + MASK);
|
||||
writeb(val | mask, base + MASK);
|
||||
}
|
||||
|
||||
static struct irq_chip iomd_chip_clr = {
|
||||
.irq_mask_ack = iomd_irq_mask_ack,
|
||||
.irq_mask = iomd_irq_mask,
|
||||
.irq_unmask = iomd_irq_unmask,
|
||||
};
|
||||
|
||||
static void iomd_mask_irq_b(struct irq_data *d)
|
||||
{
|
||||
unsigned int val, mask;
|
||||
|
||||
mask = 1 << (d->irq & 7);
|
||||
val = iomd_readb(IOMD_IRQMASKB);
|
||||
iomd_writeb(val & ~mask, IOMD_IRQMASKB);
|
||||
}
|
||||
|
||||
static void iomd_unmask_irq_b(struct irq_data *d)
|
||||
{
|
||||
unsigned int val, mask;
|
||||
|
||||
mask = 1 << (d->irq & 7);
|
||||
val = iomd_readb(IOMD_IRQMASKB);
|
||||
iomd_writeb(val | mask, IOMD_IRQMASKB);
|
||||
}
|
||||
|
||||
static struct irq_chip iomd_b_chip = {
|
||||
.irq_ack = iomd_mask_irq_b,
|
||||
.irq_mask = iomd_mask_irq_b,
|
||||
.irq_unmask = iomd_unmask_irq_b,
|
||||
};
|
||||
|
||||
static void iomd_mask_irq_dma(struct irq_data *d)
|
||||
{
|
||||
unsigned int val, mask;
|
||||
|
||||
mask = 1 << (d->irq & 7);
|
||||
val = iomd_readb(IOMD_DMAMASK);
|
||||
iomd_writeb(val & ~mask, IOMD_DMAMASK);
|
||||
}
|
||||
|
||||
static void iomd_unmask_irq_dma(struct irq_data *d)
|
||||
{
|
||||
unsigned int val, mask;
|
||||
|
||||
mask = 1 << (d->irq & 7);
|
||||
val = iomd_readb(IOMD_DMAMASK);
|
||||
iomd_writeb(val | mask, IOMD_DMAMASK);
|
||||
}
|
||||
|
||||
static struct irq_chip iomd_dma_chip = {
|
||||
.irq_ack = iomd_mask_irq_dma,
|
||||
.irq_mask = iomd_mask_irq_dma,
|
||||
.irq_unmask = iomd_unmask_irq_dma,
|
||||
};
|
||||
|
||||
static void iomd_mask_irq_fiq(struct irq_data *d)
|
||||
{
|
||||
unsigned int val, mask;
|
||||
|
||||
mask = 1 << (d->irq & 7);
|
||||
val = iomd_readb(IOMD_FIQMASK);
|
||||
iomd_writeb(val & ~mask, IOMD_FIQMASK);
|
||||
}
|
||||
|
||||
static void iomd_unmask_irq_fiq(struct irq_data *d)
|
||||
{
|
||||
unsigned int val, mask;
|
||||
|
||||
mask = 1 << (d->irq & 7);
|
||||
val = iomd_readb(IOMD_FIQMASK);
|
||||
iomd_writeb(val | mask, IOMD_FIQMASK);
|
||||
}
|
||||
|
||||
static struct irq_chip iomd_fiq_chip = {
|
||||
.irq_ack = iomd_mask_irq_fiq,
|
||||
.irq_mask = iomd_mask_irq_fiq,
|
||||
.irq_unmask = iomd_unmask_irq_fiq,
|
||||
static struct irq_chip iomd_chip_noclr = {
|
||||
.irq_mask = iomd_irq_mask,
|
||||
.irq_unmask = iomd_irq_unmask,
|
||||
};
|
||||
|
||||
extern unsigned char rpc_default_fiq_start, rpc_default_fiq_end;
|
||||
|
||||
void __init rpc_init_irq(void)
|
||||
{
|
||||
unsigned int irq, clr, set = 0;
|
||||
unsigned int irq, clr, set;
|
||||
|
||||
iomd_writeb(0, IOMD_IRQMASKA);
|
||||
iomd_writeb(0, IOMD_IRQMASKB);
|
||||
|
@ -130,6 +84,7 @@ void __init rpc_init_irq(void)
|
|||
|
||||
for (irq = 0; irq < NR_IRQS; irq++) {
|
||||
clr = IRQ_NOREQUEST;
|
||||
set = 0;
|
||||
|
||||
if (irq <= 6 || (irq >= 9 && irq <= 15))
|
||||
clr |= IRQ_NOPROBE;
|
||||
|
@ -140,30 +95,37 @@ void __init rpc_init_irq(void)
|
|||
|
||||
switch (irq) {
|
||||
case 0 ... 7:
|
||||
irq_set_chip_and_handler(irq, &iomd_a_chip,
|
||||
irq_set_chip_and_handler(irq, &iomd_chip_clr,
|
||||
handle_level_irq);
|
||||
irq_modify_status(irq, clr, set);
|
||||
iomd_set_base_mask(irq, IOMD_BASE + IOMD_IRQSTATA,
|
||||
BIT(irq));
|
||||
break;
|
||||
|
||||
case 8 ... 15:
|
||||
irq_set_chip_and_handler(irq, &iomd_b_chip,
|
||||
irq_set_chip_and_handler(irq, &iomd_chip_noclr,
|
||||
handle_level_irq);
|
||||
irq_modify_status(irq, clr, set);
|
||||
iomd_set_base_mask(irq, IOMD_BASE + IOMD_IRQSTATB,
|
||||
BIT(irq - 8));
|
||||
break;
|
||||
|
||||
case 16 ... 21:
|
||||
irq_set_chip_and_handler(irq, &iomd_dma_chip,
|
||||
irq_set_chip_and_handler(irq, &iomd_chip_noclr,
|
||||
handle_level_irq);
|
||||
irq_modify_status(irq, clr, set);
|
||||
iomd_set_base_mask(irq, IOMD_BASE + IOMD_DMASTAT,
|
||||
BIT(irq - 16));
|
||||
break;
|
||||
|
||||
case 64 ... 71:
|
||||
irq_set_chip(irq, &iomd_fiq_chip);
|
||||
irq_set_chip(irq, &iomd_chip_noclr);
|
||||
irq_modify_status(irq, clr, set);
|
||||
iomd_set_base_mask(irq, IOMD_BASE + IOMD_FIQSTAT,
|
||||
BIT(irq - 64));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
init_FIQ(FIQ_START);
|
||||
}
|
||||
|
||||
|
|
|
@ -10,7 +10,7 @@
|
|||
* 04-Dec-1997 RMK Updated for new arch/arm/time.c
|
||||
* 13=Jun-2004 DS Moved to arch/arm/common b/c shared w/CLPS7500
|
||||
*/
|
||||
#include <linux/timex.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
|
@ -24,11 +24,15 @@
|
|||
#define RPC_CLOCK_FREQ 2000000
|
||||
#define RPC_LATCH DIV_ROUND_CLOSEST(RPC_CLOCK_FREQ, HZ)
|
||||
|
||||
static u32 ioc_timer_gettimeoffset(void)
|
||||
static u32 ioc_time;
|
||||
|
||||
static u64 ioc_timer_read(struct clocksource *cs)
|
||||
{
|
||||
unsigned int count1, count2, status;
|
||||
long offset;
|
||||
unsigned long flags;
|
||||
u32 ticks;
|
||||
|
||||
local_irq_save(flags);
|
||||
ioc_writeb (0, IOC_T0LATCH);
|
||||
barrier ();
|
||||
count1 = ioc_readb(IOC_T0CNTL) | (ioc_readb(IOC_T0CNTH) << 8);
|
||||
|
@ -38,27 +42,34 @@ static u32 ioc_timer_gettimeoffset(void)
|
|||
ioc_writeb (0, IOC_T0LATCH);
|
||||
barrier ();
|
||||
count2 = ioc_readb(IOC_T0CNTL) | (ioc_readb(IOC_T0CNTH) << 8);
|
||||
ticks = ioc_time + RPC_LATCH - count2;
|
||||
local_irq_restore(flags);
|
||||
|
||||
offset = count2;
|
||||
if (count2 < count1) {
|
||||
/*
|
||||
* We have not had an interrupt between reading count1
|
||||
* and count2.
|
||||
* The timer has not reloaded between reading count1 and
|
||||
* count2, check whether an interrupt was actually pending.
|
||||
*/
|
||||
if (status & (1 << 5))
|
||||
offset -= RPC_LATCH;
|
||||
ticks += RPC_LATCH;
|
||||
} else if (count2 > count1) {
|
||||
/*
|
||||
* We have just had another interrupt between reading
|
||||
* count1 and count2.
|
||||
* The timer has reloaded, so count2 indicates the new
|
||||
* count since the wrap. The interrupt would not have
|
||||
* been processed, so add the missed ticks.
|
||||
*/
|
||||
offset -= RPC_LATCH;
|
||||
ticks += RPC_LATCH;
|
||||
}
|
||||
|
||||
offset = (RPC_LATCH - offset) * (tick_nsec / 1000);
|
||||
return DIV_ROUND_CLOSEST(offset, RPC_LATCH) * 1000;
|
||||
return ticks;
|
||||
}
|
||||
|
||||
static struct clocksource ioctime_clocksource = {
|
||||
.read = ioc_timer_read,
|
||||
.mask = CLOCKSOURCE_MASK(32),
|
||||
.rating = 100,
|
||||
};
|
||||
|
||||
void __init ioctime_init(void)
|
||||
{
|
||||
ioc_writeb(RPC_LATCH & 255, IOC_T0LTCHL);
|
||||
|
@ -69,6 +80,7 @@ void __init ioctime_init(void)
|
|||
static irqreturn_t
|
||||
ioc_timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
ioc_time += RPC_LATCH;
|
||||
timer_tick();
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
@ -83,7 +95,7 @@ static struct irqaction ioc_timer_irq = {
|
|||
*/
|
||||
void __init ioc_timer_init(void)
|
||||
{
|
||||
arch_gettimeoffset = ioc_timer_gettimeoffset;
|
||||
WARN_ON(clocksource_register_hz(&ioctime_clocksource, RPC_CLOCK_FREQ));
|
||||
ioctime_init();
|
||||
setup_irq(IRQ_TIMER0, &ioc_timer_irq);
|
||||
}
|
||||
|
|
|
@ -519,6 +519,29 @@ static const struct gpio_keys_platform_data assabet_keys_pdata = {
|
|||
.rep = 0,
|
||||
};
|
||||
|
||||
static struct gpiod_lookup_table assabet_uart1_gpio_table = {
|
||||
.dev_id = "sa11x0-uart.1",
|
||||
.table = {
|
||||
GPIO_LOOKUP("assabet", 16, "dtr", GPIO_ACTIVE_LOW),
|
||||
GPIO_LOOKUP("assabet", 17, "rts", GPIO_ACTIVE_LOW),
|
||||
GPIO_LOOKUP("assabet", 25, "dcd", GPIO_ACTIVE_LOW),
|
||||
GPIO_LOOKUP("assabet", 26, "cts", GPIO_ACTIVE_LOW),
|
||||
GPIO_LOOKUP("assabet", 27, "dsr", GPIO_ACTIVE_LOW),
|
||||
{ },
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpiod_lookup_table assabet_uart3_gpio_table = {
|
||||
.dev_id = "sa11x0-uart.3",
|
||||
.table = {
|
||||
GPIO_LOOKUP("assabet", 28, "cts", GPIO_ACTIVE_LOW),
|
||||
GPIO_LOOKUP("assabet", 29, "dsr", GPIO_ACTIVE_LOW),
|
||||
GPIO_LOOKUP("assabet", 30, "dcd", GPIO_ACTIVE_LOW),
|
||||
GPIO_LOOKUP("assabet", 31, "rng", GPIO_ACTIVE_LOW),
|
||||
{ },
|
||||
},
|
||||
};
|
||||
|
||||
static void __init assabet_init(void)
|
||||
{
|
||||
/*
|
||||
|
@ -565,7 +588,10 @@ static void __init assabet_init(void)
|
|||
neponset_resources, ARRAY_SIZE(neponset_resources));
|
||||
#endif
|
||||
} else {
|
||||
gpiod_add_lookup_table(&assabet_uart1_gpio_table);
|
||||
gpiod_add_lookup_table(&assabet_uart3_gpio_table);
|
||||
gpiod_add_lookup_table(&assabet_cf_vcc_gpio_table);
|
||||
|
||||
sa11x0_register_fixed_regulator(0, &assabet_cf_vcc_pdata,
|
||||
assabet_cf_vcc_consumers,
|
||||
ARRAY_SIZE(assabet_cf_vcc_consumers),
|
||||
|
@ -655,74 +681,13 @@ static void assabet_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
|
|||
{
|
||||
if (port->mapbase == _Ser1UTCR0) {
|
||||
if (state)
|
||||
ASSABET_BCR_clear(ASSABET_BCR_RS232EN |
|
||||
ASSABET_BCR_COM_RTS |
|
||||
ASSABET_BCR_COM_DTR);
|
||||
ASSABET_BCR_clear(ASSABET_BCR_RS232EN);
|
||||
else
|
||||
ASSABET_BCR_set(ASSABET_BCR_RS232EN |
|
||||
ASSABET_BCR_COM_RTS |
|
||||
ASSABET_BCR_COM_DTR);
|
||||
ASSABET_BCR_set(ASSABET_BCR_RS232EN);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Assabet uses COM_RTS and COM_DTR for both UART1 (com port)
|
||||
* and UART3 (radio module). We only handle them for UART1 here.
|
||||
*/
|
||||
static void assabet_set_mctrl(struct uart_port *port, u_int mctrl)
|
||||
{
|
||||
if (port->mapbase == _Ser1UTCR0) {
|
||||
u_int set = 0, clear = 0;
|
||||
|
||||
if (mctrl & TIOCM_RTS)
|
||||
clear |= ASSABET_BCR_COM_RTS;
|
||||
else
|
||||
set |= ASSABET_BCR_COM_RTS;
|
||||
|
||||
if (mctrl & TIOCM_DTR)
|
||||
clear |= ASSABET_BCR_COM_DTR;
|
||||
else
|
||||
set |= ASSABET_BCR_COM_DTR;
|
||||
|
||||
ASSABET_BCR_clear(clear);
|
||||
ASSABET_BCR_set(set);
|
||||
}
|
||||
}
|
||||
|
||||
static u_int assabet_get_mctrl(struct uart_port *port)
|
||||
{
|
||||
u_int ret = 0;
|
||||
u_int bsr = ASSABET_BSR;
|
||||
|
||||
/* need 2 reads to read current value */
|
||||
bsr = ASSABET_BSR;
|
||||
|
||||
if (port->mapbase == _Ser1UTCR0) {
|
||||
if (bsr & ASSABET_BSR_COM_DCD)
|
||||
ret |= TIOCM_CD;
|
||||
if (bsr & ASSABET_BSR_COM_CTS)
|
||||
ret |= TIOCM_CTS;
|
||||
if (bsr & ASSABET_BSR_COM_DSR)
|
||||
ret |= TIOCM_DSR;
|
||||
} else if (port->mapbase == _Ser3UTCR0) {
|
||||
if (bsr & ASSABET_BSR_RAD_DCD)
|
||||
ret |= TIOCM_CD;
|
||||
if (bsr & ASSABET_BSR_RAD_CTS)
|
||||
ret |= TIOCM_CTS;
|
||||
if (bsr & ASSABET_BSR_RAD_DSR)
|
||||
ret |= TIOCM_DSR;
|
||||
if (bsr & ASSABET_BSR_RAD_RI)
|
||||
ret |= TIOCM_RI;
|
||||
} else {
|
||||
ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct sa1100_port_fns assabet_port_fns __initdata = {
|
||||
.set_mctrl = assabet_set_mctrl,
|
||||
.get_mctrl = assabet_get_mctrl,
|
||||
.pm = assabet_uart_pm,
|
||||
};
|
||||
|
||||
|
|
|
@ -311,8 +311,6 @@ badge4_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
|
|||
}
|
||||
|
||||
static struct sa1100_port_fns badge4_port_fns __initdata = {
|
||||
//.get_mctrl = badge4_get_mctrl,
|
||||
//.set_mctrl = badge4_set_mctrl,
|
||||
.pm = badge4_uart_pm,
|
||||
};
|
||||
|
||||
|
|
|
@ -2,176 +2,144 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-sa1100/clock.c
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/generic.h>
|
||||
|
||||
struct clkops {
|
||||
void (*enable)(struct clk *);
|
||||
void (*disable)(struct clk *);
|
||||
unsigned long (*get_rate)(struct clk *);
|
||||
static const char * const clk_tucr_parents[] = {
|
||||
"clk32768", "clk3686400",
|
||||
};
|
||||
|
||||
struct clk {
|
||||
const struct clkops *ops;
|
||||
unsigned int enabled;
|
||||
};
|
||||
static DEFINE_SPINLOCK(tucr_lock);
|
||||
|
||||
#define DEFINE_CLK(_name, _ops) \
|
||||
struct clk clk_##_name = { \
|
||||
.ops = _ops, \
|
||||
}
|
||||
|
||||
static DEFINE_SPINLOCK(clocks_lock);
|
||||
|
||||
/* Dummy clk routine to build generic kernel parts that may be using them */
|
||||
long clk_round_rate(struct clk *clk, unsigned long rate)
|
||||
static int clk_gpio27_enable(struct clk_hw *hw)
|
||||
{
|
||||
return clk_get_rate(clk);
|
||||
}
|
||||
EXPORT_SYMBOL(clk_round_rate);
|
||||
unsigned long flags;
|
||||
|
||||
int clk_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_set_rate);
|
||||
|
||||
int clk_set_parent(struct clk *clk, struct clk *parent)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_set_parent);
|
||||
|
||||
struct clk *clk_get_parent(struct clk *clk)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_get_parent);
|
||||
|
||||
static void clk_gpio27_enable(struct clk *clk)
|
||||
{
|
||||
/*
|
||||
* First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
|
||||
* (SA-1110 Developer's Manual, section 9.1.2.1)
|
||||
*/
|
||||
local_irq_save(flags);
|
||||
GAFR |= GPIO_32_768kHz;
|
||||
GPDR |= GPIO_32_768kHz;
|
||||
TUCR = TUCR_3_6864MHz;
|
||||
local_irq_restore(flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void clk_gpio27_disable(struct clk *clk)
|
||||
static void clk_gpio27_disable(struct clk_hw *hw)
|
||||
{
|
||||
TUCR = 0;
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
GPDR &= ~GPIO_32_768kHz;
|
||||
GAFR &= ~GPIO_32_768kHz;
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static void clk_cpu_enable(struct clk *clk)
|
||||
{
|
||||
}
|
||||
static const struct clk_ops clk_gpio27_ops = {
|
||||
.enable = clk_gpio27_enable,
|
||||
.disable = clk_gpio27_disable,
|
||||
};
|
||||
|
||||
static void clk_cpu_disable(struct clk *clk)
|
||||
{
|
||||
}
|
||||
static const char * const clk_gpio27_parents[] = {
|
||||
"tucr-mux",
|
||||
};
|
||||
|
||||
static unsigned long clk_cpu_get_rate(struct clk *clk)
|
||||
static const struct clk_init_data clk_gpio27_init_data __initconst = {
|
||||
.name = "gpio27",
|
||||
.ops = &clk_gpio27_ops,
|
||||
.parent_names = clk_gpio27_parents,
|
||||
.num_parents = ARRAY_SIZE(clk_gpio27_parents),
|
||||
};
|
||||
|
||||
/*
|
||||
* Derived from the table 8-1 in the SA1110 manual, the MPLL appears to
|
||||
* multiply its input rate by 4 x (4 + PPCR). This calculation gives
|
||||
* the exact rate. The figures given in the table are the rates rounded
|
||||
* to 100kHz. Stick with sa11x0_getspeed() for the time being.
|
||||
*/
|
||||
static unsigned long clk_mpll_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long prate)
|
||||
{
|
||||
return sa11x0_getspeed(0) * 1000;
|
||||
}
|
||||
|
||||
int clk_enable(struct clk *clk)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
if (clk) {
|
||||
spin_lock_irqsave(&clocks_lock, flags);
|
||||
if (clk->enabled++ == 0)
|
||||
clk->ops->enable(clk);
|
||||
spin_unlock_irqrestore(&clocks_lock, flags);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_enable);
|
||||
|
||||
void clk_disable(struct clk *clk)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
if (clk) {
|
||||
WARN_ON(clk->enabled == 0);
|
||||
spin_lock_irqsave(&clocks_lock, flags);
|
||||
if (--clk->enabled == 0)
|
||||
clk->ops->disable(clk);
|
||||
spin_unlock_irqrestore(&clocks_lock, flags);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(clk_disable);
|
||||
|
||||
unsigned long clk_get_rate(struct clk *clk)
|
||||
{
|
||||
if (clk && clk->ops && clk->ops->get_rate)
|
||||
return clk->ops->get_rate(clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_get_rate);
|
||||
|
||||
const struct clkops clk_gpio27_ops = {
|
||||
.enable = clk_gpio27_enable,
|
||||
.disable = clk_gpio27_disable,
|
||||
static const struct clk_ops clk_mpll_ops = {
|
||||
.recalc_rate = clk_mpll_recalc_rate,
|
||||
};
|
||||
|
||||
const struct clkops clk_cpu_ops = {
|
||||
.enable = clk_cpu_enable,
|
||||
.disable = clk_cpu_disable,
|
||||
.get_rate = clk_cpu_get_rate,
|
||||
static const char * const clk_mpll_parents[] = {
|
||||
"clk3686400",
|
||||
};
|
||||
|
||||
static DEFINE_CLK(gpio27, &clk_gpio27_ops);
|
||||
|
||||
static DEFINE_CLK(cpu, &clk_cpu_ops);
|
||||
|
||||
static unsigned long clk_36864_get_rate(struct clk *clk)
|
||||
{
|
||||
return 3686400;
|
||||
}
|
||||
|
||||
static struct clkops clk_36864_ops = {
|
||||
.enable = clk_cpu_enable,
|
||||
.disable = clk_cpu_disable,
|
||||
.get_rate = clk_36864_get_rate,
|
||||
};
|
||||
|
||||
static DEFINE_CLK(36864, &clk_36864_ops);
|
||||
|
||||
static struct clk_lookup sa11xx_clkregs[] = {
|
||||
CLKDEV_INIT("sa1111.0", NULL, &clk_gpio27),
|
||||
CLKDEV_INIT("sa1100-rtc", NULL, NULL),
|
||||
CLKDEV_INIT("sa11x0-fb", NULL, &clk_cpu),
|
||||
CLKDEV_INIT("sa11x0-pcmcia", NULL, &clk_cpu),
|
||||
CLKDEV_INIT("sa11x0-pcmcia.0", NULL, &clk_cpu),
|
||||
CLKDEV_INIT("sa11x0-pcmcia.1", NULL, &clk_cpu),
|
||||
/* sa1111 names devices using internal offsets, PCMCIA is at 0x1800 */
|
||||
CLKDEV_INIT("1800", NULL, &clk_cpu),
|
||||
CLKDEV_INIT(NULL, "OSTIMER0", &clk_36864),
|
||||
static const struct clk_init_data clk_mpll_init_data __initconst = {
|
||||
.name = "mpll",
|
||||
.ops = &clk_mpll_ops,
|
||||
.parent_names = clk_mpll_parents,
|
||||
.num_parents = ARRAY_SIZE(clk_mpll_parents),
|
||||
.flags = CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL,
|
||||
};
|
||||
|
||||
int __init sa11xx_clk_init(void)
|
||||
{
|
||||
clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs));
|
||||
struct clk_hw *hw;
|
||||
int ret;
|
||||
|
||||
hw = clk_hw_register_fixed_rate(NULL, "clk32768", NULL, 0, 32768);
|
||||
if (IS_ERR(hw))
|
||||
return PTR_ERR(hw);
|
||||
|
||||
clk_hw_register_clkdev(hw, NULL, "sa1100-rtc");
|
||||
|
||||
hw = clk_hw_register_fixed_rate(NULL, "clk3686400", NULL, 0, 3686400);
|
||||
if (IS_ERR(hw))
|
||||
return PTR_ERR(hw);
|
||||
|
||||
clk_hw_register_clkdev(hw, "OSTIMER0", NULL);
|
||||
|
||||
hw = kzalloc(sizeof(*hw), GFP_KERNEL);
|
||||
if (!hw)
|
||||
return -ENOMEM;
|
||||
hw->init = &clk_mpll_init_data;
|
||||
ret = clk_hw_register(NULL, hw);
|
||||
if (ret) {
|
||||
kfree(hw);
|
||||
return ret;
|
||||
}
|
||||
|
||||
clk_hw_register_clkdev(hw, NULL, "sa11x0-fb");
|
||||
clk_hw_register_clkdev(hw, NULL, "sa11x0-pcmcia");
|
||||
clk_hw_register_clkdev(hw, NULL, "sa11x0-pcmcia.0");
|
||||
clk_hw_register_clkdev(hw, NULL, "sa11x0-pcmcia.1");
|
||||
clk_hw_register_clkdev(hw, NULL, "1800");
|
||||
|
||||
hw = clk_hw_register_mux(NULL, "tucr-mux", clk_tucr_parents,
|
||||
ARRAY_SIZE(clk_tucr_parents), 0,
|
||||
(void __iomem *)&TUCR, FShft(TUCR_TSEL),
|
||||
FAlnMsk(TUCR_TSEL), 0, &tucr_lock);
|
||||
clk_set_rate(hw->clk, 3686400);
|
||||
|
||||
hw = kzalloc(sizeof(*hw), GFP_KERNEL);
|
||||
if (!hw)
|
||||
return -ENOMEM;
|
||||
hw->init = &clk_gpio27_init_data;
|
||||
ret = clk_hw_register(NULL, hw);
|
||||
if (ret) {
|
||||
kfree(hw);
|
||||
return ret;
|
||||
}
|
||||
|
||||
clk_hw_register_clkdev(hw, NULL, "sa1111.0");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -83,57 +83,6 @@ static struct resource h3xxx_flash_resource =
|
|||
/*
|
||||
* H3xxx uart support
|
||||
*/
|
||||
static struct gpio h3xxx_uart_gpio[] = {
|
||||
{ H3XXX_GPIO_COM_DCD, GPIOF_IN, "COM DCD" },
|
||||
{ H3XXX_GPIO_COM_CTS, GPIOF_IN, "COM CTS" },
|
||||
{ H3XXX_GPIO_COM_RTS, GPIOF_OUT_INIT_LOW, "COM RTS" },
|
||||
};
|
||||
|
||||
static bool h3xxx_uart_request_gpios(void)
|
||||
{
|
||||
static bool h3xxx_uart_gpio_ok;
|
||||
int rc;
|
||||
|
||||
if (h3xxx_uart_gpio_ok)
|
||||
return true;
|
||||
|
||||
rc = gpio_request_array(h3xxx_uart_gpio, ARRAY_SIZE(h3xxx_uart_gpio));
|
||||
if (rc)
|
||||
pr_err("h3xxx_uart_request_gpios: error %d\n", rc);
|
||||
else
|
||||
h3xxx_uart_gpio_ok = true;
|
||||
|
||||
return h3xxx_uart_gpio_ok;
|
||||
}
|
||||
|
||||
static void h3xxx_uart_set_mctrl(struct uart_port *port, u_int mctrl)
|
||||
{
|
||||
if (port->mapbase == _Ser3UTCR0) {
|
||||
if (!h3xxx_uart_request_gpios())
|
||||
return;
|
||||
gpio_set_value(H3XXX_GPIO_COM_RTS, !(mctrl & TIOCM_RTS));
|
||||
}
|
||||
}
|
||||
|
||||
static u_int h3xxx_uart_get_mctrl(struct uart_port *port)
|
||||
{
|
||||
u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
|
||||
|
||||
if (port->mapbase == _Ser3UTCR0) {
|
||||
if (!h3xxx_uart_request_gpios())
|
||||
return ret;
|
||||
/*
|
||||
* DCD and CTS bits are inverted in GPLR by RS232 transceiver
|
||||
*/
|
||||
if (gpio_get_value(H3XXX_GPIO_COM_DCD))
|
||||
ret &= ~TIOCM_CD;
|
||||
if (gpio_get_value(H3XXX_GPIO_COM_CTS))
|
||||
ret &= ~TIOCM_CTS;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void h3xxx_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
|
||||
{
|
||||
if (port->mapbase == _Ser3UTCR0) {
|
||||
|
@ -166,12 +115,20 @@ static int h3xxx_uart_set_wake(struct uart_port *port, u_int enable)
|
|||
}
|
||||
|
||||
static struct sa1100_port_fns h3xxx_port_fns __initdata = {
|
||||
.set_mctrl = h3xxx_uart_set_mctrl,
|
||||
.get_mctrl = h3xxx_uart_get_mctrl,
|
||||
.pm = h3xxx_uart_pm,
|
||||
.set_wake = h3xxx_uart_set_wake,
|
||||
};
|
||||
|
||||
static struct gpiod_lookup_table h3xxx_uart3_gpio_table = {
|
||||
.dev_id = "sa11x0-uart.3",
|
||||
.table = {
|
||||
GPIO_LOOKUP("gpio", H3XXX_GPIO_COM_DCD, "dcd", GPIO_ACTIVE_LOW),
|
||||
GPIO_LOOKUP("gpio", H3XXX_GPIO_COM_CTS, "cts", GPIO_ACTIVE_LOW),
|
||||
GPIO_LOOKUP("gpio", H3XXX_GPIO_COM_RTS, "rts", GPIO_ACTIVE_LOW),
|
||||
{ },
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* EGPIO
|
||||
*/
|
||||
|
@ -279,6 +236,7 @@ static struct gpiod_lookup_table h3xxx_pcmcia_gpio_table = {
|
|||
void __init h3xxx_mach_init(void)
|
||||
{
|
||||
gpiod_add_lookup_table(&h3xxx_pcmcia_gpio_table);
|
||||
gpiod_add_lookup_table(&h3xxx_uart3_gpio_table);
|
||||
sa1100_register_uart_fns(&h3xxx_port_fns);
|
||||
sa11x0_register_mtd(&h3xxx_flash_data, &h3xxx_flash_resource, 1);
|
||||
platform_add_devices(h3xxx_devices, ARRAY_SIZE(h3xxx_devices));
|
||||
|
|
|
@ -45,8 +45,6 @@
|
|||
/* init funcs */
|
||||
static void __init hackkit_map_io(void);
|
||||
|
||||
static u_int hackkit_get_mctrl(struct uart_port *port);
|
||||
static void hackkit_set_mctrl(struct uart_port *port, u_int mctrl);
|
||||
static void hackkit_uart_pm(struct uart_port *port, u_int state, u_int oldstate);
|
||||
|
||||
/**********************************************************************
|
||||
|
@ -67,8 +65,6 @@ static struct map_desc hackkit_io_desc[] __initdata = {
|
|||
};
|
||||
|
||||
static struct sa1100_port_fns hackkit_port_fns __initdata = {
|
||||
.set_mctrl = hackkit_set_mctrl,
|
||||
.get_mctrl = hackkit_get_mctrl,
|
||||
.pm = hackkit_uart_pm,
|
||||
};
|
||||
|
||||
|
@ -101,50 +97,6 @@ static void hackkit_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
|
|||
/* TODO: switch on/off uart in powersave mode */
|
||||
}
|
||||
|
||||
/*
|
||||
* Note! this can be called from IRQ context.
|
||||
* FIXME: No modem ctrl lines yet.
|
||||
*/
|
||||
static void hackkit_set_mctrl(struct uart_port *port, u_int mctrl)
|
||||
{
|
||||
#if 0
|
||||
if (port->mapbase == _Ser1UTCR0) {
|
||||
u_int set = 0, clear = 0;
|
||||
|
||||
if (mctrl & TIOCM_RTS)
|
||||
set |= PT_CTRL2_RS1_RTS;
|
||||
else
|
||||
clear |= PT_CTRL2_RS1_RTS;
|
||||
|
||||
if (mctrl & TIOCM_DTR)
|
||||
set |= PT_CTRL2_RS1_DTR;
|
||||
else
|
||||
clear |= PT_CTRL2_RS1_DTR;
|
||||
|
||||
PTCTRL2_clear(clear);
|
||||
PTCTRL2_set(set);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
static u_int hackkit_get_mctrl(struct uart_port *port)
|
||||
{
|
||||
u_int ret = 0;
|
||||
#if 0
|
||||
u_int irqsr = PT_IRQSR;
|
||||
|
||||
/* need 2 reads to read current value */
|
||||
irqsr = PT_IRQSR;
|
||||
|
||||
/* TODO: check IRQ source register for modem/com
|
||||
status lines and set them correctly. */
|
||||
#endif
|
||||
|
||||
ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct mtd_partition hackkit_partitions[] = {
|
||||
{
|
||||
.name = "BLOB",
|
||||
|
|
|
@ -11,7 +11,6 @@
|
|||
#include <linux/irq.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_data/sa11x0-serial.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm.h>
|
||||
#include <linux/serial_core.h>
|
||||
|
@ -49,23 +48,8 @@
|
|||
#define IRR_SA1111 (1 << 2)
|
||||
|
||||
#define NCR_NGPIO 7
|
||||
|
||||
#define MDM_CTL0_RTS1 (1 << 0)
|
||||
#define MDM_CTL0_DTR1 (1 << 1)
|
||||
#define MDM_CTL0_RTS2 (1 << 2)
|
||||
#define MDM_CTL0_DTR2 (1 << 3)
|
||||
#define MDM_CTL0_NGPIO 4
|
||||
|
||||
#define MDM_CTL1_CTS1 (1 << 0)
|
||||
#define MDM_CTL1_DSR1 (1 << 1)
|
||||
#define MDM_CTL1_DCD1 (1 << 2)
|
||||
#define MDM_CTL1_CTS2 (1 << 3)
|
||||
#define MDM_CTL1_DSR2 (1 << 4)
|
||||
#define MDM_CTL1_DCD2 (1 << 5)
|
||||
#define MDM_CTL1_NGPIO 6
|
||||
|
||||
#define AUD_SEL_1341 (1 << 0)
|
||||
#define AUD_MUTE_1341 (1 << 1)
|
||||
#define AUD_NGPIO 2
|
||||
|
||||
extern void sa1110_mb_disable(void);
|
||||
|
@ -97,6 +81,30 @@ struct neponset_drvdata {
|
|||
struct gpio_chip *gpio[4];
|
||||
};
|
||||
|
||||
static struct gpiod_lookup_table neponset_uart1_gpio_table = {
|
||||
.dev_id = "sa11x0-uart.1",
|
||||
.table = {
|
||||
GPIO_LOOKUP("neponset-mdm-ctl0", 2, "rts", GPIO_ACTIVE_LOW),
|
||||
GPIO_LOOKUP("neponset-mdm-ctl0", 3, "dtr", GPIO_ACTIVE_LOW),
|
||||
GPIO_LOOKUP("neponset-mdm-ctl1", 3, "cts", GPIO_ACTIVE_LOW),
|
||||
GPIO_LOOKUP("neponset-mdm-ctl1", 4, "dsr", GPIO_ACTIVE_LOW),
|
||||
GPIO_LOOKUP("neponset-mdm-ctl1", 5, "dcd", GPIO_ACTIVE_LOW),
|
||||
{ },
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpiod_lookup_table neponset_uart3_gpio_table = {
|
||||
.dev_id = "sa11x0-uart.3",
|
||||
.table = {
|
||||
GPIO_LOOKUP("neponset-mdm-ctl0", 0, "rts", GPIO_ACTIVE_LOW),
|
||||
GPIO_LOOKUP("neponset-mdm-ctl0", 1, "dtr", GPIO_ACTIVE_LOW),
|
||||
GPIO_LOOKUP("neponset-mdm-ctl1", 0, "cts", GPIO_ACTIVE_LOW),
|
||||
GPIO_LOOKUP("neponset-mdm-ctl1", 1, "dsr", GPIO_ACTIVE_LOW),
|
||||
GPIO_LOOKUP("neponset-mdm-ctl1", 2, "dcd", GPIO_ACTIVE_LOW),
|
||||
{ },
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpiod_lookup_table neponset_pcmcia_table = {
|
||||
.dev_id = "1800",
|
||||
.table = {
|
||||
|
@ -124,69 +132,6 @@ void neponset_ncr_frob(unsigned int mask, unsigned int val)
|
|||
}
|
||||
EXPORT_SYMBOL(neponset_ncr_frob);
|
||||
|
||||
static void neponset_set_mctrl(struct uart_port *port, u_int mctrl)
|
||||
{
|
||||
struct neponset_drvdata *n = nep;
|
||||
unsigned long mask, val = 0;
|
||||
|
||||
if (!n)
|
||||
return;
|
||||
|
||||
if (port->mapbase == _Ser1UTCR0) {
|
||||
mask = MDM_CTL0_RTS2 | MDM_CTL0_DTR2;
|
||||
|
||||
if (!(mctrl & TIOCM_RTS))
|
||||
val |= MDM_CTL0_RTS2;
|
||||
|
||||
if (!(mctrl & TIOCM_DTR))
|
||||
val |= MDM_CTL0_DTR2;
|
||||
} else if (port->mapbase == _Ser3UTCR0) {
|
||||
mask = MDM_CTL0_RTS1 | MDM_CTL0_DTR1;
|
||||
|
||||
if (!(mctrl & TIOCM_RTS))
|
||||
val |= MDM_CTL0_RTS1;
|
||||
|
||||
if (!(mctrl & TIOCM_DTR))
|
||||
val |= MDM_CTL0_DTR1;
|
||||
}
|
||||
|
||||
n->gpio[1]->set_multiple(n->gpio[1], &mask, &val);
|
||||
}
|
||||
|
||||
static u_int neponset_get_mctrl(struct uart_port *port)
|
||||
{
|
||||
void __iomem *base = nep->base;
|
||||
u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
|
||||
u_int mdm_ctl1;
|
||||
|
||||
if (!base)
|
||||
return ret;
|
||||
|
||||
mdm_ctl1 = readb_relaxed(base + MDM_CTL_1);
|
||||
if (port->mapbase == _Ser1UTCR0) {
|
||||
if (mdm_ctl1 & MDM_CTL1_DCD2)
|
||||
ret &= ~TIOCM_CD;
|
||||
if (mdm_ctl1 & MDM_CTL1_CTS2)
|
||||
ret &= ~TIOCM_CTS;
|
||||
if (mdm_ctl1 & MDM_CTL1_DSR2)
|
||||
ret &= ~TIOCM_DSR;
|
||||
} else if (port->mapbase == _Ser3UTCR0) {
|
||||
if (mdm_ctl1 & MDM_CTL1_DCD1)
|
||||
ret &= ~TIOCM_CD;
|
||||
if (mdm_ctl1 & MDM_CTL1_CTS1)
|
||||
ret &= ~TIOCM_CTS;
|
||||
if (mdm_ctl1 & MDM_CTL1_DSR1)
|
||||
ret &= ~TIOCM_DSR;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct sa1100_port_fns neponset_port_fns = {
|
||||
.set_mctrl = neponset_set_mctrl,
|
||||
.get_mctrl = neponset_get_mctrl,
|
||||
};
|
||||
|
||||
/*
|
||||
* Install handler for Neponset IRQ. Note that we have to loop here
|
||||
* since the ETHERNET and USAR IRQs are level based, and we need to
|
||||
|
@ -388,6 +333,8 @@ static int neponset_probe(struct platform_device *dev)
|
|||
d->base + AUD_CTL, AUD_NGPIO, false,
|
||||
neponset_aud_names);
|
||||
|
||||
gpiod_add_lookup_table(&neponset_uart1_gpio_table);
|
||||
gpiod_add_lookup_table(&neponset_uart3_gpio_table);
|
||||
gpiod_add_lookup_table(&neponset_pcmcia_table);
|
||||
|
||||
/*
|
||||
|
@ -402,8 +349,6 @@ static int neponset_probe(struct platform_device *dev)
|
|||
d->irq_base, d->irq_base + NEP_IRQ_NR - 1);
|
||||
nep = d;
|
||||
|
||||
sa1100_register_uart_fns(&neponset_port_fns);
|
||||
|
||||
/* Ensure that the memory bus request/grant signals are setup */
|
||||
sa1110_mb_disable();
|
||||
|
||||
|
@ -442,6 +387,8 @@ static int neponset_remove(struct platform_device *dev)
|
|||
platform_device_unregister(d->smc91x);
|
||||
|
||||
gpiod_remove_lookup_table(&neponset_pcmcia_table);
|
||||
gpiod_remove_lookup_table(&neponset_uart3_gpio_table);
|
||||
gpiod_remove_lookup_table(&neponset_uart1_gpio_table);
|
||||
|
||||
irq_set_chained_handler(irq, NULL);
|
||||
irq_free_descs(d->irq_base, NEP_IRQ_NR);
|
||||
|
|
|
@ -17,6 +17,7 @@
|
|||
#include <linux/of.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/psci.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/secure_cntvoff.h>
|
||||
#include "common.h"
|
||||
|
@ -60,9 +61,24 @@ static unsigned int __init get_extal_freq(void)
|
|||
|
||||
void __init rcar_gen2_timer_init(void)
|
||||
{
|
||||
bool need_update = true;
|
||||
void __iomem *base;
|
||||
u32 freq;
|
||||
|
||||
/*
|
||||
* If PSCI is available then most likely we are running on PSCI-enabled
|
||||
* U-Boot which, we assume, has already taken care of resetting CNTVOFF
|
||||
* and updating counter module before switching to non-secure mode
|
||||
* and we don't need to.
|
||||
*/
|
||||
#ifdef CONFIG_ARM_PSCI_FW
|
||||
if (psci_ops.cpu_on)
|
||||
need_update = false;
|
||||
#endif
|
||||
|
||||
if (need_update == false)
|
||||
goto skip_update;
|
||||
|
||||
secure_cntvoff_init();
|
||||
|
||||
if (of_machine_is_compatible("renesas,r8a7745") ||
|
||||
|
@ -102,6 +118,7 @@ void __init rcar_gen2_timer_init(void)
|
|||
|
||||
iounmap(base);
|
||||
|
||||
skip_update:
|
||||
of_clk_init(NULL);
|
||||
timer_probe();
|
||||
}
|
||||
|
|
|
@ -1,6 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
menuconfig ARCH_STM32
|
||||
bool "STMicroelectronics STM32 family" if ARM_SINGLE_ARMV7M || ARCH_MULTI_V7
|
||||
bool "STMicroelectronics STM32 family"
|
||||
depends on ARM_SINGLE_ARMV7M || ARCH_MULTI_V7
|
||||
select ARMV7M_SYSTICK if ARM_SINGLE_ARMV7M
|
||||
select HAVE_ARM_ARCH_TIMER if ARCH_MULTI_V7
|
||||
select ARM_GIC if ARCH_MULTI_V7
|
||||
|
|
|
@ -1,7 +1,4 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
plus_sec := $(call as-instr,.arch_extension sec,+sec)
|
||||
AFLAGS_smc.o := -Wa,-march=armv7-a$(plus_sec)
|
||||
|
||||
obj-y += setup.o smc.o
|
||||
obj-$(CONFIG_SMP) += platsmp.o
|
||||
obj-$(CONFIG_SUSPEND) += pm.o
|
||||
|
|
|
@ -1,6 +1,8 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#include <linux/linkage.h>
|
||||
|
||||
.arch armv7-a
|
||||
.arch_extension sec
|
||||
ENTRY(tango_smc)
|
||||
push {lr}
|
||||
mov ip, r1
|
||||
|
|
|
@ -16,8 +16,6 @@
|
|||
#include <linux/of_platform.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/amba/bus.h>
|
||||
#include <linux/amba/clcd.h>
|
||||
#include <linux/platform_data/video-clcd-versatile.h>
|
||||
#include <linux/amba/mmci.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
@ -34,14 +32,12 @@
|
|||
*/
|
||||
#define VERSATILE_SYS_PCICTL_OFFSET 0x44
|
||||
#define VERSATILE_SYS_MCI_OFFSET 0x48
|
||||
#define VERSATILE_SYS_CLCD_OFFSET 0x50
|
||||
|
||||
/*
|
||||
* VERSATILE peripheral addresses
|
||||
*/
|
||||
#define VERSATILE_MMCI0_BASE 0x10005000 /* MMC interface */
|
||||
#define VERSATILE_MMCI1_BASE 0x1000B000 /* MMC Interface */
|
||||
#define VERSATILE_CLCD_BASE 0x10120000 /* CLCD */
|
||||
#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */
|
||||
#define VERSATILE_IB2_BASE 0x24000000 /* IB2 module */
|
||||
#define VERSATILE_IB2_CTL_BASE (VERSATILE_IB2_BASE + 0x03000000)
|
||||
|
@ -83,158 +79,6 @@ static struct mmci_platform_data mmc1_plat_data = {
|
|||
.status = mmc_status,
|
||||
};
|
||||
|
||||
/*
|
||||
* CLCD support.
|
||||
*/
|
||||
#define SYS_CLCD_MODE_MASK (3 << 0)
|
||||
#define SYS_CLCD_MODE_888 (0 << 0)
|
||||
#define SYS_CLCD_MODE_5551 (1 << 0)
|
||||
#define SYS_CLCD_MODE_565_RLSB (2 << 0)
|
||||
#define SYS_CLCD_MODE_565_BLSB (3 << 0)
|
||||
#define SYS_CLCD_NLCDIOON (1 << 2)
|
||||
#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
|
||||
#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
|
||||
#define SYS_CLCD_ID_MASK (0x1f << 8)
|
||||
#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
|
||||
#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
|
||||
#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
|
||||
#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
|
||||
#define SYS_CLCD_ID_VGA (0x1f << 8)
|
||||
|
||||
static bool is_sanyo_2_5_lcd;
|
||||
|
||||
/*
|
||||
* Disable all display connectors on the interface module.
|
||||
*/
|
||||
static void versatile_clcd_disable(struct clcd_fb *fb)
|
||||
{
|
||||
void __iomem *sys_clcd = versatile_sys_base + VERSATILE_SYS_CLCD_OFFSET;
|
||||
u32 val;
|
||||
|
||||
val = readl(sys_clcd);
|
||||
val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
|
||||
writel(val, sys_clcd);
|
||||
|
||||
/*
|
||||
* If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
|
||||
*/
|
||||
if (of_machine_is_compatible("arm,versatile-ab") && is_sanyo_2_5_lcd) {
|
||||
unsigned long ctrl;
|
||||
|
||||
ctrl = readl(versatile_ib2_ctrl);
|
||||
ctrl &= ~0x01;
|
||||
writel(ctrl, versatile_ib2_ctrl);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable the relevant connector on the interface module.
|
||||
*/
|
||||
static void versatile_clcd_enable(struct clcd_fb *fb)
|
||||
{
|
||||
struct fb_var_screeninfo *var = &fb->fb.var;
|
||||
void __iomem *sys_clcd = versatile_sys_base + VERSATILE_SYS_CLCD_OFFSET;
|
||||
u32 val;
|
||||
|
||||
val = readl(sys_clcd);
|
||||
val &= ~SYS_CLCD_MODE_MASK;
|
||||
|
||||
switch (var->green.length) {
|
||||
case 5:
|
||||
val |= SYS_CLCD_MODE_5551;
|
||||
break;
|
||||
case 6:
|
||||
if (var->red.offset == 0)
|
||||
val |= SYS_CLCD_MODE_565_RLSB;
|
||||
else
|
||||
val |= SYS_CLCD_MODE_565_BLSB;
|
||||
break;
|
||||
case 8:
|
||||
val |= SYS_CLCD_MODE_888;
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set the MUX
|
||||
*/
|
||||
writel(val, sys_clcd);
|
||||
|
||||
/*
|
||||
* And now enable the PSUs
|
||||
*/
|
||||
val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
|
||||
writel(val, sys_clcd);
|
||||
|
||||
/*
|
||||
* If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
|
||||
*/
|
||||
if (of_machine_is_compatible("arm,versatile-ab") && is_sanyo_2_5_lcd) {
|
||||
unsigned long ctrl;
|
||||
|
||||
ctrl = readl(versatile_ib2_ctrl);
|
||||
ctrl |= 0x01;
|
||||
writel(ctrl, versatile_ib2_ctrl);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Detect which LCD panel is connected, and return the appropriate
|
||||
* clcd_panel structure. Note: we do not have any information on
|
||||
* the required timings for the 8.4in panel, so we presently assume
|
||||
* VGA timings.
|
||||
*/
|
||||
static int versatile_clcd_setup(struct clcd_fb *fb)
|
||||
{
|
||||
void __iomem *sys_clcd = versatile_sys_base + VERSATILE_SYS_CLCD_OFFSET;
|
||||
const char *panel_name;
|
||||
u32 val;
|
||||
|
||||
is_sanyo_2_5_lcd = false;
|
||||
|
||||
val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
|
||||
if (val == SYS_CLCD_ID_SANYO_3_8)
|
||||
panel_name = "Sanyo TM38QV67A02A";
|
||||
else if (val == SYS_CLCD_ID_SANYO_2_5) {
|
||||
panel_name = "Sanyo QVGA Portrait";
|
||||
is_sanyo_2_5_lcd = true;
|
||||
} else if (val == SYS_CLCD_ID_EPSON_2_2)
|
||||
panel_name = "Epson L2F50113T00";
|
||||
else if (val == SYS_CLCD_ID_VGA)
|
||||
panel_name = "VGA";
|
||||
else {
|
||||
printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
|
||||
val);
|
||||
panel_name = "VGA";
|
||||
}
|
||||
|
||||
fb->panel = versatile_clcd_get_panel(panel_name);
|
||||
if (!fb->panel)
|
||||
return -EINVAL;
|
||||
|
||||
return versatile_clcd_setup_dma(fb, SZ_1M);
|
||||
}
|
||||
|
||||
static void versatile_clcd_decode(struct clcd_fb *fb, struct clcd_regs *regs)
|
||||
{
|
||||
clcdfb_decode(fb, regs);
|
||||
|
||||
/* Always clear BGR for RGB565: we do the routing externally */
|
||||
if (fb->fb.var.green.length == 6)
|
||||
regs->cntl &= ~CNTL_BGR;
|
||||
}
|
||||
|
||||
static struct clcd_board clcd_plat_data = {
|
||||
.name = "Versatile",
|
||||
.caps = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888,
|
||||
.check = clcdfb_check,
|
||||
.decode = versatile_clcd_decode,
|
||||
.disable = versatile_clcd_disable,
|
||||
.enable = versatile_clcd_enable,
|
||||
.setup = versatile_clcd_setup,
|
||||
.mmap = versatile_clcd_mmap_dma,
|
||||
.remove = versatile_clcd_remove_dma,
|
||||
};
|
||||
|
||||
/*
|
||||
* Lookup table for attaching a specific name and platform_data pointer to
|
||||
* devices as they get created by of_platform_populate(). Ideally this table
|
||||
|
@ -244,7 +88,6 @@ static struct clcd_board clcd_plat_data = {
|
|||
struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = {
|
||||
OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", &mmc0_plat_data),
|
||||
OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", &mmc1_plat_data),
|
||||
OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data),
|
||||
{}
|
||||
};
|
||||
|
||||
|
@ -299,12 +142,12 @@ static void __init versatile_dt_pci_init(void)
|
|||
* driver had it so we will keep it.
|
||||
*/
|
||||
writel(1, versatile_sys_base + VERSATILE_SYS_PCICTL_OFFSET);
|
||||
return;
|
||||
goto out_put_node;
|
||||
}
|
||||
|
||||
newprop = kzalloc(sizeof(*newprop), GFP_KERNEL);
|
||||
if (!newprop)
|
||||
return;
|
||||
goto out_put_node;
|
||||
|
||||
newprop->name = kstrdup("status", GFP_KERNEL);
|
||||
newprop->value = kstrdup("disabled", GFP_KERNEL);
|
||||
|
@ -312,6 +155,9 @@ static void __init versatile_dt_pci_init(void)
|
|||
of_update_property(np, newprop);
|
||||
|
||||
pr_info("Not plugged into PCI backplane!\n");
|
||||
|
||||
out_put_node:
|
||||
of_node_put(np);
|
||||
}
|
||||
|
||||
static void __init versatile_dt_init(void)
|
||||
|
|
|
@ -66,8 +66,11 @@ config ARCH_BITMAIN
|
|||
|
||||
config ARCH_BRCMSTB
|
||||
bool "Broadcom Set-Top-Box SoCs"
|
||||
select ARCH_HAS_RESET_CONTROLLER
|
||||
select BCM7038_L1_IRQ
|
||||
select BRCMSTB_L2_IRQ
|
||||
select GENERIC_IRQ_CHIP
|
||||
select PINCTRL
|
||||
help
|
||||
This enables support for Broadcom's ARMv8 Set Top Box SoCs
|
||||
|
||||
|
|
|
@ -57,14 +57,16 @@ config ARCH_R7S72100
|
|||
bool "RZ/A1H (R7S72100)"
|
||||
select PM
|
||||
select PM_GENERIC_DOMAINS
|
||||
select SYS_SUPPORTS_SH_MTU2
|
||||
select RENESAS_OSTM
|
||||
select RENESAS_RZA1_IRQC
|
||||
select SYS_SUPPORTS_SH_MTU2
|
||||
|
||||
config ARCH_R7S9210
|
||||
bool "RZ/A2 (R7S9210)"
|
||||
select PM
|
||||
select PM_GENERIC_DOMAINS
|
||||
select RENESAS_OSTM
|
||||
select RENESAS_RZA1_IRQC
|
||||
|
||||
config ARCH_R8A73A4
|
||||
bool "R-Mobile APE6 (R8A73A40)"
|
||||
|
|
|
@ -178,6 +178,7 @@ static int am33xx_pm_suspend(suspend_state_t suspend_state)
|
|||
suspend_wfi_flags);
|
||||
|
||||
suspend_wfi_flags &= ~WFI_FLAG_RTC_ONLY;
|
||||
dev_info(pm33xx_dev, "Entering RTC Only mode with DDR in self-refresh\n");
|
||||
|
||||
if (!ret) {
|
||||
clk_restore_context();
|
||||
|
|
|
@ -497,6 +497,7 @@ config SERIAL_SA1100
|
|||
bool "SA1100 serial port support"
|
||||
depends on ARCH_SA1100
|
||||
select SERIAL_CORE
|
||||
select SERIAL_MCTRL_GPIO if GPIOLIB
|
||||
help
|
||||
If you have a machine based on a SA1100/SA1110 StrongARM(R) CPU you
|
||||
can enable its onboard serial port by enabling this option.
|
||||
|
|
|
@ -28,6 +28,8 @@
|
|||
#include <mach/hardware.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#include "serial_mctrl_gpio.h"
|
||||
|
||||
/* We've been assigned a range on the "Low-density serial ports" major */
|
||||
#define SERIAL_SA1100_MAJOR 204
|
||||
#define MINOR_START 5
|
||||
|
@ -77,6 +79,7 @@ struct sa1100_port {
|
|||
struct uart_port port;
|
||||
struct timer_list timer;
|
||||
unsigned int old_status;
|
||||
struct mctrl_gpios *gpios;
|
||||
};
|
||||
|
||||
/*
|
||||
|
@ -174,6 +177,8 @@ static void sa1100_enable_ms(struct uart_port *port)
|
|||
container_of(port, struct sa1100_port, port);
|
||||
|
||||
mod_timer(&sport->timer, jiffies);
|
||||
|
||||
mctrl_gpio_enable_ms(sport->gpios);
|
||||
}
|
||||
|
||||
static void
|
||||
|
@ -322,11 +327,21 @@ static unsigned int sa1100_tx_empty(struct uart_port *port)
|
|||
|
||||
static unsigned int sa1100_get_mctrl(struct uart_port *port)
|
||||
{
|
||||
return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
|
||||
struct sa1100_port *sport =
|
||||
container_of(port, struct sa1100_port, port);
|
||||
int ret = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
|
||||
|
||||
mctrl_gpio_get(sport->gpios, &ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void sa1100_set_mctrl(struct uart_port *port, unsigned int mctrl)
|
||||
{
|
||||
struct sa1100_port *sport =
|
||||
container_of(port, struct sa1100_port, port);
|
||||
|
||||
mctrl_gpio_set(sport->gpios, mctrl);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -842,6 +857,31 @@ static int sa1100_serial_resume(struct platform_device *dev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int sa1100_serial_add_one_port(struct sa1100_port *sport, struct platform_device *dev)
|
||||
{
|
||||
sport->port.dev = &dev->dev;
|
||||
|
||||
// mctrl_gpio_init() requires that the GPIO driver supports interrupts,
|
||||
// but we need to support GPIO drivers for hardware that has no such
|
||||
// interrupts. Use mctrl_gpio_init_noauto() instead.
|
||||
sport->gpios = mctrl_gpio_init_noauto(sport->port.dev, 0);
|
||||
if (IS_ERR(sport->gpios)) {
|
||||
int err = PTR_ERR(sport->gpios);
|
||||
|
||||
dev_err(sport->port.dev, "failed to get mctrl gpios: %d\n",
|
||||
err);
|
||||
|
||||
if (err == -EPROBE_DEFER)
|
||||
return err;
|
||||
|
||||
sport->gpios = NULL;
|
||||
}
|
||||
|
||||
platform_set_drvdata(dev, sport);
|
||||
|
||||
return uart_add_one_port(&sa1100_reg, &sport->port);
|
||||
}
|
||||
|
||||
static int sa1100_serial_probe(struct platform_device *dev)
|
||||
{
|
||||
struct resource *res = dev->resource;
|
||||
|
@ -856,9 +896,7 @@ static int sa1100_serial_probe(struct platform_device *dev)
|
|||
if (sa1100_ports[i].port.mapbase != res->start)
|
||||
continue;
|
||||
|
||||
sa1100_ports[i].port.dev = &dev->dev;
|
||||
uart_add_one_port(&sa1100_reg, &sa1100_ports[i].port);
|
||||
platform_set_drvdata(dev, &sa1100_ports[i]);
|
||||
sa1100_serial_add_one_port(&sa1100_ports[i], dev);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -1,28 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef PLAT_CLCD_H
|
||||
#define PLAT_CLCD_H
|
||||
|
||||
#ifdef CONFIG_PLAT_VERSATILE_CLCD
|
||||
struct clcd_panel *versatile_clcd_get_panel(const char *);
|
||||
int versatile_clcd_setup_dma(struct clcd_fb *, unsigned long);
|
||||
int versatile_clcd_mmap_dma(struct clcd_fb *, struct vm_area_struct *);
|
||||
void versatile_clcd_remove_dma(struct clcd_fb *);
|
||||
#else
|
||||
static inline struct clcd_panel *versatile_clcd_get_panel(const char *s)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
static inline int versatile_clcd_setup_dma(struct clcd_fb *fb, unsigned long framesize)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int versatile_clcd_mmap_dma(struct clcd_fb *fb, struct vm_area_struct *vm)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline void versatile_clcd_remove_dma(struct clcd_fb *fb)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
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