Merge branch 'drm-fixes-4.6' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
some misc radeon fixes. * 'drm-fixes-4.6' of git://people.freedesktop.org/~agd5f/linux: drm/amd/amdgpu: fix irq domain remove for tonga ih drm/radeon: use helper for mst connector dpms. drm/radeon/mst: port some MST setup code from DAL. drm/amdgpu: add invisible pin size statistic
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Коммит
25451c195a
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@ -2034,6 +2034,7 @@ struct amdgpu_device {
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/* tracking pinned memory */
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u64 vram_pin_size;
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u64 invisible_pin_size;
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u64 gart_pin_size;
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/* amdkfd interface */
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@ -384,7 +384,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
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vram_gtt.vram_size = adev->mc.real_vram_size;
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vram_gtt.vram_size -= adev->vram_pin_size;
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vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size;
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vram_gtt.vram_cpu_accessible_size -= adev->vram_pin_size;
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vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size);
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vram_gtt.gtt_size = adev->mc.gtt_size;
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vram_gtt.gtt_size -= adev->gart_pin_size;
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return copy_to_user(out, &vram_gtt,
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@ -424,9 +424,11 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
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bo->pin_count = 1;
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if (gpu_addr != NULL)
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*gpu_addr = amdgpu_bo_gpu_offset(bo);
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if (domain == AMDGPU_GEM_DOMAIN_VRAM)
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if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
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bo->adev->vram_pin_size += amdgpu_bo_size(bo);
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else
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if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
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bo->adev->invisible_pin_size += amdgpu_bo_size(bo);
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} else
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bo->adev->gart_pin_size += amdgpu_bo_size(bo);
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} else {
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dev_err(bo->adev->dev, "%p pin failed\n", bo);
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@ -456,9 +458,11 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo)
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}
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r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
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if (likely(r == 0)) {
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if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
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if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
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bo->adev->vram_pin_size -= amdgpu_bo_size(bo);
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else
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if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
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bo->adev->invisible_pin_size -= amdgpu_bo_size(bo);
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} else
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bo->adev->gart_pin_size -= amdgpu_bo_size(bo);
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} else {
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dev_err(bo->adev->dev, "%p validate failed for unpin\n", bo);
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@ -307,7 +307,7 @@ static int tonga_ih_sw_fini(void *handle)
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amdgpu_irq_fini(adev);
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amdgpu_ih_ring_fini(adev);
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amdgpu_irq_add_domain(adev);
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amdgpu_irq_remove_domain(adev);
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return 0;
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}
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@ -109,6 +109,8 @@
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#define NI_DP_MSE_SAT2 0x7398
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#define NI_DP_MSE_SAT_UPDATE 0x739c
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# define NI_DP_MSE_SAT_UPDATE_MASK 0x3
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# define NI_DP_MSE_16_MTP_KEEPOUT 0x100
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#define NI_DIG_BE_CNTL 0x7140
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# define NI_DIG_FE_SOURCE_SELECT(x) (((x) & 0x7f) << 8)
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@ -89,8 +89,16 @@ static int radeon_dp_mst_set_stream_attrib(struct radeon_encoder *primary,
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WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1);
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do {
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unsigned value1, value2;
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udelay(10);
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temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset);
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} while ((temp & 0x1) && retries++ < 10000);
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value1 = temp & NI_DP_MSE_SAT_UPDATE_MASK;
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value2 = temp & NI_DP_MSE_16_MTP_KEEPOUT;
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if (!value1 && !value2)
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break;
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} while (retries++ < 50);
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if (retries == 10000)
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DRM_ERROR("timed out waitin for SAT update %d\n", primary->offset);
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@ -150,7 +158,7 @@ static int radeon_dp_mst_update_stream_attribs(struct radeon_connector *mst_conn
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return 0;
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}
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static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, uint32_t x, uint32_t y)
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static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, s64 avg_time_slots_per_mtp)
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{
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struct drm_device *dev = mst->base.dev;
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struct radeon_device *rdev = dev->dev_private;
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@ -158,6 +166,8 @@ static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, uint32_t x, ui
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uint32_t val, temp;
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uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
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int retries = 0;
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uint32_t x = drm_fixp2int(avg_time_slots_per_mtp);
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uint32_t y = drm_fixp2int_ceil((avg_time_slots_per_mtp - x) << 26);
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val = NI_DP_MSE_RATE_X(x) | NI_DP_MSE_RATE_Y(y);
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@ -165,6 +175,7 @@ static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, uint32_t x, ui
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do {
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temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset);
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udelay(10);
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} while ((temp & 0x1) && (retries++ < 10000));
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if (retries >= 10000)
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@ -246,14 +257,8 @@ radeon_dp_mst_connector_destroy(struct drm_connector *connector)
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kfree(radeon_connector);
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}
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static int radeon_connector_dpms(struct drm_connector *connector, int mode)
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{
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DRM_DEBUG_KMS("\n");
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return 0;
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}
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static const struct drm_connector_funcs radeon_dp_mst_connector_funcs = {
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.dpms = radeon_connector_dpms,
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.dpms = drm_helper_connector_dpms,
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.detect = radeon_dp_mst_detect,
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.fill_modes = drm_helper_probe_single_connector_modes,
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.destroy = radeon_dp_mst_connector_destroy,
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@ -394,7 +399,7 @@ radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode)
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struct drm_crtc *crtc;
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struct radeon_crtc *radeon_crtc;
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int ret, slots;
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s64 fixed_pbn, fixed_pbn_per_slot, avg_time_slots_per_mtp;
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if (!ASIC_IS_DCE5(rdev)) {
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DRM_ERROR("got mst dpms on non-DCE5\n");
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return;
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@ -456,7 +461,11 @@ radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode)
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mst_enc->enc_active = true;
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radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
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radeon_dp_mst_set_vcp_size(radeon_encoder, slots, 0);
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fixed_pbn = drm_int2fixp(mst_enc->pbn);
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fixed_pbn_per_slot = drm_int2fixp(radeon_connector->mst_port->mst_mgr.pbn_div);
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avg_time_slots_per_mtp = drm_fixp_div(fixed_pbn, fixed_pbn_per_slot);
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radeon_dp_mst_set_vcp_size(radeon_encoder, avg_time_slots_per_mtp);
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atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0,
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mst_enc->fe);
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