perf/cores fixes and improvements:
Tools: top: - Fix 'struct comm_str' removal crash race, detected with refcount_t debugging (Jiri Olsa) - Use last_match threads cache only in single threaded mode, fixing a crash (Jiri Olsa) record: - Synthesize GROUP_DESC feature in pipe mode fixing display of event groups (Jiri Olsa) stat: - Get rid of extra clock display function (Jiri Olsa) perf script: - Show correct offsets for DWARF-based unwinding (Sandipan Das) test: - Check that complex event name is parsed correctly (Alexey Budankov) - Fix subtest number when showing results (Thomas Richter) Arch specific: arm64: - Generate syscall table from the kernel sources (asm/unistd.h) like other arches do, speeding up the support for new system calls in tools such as 'perf trace' (Kim Phillips) arm: - Bail out immediatelly on CoreSight hardware tracing instruction sample failure (Leo Yan) PowerPC: - Fix record+probe_libc_inet_pton.sh 'perf test' entry (Sandipan Das) - Callchain IP filtering fixes (Sandipan Das) S/390: - Add support for detailed S/390 PMU event description in 'perf list' (Thomas Richter) - Add transaction flag (-T) support in 'perf stat' for S/390 (Thomas Richter) - Fix 'perf kvm' S/390 subcommands (Thomas Richter) Infrastructure: hists: - Clarify callchain disabling when available (Arnaldo Carvalho de Melo) evsel: - Use perf_evsel__match instead of open coded equivalent (Jiri Olsa) Documentation: - Add missing documentation for 'perf list' --desc and --debug options (Sangwon Hong) Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com> -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEELb9bqkb7Te0zijNb1lAW81NSqkAFAltYrXUACgkQ1lAW81NS qkD8jQ//STGb87h4aFaXSHucRFfSqBTj1/6nOlk9PafJ1wLmOZhWVccUJzvPENJq wRCffnQi0yMaFJBq4omfVf0zlnCvg78jb+4oYhExy66x+6edvYPg6UF1O68EhjZC dbe7ejkq6uiG7kpJpwaZQNBa4UiJ1DtlPmKUukpJnZD45JWWU6l0b5j0xKs/pybI phApii5iRB6KEWL/NvqdQJBJ796dJJKKRHMLCjU7GQfkmpMT++/qqecBwlrQdhos BLsNYoqhktUlm3GYJEWmzn/rJNNiQPiJcF5cy+I8/+a7v0dQgqIGrkq9fqoW060f GlIGs75ZT5GnWqv6JpmYWoUUYw0qeLvjPgh2vTwfWcidO1jWXF6BV9vo20LNukmB rQgMa4N/ypPk0aGPb1n/VraUPrGGdSC/p4XheJ3SiwEDwb2xbhRUCJJIA/X/Xn9G COJrGeypKbHVq2r4r81cp0yEtO6qrkjfoDlRXamCpiNVtU0nPM1A1alutNAeDk0s 2rQnqidku8DxtKaTBJIuA+YZAiM1bSPFEbY2p+NR/op4tAxAXAtkJgUi1x39J8uW 9TmbYkHRBBk59S+nOJQJXHz0KBecuN4HS9KZTT2Qw9sgGu+lLPtg7+rLUbwV87d+ 5o41ZxAEV/000n0lU17chDvbQxCYl5jxmNRfHTiRc4bWI+ltM1o= =+kyy -----END PGP SIGNATURE----- Merge tag 'perf-core-for-mingo-4.19-20180725' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/core Pull perf/cores fixes and improvements from Arnaldo Carvalho de Melo: Tools: top: - Fix 'struct comm_str' removal crash race, detected with refcount_t debugging (Jiri Olsa) - Use last_match threads cache only in single threaded mode, fixing a crash (Jiri Olsa) record: - Synthesize GROUP_DESC feature in pipe mode fixing display of event groups (Jiri Olsa) stat: - Get rid of extra clock display function (Jiri Olsa) perf script: - Show correct offsets for DWARF-based unwinding (Sandipan Das) test: - Check that complex event name is parsed correctly (Alexey Budankov) - Fix subtest number when showing results (Thomas Richter) Arch specific: arm64: - Generate syscall table from the kernel sources (asm/unistd.h) like other arches do, speeding up the support for new system calls in tools such as 'perf trace' (Kim Phillips) arm: - Bail out immediatelly on CoreSight hardware tracing instruction sample failure (Leo Yan) PowerPC: - Fix record+probe_libc_inet_pton.sh 'perf test' entry (Sandipan Das) - Callchain IP filtering fixes (Sandipan Das) S/390: - Add support for detailed S/390 PMU event description in 'perf list' (Thomas Richter) - Add transaction flag (-T) support in 'perf stat' for S/390 (Thomas Richter) - Fix 'perf kvm' S/390 subcommands (Thomas Richter) Infrastructure: hists: - Clarify callchain disabling when available (Arnaldo Carvalho de Melo) evsel: - Use perf_evsel__match instead of open coded equivalent (Jiri Olsa) Documentation: - Add missing documentation for 'perf list' --desc and --debug options (Sangwon Hong) Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com> Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Ingo Molnar
Коммит
25a00ac7dc
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@ -0,0 +1,20 @@
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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
|
||||
* Copyright (C) 2012 ARM Ltd.
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*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#define __ARCH_WANT_RENAMEAT
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||||
|
||||
#include <asm-generic/unistd.h>
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|
|
@ -0,0 +1,783 @@
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|||
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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||||
#include <asm/bitsperlong.h>
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|
||||
/*
|
||||
* This file contains the system call numbers, based on the
|
||||
* layout of the x86-64 architecture, which embeds the
|
||||
* pointer to the syscall in the table.
|
||||
*
|
||||
* As a basic principle, no duplication of functionality
|
||||
* should be added, e.g. we don't use lseek when llseek
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||||
* is present. New architectures should use this file
|
||||
* and implement the less feature-full calls in user space.
|
||||
*/
|
||||
|
||||
#ifndef __SYSCALL
|
||||
#define __SYSCALL(x, y)
|
||||
#endif
|
||||
|
||||
#if __BITS_PER_LONG == 32 || defined(__SYSCALL_COMPAT)
|
||||
#define __SC_3264(_nr, _32, _64) __SYSCALL(_nr, _32)
|
||||
#else
|
||||
#define __SC_3264(_nr, _32, _64) __SYSCALL(_nr, _64)
|
||||
#endif
|
||||
|
||||
#ifdef __SYSCALL_COMPAT
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||||
#define __SC_COMP(_nr, _sys, _comp) __SYSCALL(_nr, _comp)
|
||||
#define __SC_COMP_3264(_nr, _32, _64, _comp) __SYSCALL(_nr, _comp)
|
||||
#else
|
||||
#define __SC_COMP(_nr, _sys, _comp) __SYSCALL(_nr, _sys)
|
||||
#define __SC_COMP_3264(_nr, _32, _64, _comp) __SC_3264(_nr, _32, _64)
|
||||
#endif
|
||||
|
||||
#define __NR_io_setup 0
|
||||
__SC_COMP(__NR_io_setup, sys_io_setup, compat_sys_io_setup)
|
||||
#define __NR_io_destroy 1
|
||||
__SYSCALL(__NR_io_destroy, sys_io_destroy)
|
||||
#define __NR_io_submit 2
|
||||
__SC_COMP(__NR_io_submit, sys_io_submit, compat_sys_io_submit)
|
||||
#define __NR_io_cancel 3
|
||||
__SYSCALL(__NR_io_cancel, sys_io_cancel)
|
||||
#define __NR_io_getevents 4
|
||||
__SC_COMP(__NR_io_getevents, sys_io_getevents, compat_sys_io_getevents)
|
||||
|
||||
/* fs/xattr.c */
|
||||
#define __NR_setxattr 5
|
||||
__SYSCALL(__NR_setxattr, sys_setxattr)
|
||||
#define __NR_lsetxattr 6
|
||||
__SYSCALL(__NR_lsetxattr, sys_lsetxattr)
|
||||
#define __NR_fsetxattr 7
|
||||
__SYSCALL(__NR_fsetxattr, sys_fsetxattr)
|
||||
#define __NR_getxattr 8
|
||||
__SYSCALL(__NR_getxattr, sys_getxattr)
|
||||
#define __NR_lgetxattr 9
|
||||
__SYSCALL(__NR_lgetxattr, sys_lgetxattr)
|
||||
#define __NR_fgetxattr 10
|
||||
__SYSCALL(__NR_fgetxattr, sys_fgetxattr)
|
||||
#define __NR_listxattr 11
|
||||
__SYSCALL(__NR_listxattr, sys_listxattr)
|
||||
#define __NR_llistxattr 12
|
||||
__SYSCALL(__NR_llistxattr, sys_llistxattr)
|
||||
#define __NR_flistxattr 13
|
||||
__SYSCALL(__NR_flistxattr, sys_flistxattr)
|
||||
#define __NR_removexattr 14
|
||||
__SYSCALL(__NR_removexattr, sys_removexattr)
|
||||
#define __NR_lremovexattr 15
|
||||
__SYSCALL(__NR_lremovexattr, sys_lremovexattr)
|
||||
#define __NR_fremovexattr 16
|
||||
__SYSCALL(__NR_fremovexattr, sys_fremovexattr)
|
||||
|
||||
/* fs/dcache.c */
|
||||
#define __NR_getcwd 17
|
||||
__SYSCALL(__NR_getcwd, sys_getcwd)
|
||||
|
||||
/* fs/cookies.c */
|
||||
#define __NR_lookup_dcookie 18
|
||||
__SC_COMP(__NR_lookup_dcookie, sys_lookup_dcookie, compat_sys_lookup_dcookie)
|
||||
|
||||
/* fs/eventfd.c */
|
||||
#define __NR_eventfd2 19
|
||||
__SYSCALL(__NR_eventfd2, sys_eventfd2)
|
||||
|
||||
/* fs/eventpoll.c */
|
||||
#define __NR_epoll_create1 20
|
||||
__SYSCALL(__NR_epoll_create1, sys_epoll_create1)
|
||||
#define __NR_epoll_ctl 21
|
||||
__SYSCALL(__NR_epoll_ctl, sys_epoll_ctl)
|
||||
#define __NR_epoll_pwait 22
|
||||
__SC_COMP(__NR_epoll_pwait, sys_epoll_pwait, compat_sys_epoll_pwait)
|
||||
|
||||
/* fs/fcntl.c */
|
||||
#define __NR_dup 23
|
||||
__SYSCALL(__NR_dup, sys_dup)
|
||||
#define __NR_dup3 24
|
||||
__SYSCALL(__NR_dup3, sys_dup3)
|
||||
#define __NR3264_fcntl 25
|
||||
__SC_COMP_3264(__NR3264_fcntl, sys_fcntl64, sys_fcntl, compat_sys_fcntl64)
|
||||
|
||||
/* fs/inotify_user.c */
|
||||
#define __NR_inotify_init1 26
|
||||
__SYSCALL(__NR_inotify_init1, sys_inotify_init1)
|
||||
#define __NR_inotify_add_watch 27
|
||||
__SYSCALL(__NR_inotify_add_watch, sys_inotify_add_watch)
|
||||
#define __NR_inotify_rm_watch 28
|
||||
__SYSCALL(__NR_inotify_rm_watch, sys_inotify_rm_watch)
|
||||
|
||||
/* fs/ioctl.c */
|
||||
#define __NR_ioctl 29
|
||||
__SC_COMP(__NR_ioctl, sys_ioctl, compat_sys_ioctl)
|
||||
|
||||
/* fs/ioprio.c */
|
||||
#define __NR_ioprio_set 30
|
||||
__SYSCALL(__NR_ioprio_set, sys_ioprio_set)
|
||||
#define __NR_ioprio_get 31
|
||||
__SYSCALL(__NR_ioprio_get, sys_ioprio_get)
|
||||
|
||||
/* fs/locks.c */
|
||||
#define __NR_flock 32
|
||||
__SYSCALL(__NR_flock, sys_flock)
|
||||
|
||||
/* fs/namei.c */
|
||||
#define __NR_mknodat 33
|
||||
__SYSCALL(__NR_mknodat, sys_mknodat)
|
||||
#define __NR_mkdirat 34
|
||||
__SYSCALL(__NR_mkdirat, sys_mkdirat)
|
||||
#define __NR_unlinkat 35
|
||||
__SYSCALL(__NR_unlinkat, sys_unlinkat)
|
||||
#define __NR_symlinkat 36
|
||||
__SYSCALL(__NR_symlinkat, sys_symlinkat)
|
||||
#define __NR_linkat 37
|
||||
__SYSCALL(__NR_linkat, sys_linkat)
|
||||
#ifdef __ARCH_WANT_RENAMEAT
|
||||
/* renameat is superseded with flags by renameat2 */
|
||||
#define __NR_renameat 38
|
||||
__SYSCALL(__NR_renameat, sys_renameat)
|
||||
#endif /* __ARCH_WANT_RENAMEAT */
|
||||
|
||||
/* fs/namespace.c */
|
||||
#define __NR_umount2 39
|
||||
__SYSCALL(__NR_umount2, sys_umount)
|
||||
#define __NR_mount 40
|
||||
__SC_COMP(__NR_mount, sys_mount, compat_sys_mount)
|
||||
#define __NR_pivot_root 41
|
||||
__SYSCALL(__NR_pivot_root, sys_pivot_root)
|
||||
|
||||
/* fs/nfsctl.c */
|
||||
#define __NR_nfsservctl 42
|
||||
__SYSCALL(__NR_nfsservctl, sys_ni_syscall)
|
||||
|
||||
/* fs/open.c */
|
||||
#define __NR3264_statfs 43
|
||||
__SC_COMP_3264(__NR3264_statfs, sys_statfs64, sys_statfs, \
|
||||
compat_sys_statfs64)
|
||||
#define __NR3264_fstatfs 44
|
||||
__SC_COMP_3264(__NR3264_fstatfs, sys_fstatfs64, sys_fstatfs, \
|
||||
compat_sys_fstatfs64)
|
||||
#define __NR3264_truncate 45
|
||||
__SC_COMP_3264(__NR3264_truncate, sys_truncate64, sys_truncate, \
|
||||
compat_sys_truncate64)
|
||||
#define __NR3264_ftruncate 46
|
||||
__SC_COMP_3264(__NR3264_ftruncate, sys_ftruncate64, sys_ftruncate, \
|
||||
compat_sys_ftruncate64)
|
||||
|
||||
#define __NR_fallocate 47
|
||||
__SC_COMP(__NR_fallocate, sys_fallocate, compat_sys_fallocate)
|
||||
#define __NR_faccessat 48
|
||||
__SYSCALL(__NR_faccessat, sys_faccessat)
|
||||
#define __NR_chdir 49
|
||||
__SYSCALL(__NR_chdir, sys_chdir)
|
||||
#define __NR_fchdir 50
|
||||
__SYSCALL(__NR_fchdir, sys_fchdir)
|
||||
#define __NR_chroot 51
|
||||
__SYSCALL(__NR_chroot, sys_chroot)
|
||||
#define __NR_fchmod 52
|
||||
__SYSCALL(__NR_fchmod, sys_fchmod)
|
||||
#define __NR_fchmodat 53
|
||||
__SYSCALL(__NR_fchmodat, sys_fchmodat)
|
||||
#define __NR_fchownat 54
|
||||
__SYSCALL(__NR_fchownat, sys_fchownat)
|
||||
#define __NR_fchown 55
|
||||
__SYSCALL(__NR_fchown, sys_fchown)
|
||||
#define __NR_openat 56
|
||||
__SC_COMP(__NR_openat, sys_openat, compat_sys_openat)
|
||||
#define __NR_close 57
|
||||
__SYSCALL(__NR_close, sys_close)
|
||||
#define __NR_vhangup 58
|
||||
__SYSCALL(__NR_vhangup, sys_vhangup)
|
||||
|
||||
/* fs/pipe.c */
|
||||
#define __NR_pipe2 59
|
||||
__SYSCALL(__NR_pipe2, sys_pipe2)
|
||||
|
||||
/* fs/quota.c */
|
||||
#define __NR_quotactl 60
|
||||
__SYSCALL(__NR_quotactl, sys_quotactl)
|
||||
|
||||
/* fs/readdir.c */
|
||||
#define __NR_getdents64 61
|
||||
__SYSCALL(__NR_getdents64, sys_getdents64)
|
||||
|
||||
/* fs/read_write.c */
|
||||
#define __NR3264_lseek 62
|
||||
__SC_3264(__NR3264_lseek, sys_llseek, sys_lseek)
|
||||
#define __NR_read 63
|
||||
__SYSCALL(__NR_read, sys_read)
|
||||
#define __NR_write 64
|
||||
__SYSCALL(__NR_write, sys_write)
|
||||
#define __NR_readv 65
|
||||
__SC_COMP(__NR_readv, sys_readv, compat_sys_readv)
|
||||
#define __NR_writev 66
|
||||
__SC_COMP(__NR_writev, sys_writev, compat_sys_writev)
|
||||
#define __NR_pread64 67
|
||||
__SC_COMP(__NR_pread64, sys_pread64, compat_sys_pread64)
|
||||
#define __NR_pwrite64 68
|
||||
__SC_COMP(__NR_pwrite64, sys_pwrite64, compat_sys_pwrite64)
|
||||
#define __NR_preadv 69
|
||||
__SC_COMP(__NR_preadv, sys_preadv, compat_sys_preadv)
|
||||
#define __NR_pwritev 70
|
||||
__SC_COMP(__NR_pwritev, sys_pwritev, compat_sys_pwritev)
|
||||
|
||||
/* fs/sendfile.c */
|
||||
#define __NR3264_sendfile 71
|
||||
__SYSCALL(__NR3264_sendfile, sys_sendfile64)
|
||||
|
||||
/* fs/select.c */
|
||||
#define __NR_pselect6 72
|
||||
__SC_COMP(__NR_pselect6, sys_pselect6, compat_sys_pselect6)
|
||||
#define __NR_ppoll 73
|
||||
__SC_COMP(__NR_ppoll, sys_ppoll, compat_sys_ppoll)
|
||||
|
||||
/* fs/signalfd.c */
|
||||
#define __NR_signalfd4 74
|
||||
__SC_COMP(__NR_signalfd4, sys_signalfd4, compat_sys_signalfd4)
|
||||
|
||||
/* fs/splice.c */
|
||||
#define __NR_vmsplice 75
|
||||
__SC_COMP(__NR_vmsplice, sys_vmsplice, compat_sys_vmsplice)
|
||||
#define __NR_splice 76
|
||||
__SYSCALL(__NR_splice, sys_splice)
|
||||
#define __NR_tee 77
|
||||
__SYSCALL(__NR_tee, sys_tee)
|
||||
|
||||
/* fs/stat.c */
|
||||
#define __NR_readlinkat 78
|
||||
__SYSCALL(__NR_readlinkat, sys_readlinkat)
|
||||
#define __NR3264_fstatat 79
|
||||
__SC_3264(__NR3264_fstatat, sys_fstatat64, sys_newfstatat)
|
||||
#define __NR3264_fstat 80
|
||||
__SC_3264(__NR3264_fstat, sys_fstat64, sys_newfstat)
|
||||
|
||||
/* fs/sync.c */
|
||||
#define __NR_sync 81
|
||||
__SYSCALL(__NR_sync, sys_sync)
|
||||
#define __NR_fsync 82
|
||||
__SYSCALL(__NR_fsync, sys_fsync)
|
||||
#define __NR_fdatasync 83
|
||||
__SYSCALL(__NR_fdatasync, sys_fdatasync)
|
||||
#ifdef __ARCH_WANT_SYNC_FILE_RANGE2
|
||||
#define __NR_sync_file_range2 84
|
||||
__SC_COMP(__NR_sync_file_range2, sys_sync_file_range2, \
|
||||
compat_sys_sync_file_range2)
|
||||
#else
|
||||
#define __NR_sync_file_range 84
|
||||
__SC_COMP(__NR_sync_file_range, sys_sync_file_range, \
|
||||
compat_sys_sync_file_range)
|
||||
#endif
|
||||
|
||||
/* fs/timerfd.c */
|
||||
#define __NR_timerfd_create 85
|
||||
__SYSCALL(__NR_timerfd_create, sys_timerfd_create)
|
||||
#define __NR_timerfd_settime 86
|
||||
__SC_COMP(__NR_timerfd_settime, sys_timerfd_settime, \
|
||||
compat_sys_timerfd_settime)
|
||||
#define __NR_timerfd_gettime 87
|
||||
__SC_COMP(__NR_timerfd_gettime, sys_timerfd_gettime, \
|
||||
compat_sys_timerfd_gettime)
|
||||
|
||||
/* fs/utimes.c */
|
||||
#define __NR_utimensat 88
|
||||
__SC_COMP(__NR_utimensat, sys_utimensat, compat_sys_utimensat)
|
||||
|
||||
/* kernel/acct.c */
|
||||
#define __NR_acct 89
|
||||
__SYSCALL(__NR_acct, sys_acct)
|
||||
|
||||
/* kernel/capability.c */
|
||||
#define __NR_capget 90
|
||||
__SYSCALL(__NR_capget, sys_capget)
|
||||
#define __NR_capset 91
|
||||
__SYSCALL(__NR_capset, sys_capset)
|
||||
|
||||
/* kernel/exec_domain.c */
|
||||
#define __NR_personality 92
|
||||
__SYSCALL(__NR_personality, sys_personality)
|
||||
|
||||
/* kernel/exit.c */
|
||||
#define __NR_exit 93
|
||||
__SYSCALL(__NR_exit, sys_exit)
|
||||
#define __NR_exit_group 94
|
||||
__SYSCALL(__NR_exit_group, sys_exit_group)
|
||||
#define __NR_waitid 95
|
||||
__SC_COMP(__NR_waitid, sys_waitid, compat_sys_waitid)
|
||||
|
||||
/* kernel/fork.c */
|
||||
#define __NR_set_tid_address 96
|
||||
__SYSCALL(__NR_set_tid_address, sys_set_tid_address)
|
||||
#define __NR_unshare 97
|
||||
__SYSCALL(__NR_unshare, sys_unshare)
|
||||
|
||||
/* kernel/futex.c */
|
||||
#define __NR_futex 98
|
||||
__SC_COMP(__NR_futex, sys_futex, compat_sys_futex)
|
||||
#define __NR_set_robust_list 99
|
||||
__SC_COMP(__NR_set_robust_list, sys_set_robust_list, \
|
||||
compat_sys_set_robust_list)
|
||||
#define __NR_get_robust_list 100
|
||||
__SC_COMP(__NR_get_robust_list, sys_get_robust_list, \
|
||||
compat_sys_get_robust_list)
|
||||
|
||||
/* kernel/hrtimer.c */
|
||||
#define __NR_nanosleep 101
|
||||
__SC_COMP(__NR_nanosleep, sys_nanosleep, compat_sys_nanosleep)
|
||||
|
||||
/* kernel/itimer.c */
|
||||
#define __NR_getitimer 102
|
||||
__SC_COMP(__NR_getitimer, sys_getitimer, compat_sys_getitimer)
|
||||
#define __NR_setitimer 103
|
||||
__SC_COMP(__NR_setitimer, sys_setitimer, compat_sys_setitimer)
|
||||
|
||||
/* kernel/kexec.c */
|
||||
#define __NR_kexec_load 104
|
||||
__SC_COMP(__NR_kexec_load, sys_kexec_load, compat_sys_kexec_load)
|
||||
|
||||
/* kernel/module.c */
|
||||
#define __NR_init_module 105
|
||||
__SYSCALL(__NR_init_module, sys_init_module)
|
||||
#define __NR_delete_module 106
|
||||
__SYSCALL(__NR_delete_module, sys_delete_module)
|
||||
|
||||
/* kernel/posix-timers.c */
|
||||
#define __NR_timer_create 107
|
||||
__SC_COMP(__NR_timer_create, sys_timer_create, compat_sys_timer_create)
|
||||
#define __NR_timer_gettime 108
|
||||
__SC_COMP(__NR_timer_gettime, sys_timer_gettime, compat_sys_timer_gettime)
|
||||
#define __NR_timer_getoverrun 109
|
||||
__SYSCALL(__NR_timer_getoverrun, sys_timer_getoverrun)
|
||||
#define __NR_timer_settime 110
|
||||
__SC_COMP(__NR_timer_settime, sys_timer_settime, compat_sys_timer_settime)
|
||||
#define __NR_timer_delete 111
|
||||
__SYSCALL(__NR_timer_delete, sys_timer_delete)
|
||||
#define __NR_clock_settime 112
|
||||
__SC_COMP(__NR_clock_settime, sys_clock_settime, compat_sys_clock_settime)
|
||||
#define __NR_clock_gettime 113
|
||||
__SC_COMP(__NR_clock_gettime, sys_clock_gettime, compat_sys_clock_gettime)
|
||||
#define __NR_clock_getres 114
|
||||
__SC_COMP(__NR_clock_getres, sys_clock_getres, compat_sys_clock_getres)
|
||||
#define __NR_clock_nanosleep 115
|
||||
__SC_COMP(__NR_clock_nanosleep, sys_clock_nanosleep, \
|
||||
compat_sys_clock_nanosleep)
|
||||
|
||||
/* kernel/printk.c */
|
||||
#define __NR_syslog 116
|
||||
__SYSCALL(__NR_syslog, sys_syslog)
|
||||
|
||||
/* kernel/ptrace.c */
|
||||
#define __NR_ptrace 117
|
||||
__SYSCALL(__NR_ptrace, sys_ptrace)
|
||||
|
||||
/* kernel/sched/core.c */
|
||||
#define __NR_sched_setparam 118
|
||||
__SYSCALL(__NR_sched_setparam, sys_sched_setparam)
|
||||
#define __NR_sched_setscheduler 119
|
||||
__SYSCALL(__NR_sched_setscheduler, sys_sched_setscheduler)
|
||||
#define __NR_sched_getscheduler 120
|
||||
__SYSCALL(__NR_sched_getscheduler, sys_sched_getscheduler)
|
||||
#define __NR_sched_getparam 121
|
||||
__SYSCALL(__NR_sched_getparam, sys_sched_getparam)
|
||||
#define __NR_sched_setaffinity 122
|
||||
__SC_COMP(__NR_sched_setaffinity, sys_sched_setaffinity, \
|
||||
compat_sys_sched_setaffinity)
|
||||
#define __NR_sched_getaffinity 123
|
||||
__SC_COMP(__NR_sched_getaffinity, sys_sched_getaffinity, \
|
||||
compat_sys_sched_getaffinity)
|
||||
#define __NR_sched_yield 124
|
||||
__SYSCALL(__NR_sched_yield, sys_sched_yield)
|
||||
#define __NR_sched_get_priority_max 125
|
||||
__SYSCALL(__NR_sched_get_priority_max, sys_sched_get_priority_max)
|
||||
#define __NR_sched_get_priority_min 126
|
||||
__SYSCALL(__NR_sched_get_priority_min, sys_sched_get_priority_min)
|
||||
#define __NR_sched_rr_get_interval 127
|
||||
__SC_COMP(__NR_sched_rr_get_interval, sys_sched_rr_get_interval, \
|
||||
compat_sys_sched_rr_get_interval)
|
||||
|
||||
/* kernel/signal.c */
|
||||
#define __NR_restart_syscall 128
|
||||
__SYSCALL(__NR_restart_syscall, sys_restart_syscall)
|
||||
#define __NR_kill 129
|
||||
__SYSCALL(__NR_kill, sys_kill)
|
||||
#define __NR_tkill 130
|
||||
__SYSCALL(__NR_tkill, sys_tkill)
|
||||
#define __NR_tgkill 131
|
||||
__SYSCALL(__NR_tgkill, sys_tgkill)
|
||||
#define __NR_sigaltstack 132
|
||||
__SC_COMP(__NR_sigaltstack, sys_sigaltstack, compat_sys_sigaltstack)
|
||||
#define __NR_rt_sigsuspend 133
|
||||
__SC_COMP(__NR_rt_sigsuspend, sys_rt_sigsuspend, compat_sys_rt_sigsuspend)
|
||||
#define __NR_rt_sigaction 134
|
||||
__SC_COMP(__NR_rt_sigaction, sys_rt_sigaction, compat_sys_rt_sigaction)
|
||||
#define __NR_rt_sigprocmask 135
|
||||
__SC_COMP(__NR_rt_sigprocmask, sys_rt_sigprocmask, compat_sys_rt_sigprocmask)
|
||||
#define __NR_rt_sigpending 136
|
||||
__SC_COMP(__NR_rt_sigpending, sys_rt_sigpending, compat_sys_rt_sigpending)
|
||||
#define __NR_rt_sigtimedwait 137
|
||||
__SC_COMP(__NR_rt_sigtimedwait, sys_rt_sigtimedwait, \
|
||||
compat_sys_rt_sigtimedwait)
|
||||
#define __NR_rt_sigqueueinfo 138
|
||||
__SC_COMP(__NR_rt_sigqueueinfo, sys_rt_sigqueueinfo, \
|
||||
compat_sys_rt_sigqueueinfo)
|
||||
#define __NR_rt_sigreturn 139
|
||||
__SC_COMP(__NR_rt_sigreturn, sys_rt_sigreturn, compat_sys_rt_sigreturn)
|
||||
|
||||
/* kernel/sys.c */
|
||||
#define __NR_setpriority 140
|
||||
__SYSCALL(__NR_setpriority, sys_setpriority)
|
||||
#define __NR_getpriority 141
|
||||
__SYSCALL(__NR_getpriority, sys_getpriority)
|
||||
#define __NR_reboot 142
|
||||
__SYSCALL(__NR_reboot, sys_reboot)
|
||||
#define __NR_setregid 143
|
||||
__SYSCALL(__NR_setregid, sys_setregid)
|
||||
#define __NR_setgid 144
|
||||
__SYSCALL(__NR_setgid, sys_setgid)
|
||||
#define __NR_setreuid 145
|
||||
__SYSCALL(__NR_setreuid, sys_setreuid)
|
||||
#define __NR_setuid 146
|
||||
__SYSCALL(__NR_setuid, sys_setuid)
|
||||
#define __NR_setresuid 147
|
||||
__SYSCALL(__NR_setresuid, sys_setresuid)
|
||||
#define __NR_getresuid 148
|
||||
__SYSCALL(__NR_getresuid, sys_getresuid)
|
||||
#define __NR_setresgid 149
|
||||
__SYSCALL(__NR_setresgid, sys_setresgid)
|
||||
#define __NR_getresgid 150
|
||||
__SYSCALL(__NR_getresgid, sys_getresgid)
|
||||
#define __NR_setfsuid 151
|
||||
__SYSCALL(__NR_setfsuid, sys_setfsuid)
|
||||
#define __NR_setfsgid 152
|
||||
__SYSCALL(__NR_setfsgid, sys_setfsgid)
|
||||
#define __NR_times 153
|
||||
__SC_COMP(__NR_times, sys_times, compat_sys_times)
|
||||
#define __NR_setpgid 154
|
||||
__SYSCALL(__NR_setpgid, sys_setpgid)
|
||||
#define __NR_getpgid 155
|
||||
__SYSCALL(__NR_getpgid, sys_getpgid)
|
||||
#define __NR_getsid 156
|
||||
__SYSCALL(__NR_getsid, sys_getsid)
|
||||
#define __NR_setsid 157
|
||||
__SYSCALL(__NR_setsid, sys_setsid)
|
||||
#define __NR_getgroups 158
|
||||
__SYSCALL(__NR_getgroups, sys_getgroups)
|
||||
#define __NR_setgroups 159
|
||||
__SYSCALL(__NR_setgroups, sys_setgroups)
|
||||
#define __NR_uname 160
|
||||
__SYSCALL(__NR_uname, sys_newuname)
|
||||
#define __NR_sethostname 161
|
||||
__SYSCALL(__NR_sethostname, sys_sethostname)
|
||||
#define __NR_setdomainname 162
|
||||
__SYSCALL(__NR_setdomainname, sys_setdomainname)
|
||||
#define __NR_getrlimit 163
|
||||
__SC_COMP(__NR_getrlimit, sys_getrlimit, compat_sys_getrlimit)
|
||||
#define __NR_setrlimit 164
|
||||
__SC_COMP(__NR_setrlimit, sys_setrlimit, compat_sys_setrlimit)
|
||||
#define __NR_getrusage 165
|
||||
__SC_COMP(__NR_getrusage, sys_getrusage, compat_sys_getrusage)
|
||||
#define __NR_umask 166
|
||||
__SYSCALL(__NR_umask, sys_umask)
|
||||
#define __NR_prctl 167
|
||||
__SYSCALL(__NR_prctl, sys_prctl)
|
||||
#define __NR_getcpu 168
|
||||
__SYSCALL(__NR_getcpu, sys_getcpu)
|
||||
|
||||
/* kernel/time.c */
|
||||
#define __NR_gettimeofday 169
|
||||
__SC_COMP(__NR_gettimeofday, sys_gettimeofday, compat_sys_gettimeofday)
|
||||
#define __NR_settimeofday 170
|
||||
__SC_COMP(__NR_settimeofday, sys_settimeofday, compat_sys_settimeofday)
|
||||
#define __NR_adjtimex 171
|
||||
__SC_COMP(__NR_adjtimex, sys_adjtimex, compat_sys_adjtimex)
|
||||
|
||||
/* kernel/timer.c */
|
||||
#define __NR_getpid 172
|
||||
__SYSCALL(__NR_getpid, sys_getpid)
|
||||
#define __NR_getppid 173
|
||||
__SYSCALL(__NR_getppid, sys_getppid)
|
||||
#define __NR_getuid 174
|
||||
__SYSCALL(__NR_getuid, sys_getuid)
|
||||
#define __NR_geteuid 175
|
||||
__SYSCALL(__NR_geteuid, sys_geteuid)
|
||||
#define __NR_getgid 176
|
||||
__SYSCALL(__NR_getgid, sys_getgid)
|
||||
#define __NR_getegid 177
|
||||
__SYSCALL(__NR_getegid, sys_getegid)
|
||||
#define __NR_gettid 178
|
||||
__SYSCALL(__NR_gettid, sys_gettid)
|
||||
#define __NR_sysinfo 179
|
||||
__SC_COMP(__NR_sysinfo, sys_sysinfo, compat_sys_sysinfo)
|
||||
|
||||
/* ipc/mqueue.c */
|
||||
#define __NR_mq_open 180
|
||||
__SC_COMP(__NR_mq_open, sys_mq_open, compat_sys_mq_open)
|
||||
#define __NR_mq_unlink 181
|
||||
__SYSCALL(__NR_mq_unlink, sys_mq_unlink)
|
||||
#define __NR_mq_timedsend 182
|
||||
__SC_COMP(__NR_mq_timedsend, sys_mq_timedsend, compat_sys_mq_timedsend)
|
||||
#define __NR_mq_timedreceive 183
|
||||
__SC_COMP(__NR_mq_timedreceive, sys_mq_timedreceive, \
|
||||
compat_sys_mq_timedreceive)
|
||||
#define __NR_mq_notify 184
|
||||
__SC_COMP(__NR_mq_notify, sys_mq_notify, compat_sys_mq_notify)
|
||||
#define __NR_mq_getsetattr 185
|
||||
__SC_COMP(__NR_mq_getsetattr, sys_mq_getsetattr, compat_sys_mq_getsetattr)
|
||||
|
||||
/* ipc/msg.c */
|
||||
#define __NR_msgget 186
|
||||
__SYSCALL(__NR_msgget, sys_msgget)
|
||||
#define __NR_msgctl 187
|
||||
__SC_COMP(__NR_msgctl, sys_msgctl, compat_sys_msgctl)
|
||||
#define __NR_msgrcv 188
|
||||
__SC_COMP(__NR_msgrcv, sys_msgrcv, compat_sys_msgrcv)
|
||||
#define __NR_msgsnd 189
|
||||
__SC_COMP(__NR_msgsnd, sys_msgsnd, compat_sys_msgsnd)
|
||||
|
||||
/* ipc/sem.c */
|
||||
#define __NR_semget 190
|
||||
__SYSCALL(__NR_semget, sys_semget)
|
||||
#define __NR_semctl 191
|
||||
__SC_COMP(__NR_semctl, sys_semctl, compat_sys_semctl)
|
||||
#define __NR_semtimedop 192
|
||||
__SC_COMP(__NR_semtimedop, sys_semtimedop, compat_sys_semtimedop)
|
||||
#define __NR_semop 193
|
||||
__SYSCALL(__NR_semop, sys_semop)
|
||||
|
||||
/* ipc/shm.c */
|
||||
#define __NR_shmget 194
|
||||
__SYSCALL(__NR_shmget, sys_shmget)
|
||||
#define __NR_shmctl 195
|
||||
__SC_COMP(__NR_shmctl, sys_shmctl, compat_sys_shmctl)
|
||||
#define __NR_shmat 196
|
||||
__SC_COMP(__NR_shmat, sys_shmat, compat_sys_shmat)
|
||||
#define __NR_shmdt 197
|
||||
__SYSCALL(__NR_shmdt, sys_shmdt)
|
||||
|
||||
/* net/socket.c */
|
||||
#define __NR_socket 198
|
||||
__SYSCALL(__NR_socket, sys_socket)
|
||||
#define __NR_socketpair 199
|
||||
__SYSCALL(__NR_socketpair, sys_socketpair)
|
||||
#define __NR_bind 200
|
||||
__SYSCALL(__NR_bind, sys_bind)
|
||||
#define __NR_listen 201
|
||||
__SYSCALL(__NR_listen, sys_listen)
|
||||
#define __NR_accept 202
|
||||
__SYSCALL(__NR_accept, sys_accept)
|
||||
#define __NR_connect 203
|
||||
__SYSCALL(__NR_connect, sys_connect)
|
||||
#define __NR_getsockname 204
|
||||
__SYSCALL(__NR_getsockname, sys_getsockname)
|
||||
#define __NR_getpeername 205
|
||||
__SYSCALL(__NR_getpeername, sys_getpeername)
|
||||
#define __NR_sendto 206
|
||||
__SYSCALL(__NR_sendto, sys_sendto)
|
||||
#define __NR_recvfrom 207
|
||||
__SC_COMP(__NR_recvfrom, sys_recvfrom, compat_sys_recvfrom)
|
||||
#define __NR_setsockopt 208
|
||||
__SC_COMP(__NR_setsockopt, sys_setsockopt, compat_sys_setsockopt)
|
||||
#define __NR_getsockopt 209
|
||||
__SC_COMP(__NR_getsockopt, sys_getsockopt, compat_sys_getsockopt)
|
||||
#define __NR_shutdown 210
|
||||
__SYSCALL(__NR_shutdown, sys_shutdown)
|
||||
#define __NR_sendmsg 211
|
||||
__SC_COMP(__NR_sendmsg, sys_sendmsg, compat_sys_sendmsg)
|
||||
#define __NR_recvmsg 212
|
||||
__SC_COMP(__NR_recvmsg, sys_recvmsg, compat_sys_recvmsg)
|
||||
|
||||
/* mm/filemap.c */
|
||||
#define __NR_readahead 213
|
||||
__SC_COMP(__NR_readahead, sys_readahead, compat_sys_readahead)
|
||||
|
||||
/* mm/nommu.c, also with MMU */
|
||||
#define __NR_brk 214
|
||||
__SYSCALL(__NR_brk, sys_brk)
|
||||
#define __NR_munmap 215
|
||||
__SYSCALL(__NR_munmap, sys_munmap)
|
||||
#define __NR_mremap 216
|
||||
__SYSCALL(__NR_mremap, sys_mremap)
|
||||
|
||||
/* security/keys/keyctl.c */
|
||||
#define __NR_add_key 217
|
||||
__SYSCALL(__NR_add_key, sys_add_key)
|
||||
#define __NR_request_key 218
|
||||
__SYSCALL(__NR_request_key, sys_request_key)
|
||||
#define __NR_keyctl 219
|
||||
__SC_COMP(__NR_keyctl, sys_keyctl, compat_sys_keyctl)
|
||||
|
||||
/* arch/example/kernel/sys_example.c */
|
||||
#define __NR_clone 220
|
||||
__SYSCALL(__NR_clone, sys_clone)
|
||||
#define __NR_execve 221
|
||||
__SC_COMP(__NR_execve, sys_execve, compat_sys_execve)
|
||||
|
||||
#define __NR3264_mmap 222
|
||||
__SC_3264(__NR3264_mmap, sys_mmap2, sys_mmap)
|
||||
/* mm/fadvise.c */
|
||||
#define __NR3264_fadvise64 223
|
||||
__SC_COMP(__NR3264_fadvise64, sys_fadvise64_64, compat_sys_fadvise64_64)
|
||||
|
||||
/* mm/, CONFIG_MMU only */
|
||||
#ifndef __ARCH_NOMMU
|
||||
#define __NR_swapon 224
|
||||
__SYSCALL(__NR_swapon, sys_swapon)
|
||||
#define __NR_swapoff 225
|
||||
__SYSCALL(__NR_swapoff, sys_swapoff)
|
||||
#define __NR_mprotect 226
|
||||
__SYSCALL(__NR_mprotect, sys_mprotect)
|
||||
#define __NR_msync 227
|
||||
__SYSCALL(__NR_msync, sys_msync)
|
||||
#define __NR_mlock 228
|
||||
__SYSCALL(__NR_mlock, sys_mlock)
|
||||
#define __NR_munlock 229
|
||||
__SYSCALL(__NR_munlock, sys_munlock)
|
||||
#define __NR_mlockall 230
|
||||
__SYSCALL(__NR_mlockall, sys_mlockall)
|
||||
#define __NR_munlockall 231
|
||||
__SYSCALL(__NR_munlockall, sys_munlockall)
|
||||
#define __NR_mincore 232
|
||||
__SYSCALL(__NR_mincore, sys_mincore)
|
||||
#define __NR_madvise 233
|
||||
__SYSCALL(__NR_madvise, sys_madvise)
|
||||
#define __NR_remap_file_pages 234
|
||||
__SYSCALL(__NR_remap_file_pages, sys_remap_file_pages)
|
||||
#define __NR_mbind 235
|
||||
__SC_COMP(__NR_mbind, sys_mbind, compat_sys_mbind)
|
||||
#define __NR_get_mempolicy 236
|
||||
__SC_COMP(__NR_get_mempolicy, sys_get_mempolicy, compat_sys_get_mempolicy)
|
||||
#define __NR_set_mempolicy 237
|
||||
__SC_COMP(__NR_set_mempolicy, sys_set_mempolicy, compat_sys_set_mempolicy)
|
||||
#define __NR_migrate_pages 238
|
||||
__SC_COMP(__NR_migrate_pages, sys_migrate_pages, compat_sys_migrate_pages)
|
||||
#define __NR_move_pages 239
|
||||
__SC_COMP(__NR_move_pages, sys_move_pages, compat_sys_move_pages)
|
||||
#endif
|
||||
|
||||
#define __NR_rt_tgsigqueueinfo 240
|
||||
__SC_COMP(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo, \
|
||||
compat_sys_rt_tgsigqueueinfo)
|
||||
#define __NR_perf_event_open 241
|
||||
__SYSCALL(__NR_perf_event_open, sys_perf_event_open)
|
||||
#define __NR_accept4 242
|
||||
__SYSCALL(__NR_accept4, sys_accept4)
|
||||
#define __NR_recvmmsg 243
|
||||
__SC_COMP(__NR_recvmmsg, sys_recvmmsg, compat_sys_recvmmsg)
|
||||
|
||||
/*
|
||||
* Architectures may provide up to 16 syscalls of their own
|
||||
* starting with this value.
|
||||
*/
|
||||
#define __NR_arch_specific_syscall 244
|
||||
|
||||
#define __NR_wait4 260
|
||||
__SC_COMP(__NR_wait4, sys_wait4, compat_sys_wait4)
|
||||
#define __NR_prlimit64 261
|
||||
__SYSCALL(__NR_prlimit64, sys_prlimit64)
|
||||
#define __NR_fanotify_init 262
|
||||
__SYSCALL(__NR_fanotify_init, sys_fanotify_init)
|
||||
#define __NR_fanotify_mark 263
|
||||
__SYSCALL(__NR_fanotify_mark, sys_fanotify_mark)
|
||||
#define __NR_name_to_handle_at 264
|
||||
__SYSCALL(__NR_name_to_handle_at, sys_name_to_handle_at)
|
||||
#define __NR_open_by_handle_at 265
|
||||
__SC_COMP(__NR_open_by_handle_at, sys_open_by_handle_at, \
|
||||
compat_sys_open_by_handle_at)
|
||||
#define __NR_clock_adjtime 266
|
||||
__SC_COMP(__NR_clock_adjtime, sys_clock_adjtime, compat_sys_clock_adjtime)
|
||||
#define __NR_syncfs 267
|
||||
__SYSCALL(__NR_syncfs, sys_syncfs)
|
||||
#define __NR_setns 268
|
||||
__SYSCALL(__NR_setns, sys_setns)
|
||||
#define __NR_sendmmsg 269
|
||||
__SC_COMP(__NR_sendmmsg, sys_sendmmsg, compat_sys_sendmmsg)
|
||||
#define __NR_process_vm_readv 270
|
||||
__SC_COMP(__NR_process_vm_readv, sys_process_vm_readv, \
|
||||
compat_sys_process_vm_readv)
|
||||
#define __NR_process_vm_writev 271
|
||||
__SC_COMP(__NR_process_vm_writev, sys_process_vm_writev, \
|
||||
compat_sys_process_vm_writev)
|
||||
#define __NR_kcmp 272
|
||||
__SYSCALL(__NR_kcmp, sys_kcmp)
|
||||
#define __NR_finit_module 273
|
||||
__SYSCALL(__NR_finit_module, sys_finit_module)
|
||||
#define __NR_sched_setattr 274
|
||||
__SYSCALL(__NR_sched_setattr, sys_sched_setattr)
|
||||
#define __NR_sched_getattr 275
|
||||
__SYSCALL(__NR_sched_getattr, sys_sched_getattr)
|
||||
#define __NR_renameat2 276
|
||||
__SYSCALL(__NR_renameat2, sys_renameat2)
|
||||
#define __NR_seccomp 277
|
||||
__SYSCALL(__NR_seccomp, sys_seccomp)
|
||||
#define __NR_getrandom 278
|
||||
__SYSCALL(__NR_getrandom, sys_getrandom)
|
||||
#define __NR_memfd_create 279
|
||||
__SYSCALL(__NR_memfd_create, sys_memfd_create)
|
||||
#define __NR_bpf 280
|
||||
__SYSCALL(__NR_bpf, sys_bpf)
|
||||
#define __NR_execveat 281
|
||||
__SC_COMP(__NR_execveat, sys_execveat, compat_sys_execveat)
|
||||
#define __NR_userfaultfd 282
|
||||
__SYSCALL(__NR_userfaultfd, sys_userfaultfd)
|
||||
#define __NR_membarrier 283
|
||||
__SYSCALL(__NR_membarrier, sys_membarrier)
|
||||
#define __NR_mlock2 284
|
||||
__SYSCALL(__NR_mlock2, sys_mlock2)
|
||||
#define __NR_copy_file_range 285
|
||||
__SYSCALL(__NR_copy_file_range, sys_copy_file_range)
|
||||
#define __NR_preadv2 286
|
||||
__SC_COMP(__NR_preadv2, sys_preadv2, compat_sys_preadv2)
|
||||
#define __NR_pwritev2 287
|
||||
__SC_COMP(__NR_pwritev2, sys_pwritev2, compat_sys_pwritev2)
|
||||
#define __NR_pkey_mprotect 288
|
||||
__SYSCALL(__NR_pkey_mprotect, sys_pkey_mprotect)
|
||||
#define __NR_pkey_alloc 289
|
||||
__SYSCALL(__NR_pkey_alloc, sys_pkey_alloc)
|
||||
#define __NR_pkey_free 290
|
||||
__SYSCALL(__NR_pkey_free, sys_pkey_free)
|
||||
#define __NR_statx 291
|
||||
__SYSCALL(__NR_statx, sys_statx)
|
||||
#define __NR_io_pgetevents 292
|
||||
__SC_COMP(__NR_io_pgetevents, sys_io_pgetevents, compat_sys_io_pgetevents)
|
||||
|
||||
#undef __NR_syscalls
|
||||
#define __NR_syscalls 293
|
||||
|
||||
/*
|
||||
* 32 bit systems traditionally used different
|
||||
* syscalls for off_t and loff_t arguments, while
|
||||
* 64 bit systems only need the off_t version.
|
||||
* For new 32 bit platforms, there is no need to
|
||||
* implement the old 32 bit off_t syscalls, so
|
||||
* they take different names.
|
||||
* Here we map the numbers so that both versions
|
||||
* use the same syscall table layout.
|
||||
*/
|
||||
#if __BITS_PER_LONG == 64 && !defined(__SYSCALL_COMPAT)
|
||||
#define __NR_fcntl __NR3264_fcntl
|
||||
#define __NR_statfs __NR3264_statfs
|
||||
#define __NR_fstatfs __NR3264_fstatfs
|
||||
#define __NR_truncate __NR3264_truncate
|
||||
#define __NR_ftruncate __NR3264_ftruncate
|
||||
#define __NR_lseek __NR3264_lseek
|
||||
#define __NR_sendfile __NR3264_sendfile
|
||||
#define __NR_newfstatat __NR3264_fstatat
|
||||
#define __NR_fstat __NR3264_fstat
|
||||
#define __NR_mmap __NR3264_mmap
|
||||
#define __NR_fadvise64 __NR3264_fadvise64
|
||||
#ifdef __NR3264_stat
|
||||
#define __NR_stat __NR3264_stat
|
||||
#define __NR_lstat __NR3264_lstat
|
||||
#endif
|
||||
#else
|
||||
#define __NR_fcntl64 __NR3264_fcntl
|
||||
#define __NR_statfs64 __NR3264_statfs
|
||||
#define __NR_fstatfs64 __NR3264_fstatfs
|
||||
#define __NR_truncate64 __NR3264_truncate
|
||||
#define __NR_ftruncate64 __NR3264_ftruncate
|
||||
#define __NR_llseek __NR3264_lseek
|
||||
#define __NR_sendfile64 __NR3264_sendfile
|
||||
#define __NR_fstatat64 __NR3264_fstatat
|
||||
#define __NR_fstat64 __NR3264_fstat
|
||||
#define __NR_mmap2 __NR3264_mmap
|
||||
#define __NR_fadvise64_64 __NR3264_fadvise64
|
||||
#ifdef __NR3264_stat
|
||||
#define __NR_stat64 __NR3264_stat
|
||||
#define __NR_lstat64 __NR3264_lstat
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -18,6 +18,10 @@ various perf commands with the -e option.
|
|||
|
||||
OPTIONS
|
||||
-------
|
||||
-d::
|
||||
--desc::
|
||||
Print extra event descriptions. (default)
|
||||
|
||||
--no-desc::
|
||||
Don't print descriptions.
|
||||
|
||||
|
|
@ -25,11 +29,13 @@ Don't print descriptions.
|
|||
--long-desc::
|
||||
Print longer event descriptions.
|
||||
|
||||
--debug::
|
||||
Enable debugging output.
|
||||
|
||||
--details::
|
||||
Print how named events are resolved internally into perf events, and also
|
||||
any extra expressions computed by perf stat.
|
||||
|
||||
|
||||
[[EVENT_MODIFIERS]]
|
||||
EVENT MODIFIERS
|
||||
---------------
|
||||
|
|
|
|||
|
|
@ -54,6 +54,8 @@ endif
|
|||
|
||||
ifeq ($(SRCARCH),arm64)
|
||||
NO_PERF_REGS := 0
|
||||
NO_SYSCALL_TABLE := 0
|
||||
CFLAGS += -I$(OUTPUT)arch/arm64/include/generated
|
||||
LIBUNWIND_LIBS = -lunwind -lunwind-aarch64
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -4,3 +4,24 @@ PERF_HAVE_DWARF_REGS := 1
|
|||
endif
|
||||
PERF_HAVE_JITDUMP := 1
|
||||
PERF_HAVE_ARCH_REGS_QUERY_REGISTER_OFFSET := 1
|
||||
|
||||
#
|
||||
# Syscall table generation for perf
|
||||
#
|
||||
|
||||
out := $(OUTPUT)arch/arm64/include/generated/asm
|
||||
header := $(out)/syscalls.c
|
||||
sysdef := $(srctree)/tools/include/uapi/asm-generic/unistd.h
|
||||
sysprf := $(srctree)/tools/perf/arch/arm64/entry/syscalls/
|
||||
systbl := $(sysprf)/mksyscalltbl
|
||||
|
||||
# Create output directory if not already present
|
||||
_dummy := $(shell [ -d '$(out)' ] || mkdir -p '$(out)')
|
||||
|
||||
$(header): $(sysdef) $(systbl)
|
||||
$(Q)$(SHELL) '$(systbl)' '$(CC)' '$(HOSTCC)' $(sysdef) > $@
|
||||
|
||||
clean::
|
||||
$(call QUIET_CLEAN, arm64) $(RM) $(header)
|
||||
|
||||
archheaders: $(header)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,62 @@
|
|||
#!/bin/sh
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
#
|
||||
# Generate system call table for perf. Derived from
|
||||
# powerpc script.
|
||||
#
|
||||
# Copyright IBM Corp. 2017
|
||||
# Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
|
||||
# Changed by: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
|
||||
# Changed by: Kim Phillips <kim.phillips@arm.com>
|
||||
|
||||
gcc=$1
|
||||
hostcc=$2
|
||||
input=$3
|
||||
|
||||
if ! test -r $input; then
|
||||
echo "Could not read input file" >&2
|
||||
exit 1
|
||||
fi
|
||||
|
||||
create_table_from_c()
|
||||
{
|
||||
local sc nr last_sc
|
||||
|
||||
create_table_exe=`mktemp /tmp/create-table-XXXXXX`
|
||||
|
||||
{
|
||||
|
||||
cat <<-_EoHEADER
|
||||
#include <stdio.h>
|
||||
#define __ARCH_WANT_RENAMEAT
|
||||
#include "$input"
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
_EoHEADER
|
||||
|
||||
while read sc nr; do
|
||||
printf "%s\n" " printf(\"\\t[%d] = \\\"$sc\\\",\\n\", __NR_$sc);"
|
||||
last_sc=$sc
|
||||
done
|
||||
|
||||
printf "%s\n" " printf(\"#define SYSCALLTBL_ARM64_MAX_ID %d\\n\", __NR_$last_sc);"
|
||||
printf "}\n"
|
||||
|
||||
} | $hostcc -o $create_table_exe -x c -
|
||||
|
||||
$create_table_exe
|
||||
|
||||
rm -f $create_table_exe
|
||||
}
|
||||
|
||||
create_table()
|
||||
{
|
||||
echo "static const char *syscalltbl_arm64[] = {"
|
||||
create_table_from_c
|
||||
echo "};"
|
||||
}
|
||||
|
||||
$gcc -E -dM -x c $input \
|
||||
|sed -ne 's/^#define __NR_//p' \
|
||||
|sort -t' ' -k2 -nu \
|
||||
|create_table
|
||||
|
|
@ -58,9 +58,13 @@ static int check_return_reg(int ra_regno, Dwarf_Frame *frame)
|
|||
}
|
||||
|
||||
/*
|
||||
* Check if return address is on the stack.
|
||||
* Check if return address is on the stack. If return address
|
||||
* is in a register (typically R0), it is yet to be saved on
|
||||
* the stack.
|
||||
*/
|
||||
if (nops != 0 || ops != NULL)
|
||||
if ((nops != 0 || ops != NULL) &&
|
||||
!(nops == 1 && ops[0].atom == DW_OP_regx &&
|
||||
ops[0].number2 == 0 && ops[0].offset == 0))
|
||||
return 0;
|
||||
|
||||
/*
|
||||
|
|
@ -246,7 +250,7 @@ int arch_skip_callchain_idx(struct thread *thread, struct ip_callchain *chain)
|
|||
if (!chain || chain->nr < 3)
|
||||
return skip_slot;
|
||||
|
||||
ip = chain->ips[2];
|
||||
ip = chain->ips[1];
|
||||
|
||||
thread__find_symbol(thread, PERF_RECORD_MISC_USER, ip, &al);
|
||||
|
||||
|
|
|
|||
|
|
@ -102,7 +102,7 @@ const char * const kvm_skip_events[] = {
|
|||
|
||||
int cpu_isa_init(struct perf_kvm_stat *kvm, const char *cpuid)
|
||||
{
|
||||
if (strstr(cpuid, "IBM/S390")) {
|
||||
if (strstr(cpuid, "IBM")) {
|
||||
kvm->exit_reasons = sie_exit_reasons;
|
||||
kvm->exit_reasons_isa = "SIE";
|
||||
} else
|
||||
|
|
|
|||
|
|
@ -2193,7 +2193,7 @@ static void print_cacheline(struct c2c_hists *c2c_hists,
|
|||
fprintf(out, "%s\n", bf);
|
||||
fprintf(out, " -------------------------------------------------------------\n");
|
||||
|
||||
hists__fprintf(&c2c_hists->hists, false, 0, 0, 0, out, true);
|
||||
hists__fprintf(&c2c_hists->hists, false, 0, 0, 0, out, false);
|
||||
}
|
||||
|
||||
static void print_pareto(FILE *out)
|
||||
|
|
@ -2268,7 +2268,7 @@ static void perf_c2c__hists_fprintf(FILE *out, struct perf_session *session)
|
|||
fprintf(out, "=================================================\n");
|
||||
fprintf(out, "#\n");
|
||||
|
||||
hists__fprintf(&c2c.hists.hists, true, 0, 0, 0, stdout, false);
|
||||
hists__fprintf(&c2c.hists.hists, true, 0, 0, 0, stdout, true);
|
||||
|
||||
fprintf(out, "\n");
|
||||
fprintf(out, "=================================================\n");
|
||||
|
|
|
|||
|
|
@ -696,7 +696,7 @@ static void hists__process(struct hists *hists)
|
|||
hists__output_resort(hists, NULL);
|
||||
|
||||
hists__fprintf(hists, !quiet, 0, 0, 0, stdout,
|
||||
symbol_conf.use_callchain);
|
||||
!symbol_conf.use_callchain);
|
||||
}
|
||||
|
||||
static void data__fprintf(void)
|
||||
|
|
|
|||
|
|
@ -478,8 +478,8 @@ static int perf_evlist__tty_browse_hists(struct perf_evlist *evlist,
|
|||
|
||||
hists__fprintf_nr_sample_events(hists, rep, evname, stdout);
|
||||
hists__fprintf(hists, !quiet, 0, 0, rep->min_percent, stdout,
|
||||
symbol_conf.use_callchain ||
|
||||
symbol_conf.show_branchflag_count);
|
||||
!(symbol_conf.use_callchain ||
|
||||
symbol_conf.show_branchflag_count));
|
||||
fprintf(stdout, "\n\n");
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -296,18 +296,6 @@ static int create_perf_stat_counter(struct perf_evsel *evsel)
|
|||
return perf_evsel__open_per_thread(evsel, evsel_list->threads);
|
||||
}
|
||||
|
||||
/*
|
||||
* Does the counter have nsecs as a unit?
|
||||
*/
|
||||
static inline int nsec_counter(struct perf_evsel *evsel)
|
||||
{
|
||||
if (perf_evsel__match(evsel, SOFTWARE, SW_CPU_CLOCK) ||
|
||||
perf_evsel__match(evsel, SOFTWARE, SW_TASK_CLOCK))
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int process_synthesized_event(struct perf_tool *tool __maybe_unused,
|
||||
union perf_event *event,
|
||||
struct perf_sample *sample __maybe_unused,
|
||||
|
|
@ -1058,34 +1046,6 @@ static void print_metric_header(void *ctx, const char *color __maybe_unused,
|
|||
fprintf(os->fh, "%*s ", metric_only_len, unit);
|
||||
}
|
||||
|
||||
static void nsec_printout(int id, int nr, struct perf_evsel *evsel, double avg)
|
||||
{
|
||||
FILE *output = stat_config.output;
|
||||
double msecs = avg / NSEC_PER_MSEC;
|
||||
const char *fmt_v, *fmt_n;
|
||||
char name[25];
|
||||
|
||||
fmt_v = csv_output ? "%.6f%s" : "%18.6f%s";
|
||||
fmt_n = csv_output ? "%s" : "%-25s";
|
||||
|
||||
aggr_printout(evsel, id, nr);
|
||||
|
||||
scnprintf(name, sizeof(name), "%s%s",
|
||||
perf_evsel__name(evsel), csv_output ? "" : " (msec)");
|
||||
|
||||
fprintf(output, fmt_v, msecs, csv_sep);
|
||||
|
||||
if (csv_output)
|
||||
fprintf(output, "%s%s", evsel->unit, csv_sep);
|
||||
else
|
||||
fprintf(output, "%-*s%s", unit_width, evsel->unit, csv_sep);
|
||||
|
||||
fprintf(output, fmt_n, name);
|
||||
|
||||
if (evsel->cgrp)
|
||||
fprintf(output, "%s%s", csv_sep, evsel->cgrp->name);
|
||||
}
|
||||
|
||||
static int first_shadow_cpu(struct perf_evsel *evsel, int id)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -1241,11 +1201,7 @@ static void printout(int id, int nr, struct perf_evsel *counter, double uval,
|
|||
return;
|
||||
}
|
||||
|
||||
if (metric_only)
|
||||
/* nothing */;
|
||||
else if (nsec_counter(counter))
|
||||
nsec_printout(id, nr, counter, uval);
|
||||
else
|
||||
if (!metric_only)
|
||||
abs_printout(id, nr, counter, uval);
|
||||
|
||||
out.print_metric = pm;
|
||||
|
|
@ -1331,7 +1287,7 @@ static void collect_all_aliases(struct perf_evsel *counter,
|
|||
alias->scale != counter->scale ||
|
||||
alias->cgrp != counter->cgrp ||
|
||||
strcmp(alias->unit, counter->unit) ||
|
||||
nsec_counter(alias) != nsec_counter(counter))
|
||||
perf_evsel__is_clock(alias) != perf_evsel__is_clock(counter))
|
||||
break;
|
||||
alias->merged_stat = true;
|
||||
cb(alias, data, false);
|
||||
|
|
@ -2449,6 +2405,18 @@ static int add_default_attributes(void)
|
|||
return 0;
|
||||
|
||||
if (transaction_run) {
|
||||
/* Handle -T as -M transaction. Once platform specific metrics
|
||||
* support has been added to the json files, all archictures
|
||||
* will use this approach. To determine transaction support
|
||||
* on an architecture test for such a metric name.
|
||||
*/
|
||||
if (metricgroup__has_metric("transaction")) {
|
||||
struct option opt = { .value = &evsel_list };
|
||||
|
||||
return metricgroup__parse_groups(&opt, "transaction",
|
||||
&metric_events);
|
||||
}
|
||||
|
||||
if (pmu_have_event("cpu", "cycles-ct") &&
|
||||
pmu_have_event("cpu", "el-start"))
|
||||
err = parse_events(evsel_list, transaction_attrs,
|
||||
|
|
|
|||
|
|
@ -307,7 +307,7 @@ static void perf_top__print_sym_table(struct perf_top *top)
|
|||
hists__output_recalc_col_len(hists, top->print_entries - printed);
|
||||
putchar('\n');
|
||||
hists__fprintf(hists, false, top->print_entries - printed, win_width,
|
||||
top->min_percent, stdout, symbol_conf.use_callchain);
|
||||
top->min_percent, stdout, !symbol_conf.use_callchain);
|
||||
}
|
||||
|
||||
static void prompt_integer(int *target, const char *msg)
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@ arch/s390/include/uapi/asm/ptrace.h
|
|||
arch/s390/include/uapi/asm/sie.h
|
||||
arch/arm/include/uapi/asm/kvm.h
|
||||
arch/arm64/include/uapi/asm/kvm.h
|
||||
arch/arm64/include/uapi/asm/unistd.h
|
||||
arch/alpha/include/uapi/asm/errno.h
|
||||
arch/mips/include/asm/errno.h
|
||||
arch/mips/include/uapi/asm/errno.h
|
||||
|
|
@ -53,6 +54,7 @@ include/uapi/asm-generic/errno.h
|
|||
include/uapi/asm-generic/errno-base.h
|
||||
include/uapi/asm-generic/ioctls.h
|
||||
include/uapi/asm-generic/mman-common.h
|
||||
include/uapi/asm-generic/unistd.h
|
||||
'
|
||||
|
||||
check_2 () {
|
||||
|
|
|
|||
|
|
@ -1,71 +1,83 @@
|
|||
[
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "0",
|
||||
"EventName": "CPU_CYCLES",
|
||||
"BriefDescription": "CPU Cycles",
|
||||
"PublicDescription": "Cycle Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "1",
|
||||
"EventName": "INSTRUCTIONS",
|
||||
"BriefDescription": "Instructions",
|
||||
"PublicDescription": "Instruction Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "2",
|
||||
"EventName": "L1I_DIR_WRITES",
|
||||
"BriefDescription": "L1I Directory Writes",
|
||||
"PublicDescription": "Level-1 I-Cache Directory Write Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "3",
|
||||
"EventName": "L1I_PENALTY_CYCLES",
|
||||
"BriefDescription": "L1I Penalty Cycles",
|
||||
"PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "4",
|
||||
"EventName": "L1D_DIR_WRITES",
|
||||
"BriefDescription": "L1D Directory Writes",
|
||||
"PublicDescription": "Level-1 D-Cache Directory Write Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "5",
|
||||
"EventName": "L1D_PENALTY_CYCLES",
|
||||
"BriefDescription": "L1D Penalty Cycles",
|
||||
"PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "32",
|
||||
"EventName": "PROBLEM_STATE_CPU_CYCLES",
|
||||
"BriefDescription": "Problem-State CPU Cycles",
|
||||
"PublicDescription": "Problem-State Cycle Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "33",
|
||||
"EventName": "PROBLEM_STATE_INSTRUCTIONS",
|
||||
"BriefDescription": "Problem-State Instructions",
|
||||
"PublicDescription": "Problem-State Instruction Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "34",
|
||||
"EventName": "PROBLEM_STATE_L1I_DIR_WRITES",
|
||||
"BriefDescription": "Problem-State L1I Directory Writes",
|
||||
"PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "35",
|
||||
"EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES",
|
||||
"BriefDescription": "Problem-State L1I Penalty Cycles",
|
||||
"PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "36",
|
||||
"EventName": "PROBLEM_STATE_L1D_DIR_WRITES",
|
||||
"BriefDescription": "Problem-State L1D Directory Writes",
|
||||
"PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "37",
|
||||
"EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES",
|
||||
"BriefDescription": "Problem-State L1D Penalty Cycles",
|
||||
|
|
|
|||
|
|
@ -1,95 +1,111 @@
|
|||
[
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "64",
|
||||
"EventName": "PRNG_FUNCTIONS",
|
||||
"BriefDescription": "PRNG Functions",
|
||||
"PublicDescription": "Total number of the PRNG functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "65",
|
||||
"EventName": "PRNG_CYCLES",
|
||||
"BriefDescription": "PRNG Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "66",
|
||||
"EventName": "PRNG_BLOCKED_FUNCTIONS",
|
||||
"BriefDescription": "PRNG Blocked Functions",
|
||||
"PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "67",
|
||||
"EventName": "PRNG_BLOCKED_CYCLES",
|
||||
"BriefDescription": "PRNG Blocked Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "68",
|
||||
"EventName": "SHA_FUNCTIONS",
|
||||
"BriefDescription": "SHA Functions",
|
||||
"PublicDescription": "Total number of SHA functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "69",
|
||||
"EventName": "SHA_CYCLES",
|
||||
"BriefDescription": "SHA Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "70",
|
||||
"EventName": "SHA_BLOCKED_FUNCTIONS",
|
||||
"BriefDescription": "SHA Blocked Functions",
|
||||
"PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "71",
|
||||
"EventName": "SHA_BLOCKED_CYCLES",
|
||||
"BriefDescription": "SHA Bloced Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "72",
|
||||
"EventName": "DEA_FUNCTIONS",
|
||||
"BriefDescription": "DEA Functions",
|
||||
"PublicDescription": "Total number of the DEA functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "73",
|
||||
"EventName": "DEA_CYCLES",
|
||||
"BriefDescription": "DEA Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "74",
|
||||
"EventName": "DEA_BLOCKED_FUNCTIONS",
|
||||
"BriefDescription": "DEA Blocked Functions",
|
||||
"PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "75",
|
||||
"EventName": "DEA_BLOCKED_CYCLES",
|
||||
"BriefDescription": "DEA Blocked Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "76",
|
||||
"EventName": "AES_FUNCTIONS",
|
||||
"BriefDescription": "AES Functions",
|
||||
"PublicDescription": "Total number of AES functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "77",
|
||||
"EventName": "AES_CYCLES",
|
||||
"BriefDescription": "AES Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "78",
|
||||
"EventName": "AES_BLOCKED_FUNCTIONS",
|
||||
"BriefDescription": "AES Blocked Functions",
|
||||
"PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "79",
|
||||
"EventName": "AES_BLOCKED_CYCLES",
|
||||
"BriefDescription": "AES Blocked Cycles",
|
||||
|
|
|
|||
|
|
@ -1,107 +1,125 @@
|
|||
[
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "128",
|
||||
"EventName": "L1I_L2_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I L2 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from the Level-2 (L1.5) cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "129",
|
||||
"EventName": "L1D_L2_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D L2 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from the Level-2 (L1.5) cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "130",
|
||||
"EventName": "L1I_L3_LOCAL_WRITES",
|
||||
"BriefDescription": "L1I L3 Local Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 I-Cache directory where the installed cache line was sourced from the Level-3 cache that is on the same book as the Instruction cache (Local L2 cache)"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "131",
|
||||
"EventName": "L1D_L3_LOCAL_WRITES",
|
||||
"BriefDescription": "L1D L3 Local Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 D-Cache directory where the installtion cache line was source from the Level-3 cache that is on the same book as the Data cache (Local L2 cache)"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "132",
|
||||
"EventName": "L1I_L3_REMOTE_WRITES",
|
||||
"BriefDescription": "L1I L3 Remote Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 I-Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Instruction cache (Remote L2 cache)"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "133",
|
||||
"EventName": "L1D_L3_REMOTE_WRITES",
|
||||
"BriefDescription": "L1D L3 Remote Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Data cache (Remote L2 cache)"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "134",
|
||||
"EventName": "L1D_LMEM_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D Local Memory Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "135",
|
||||
"EventName": "L1I_LMEM_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I Local Memory Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 I-Cache where the installed cache line was sourced from memory that is attached to the s ame book as the Instruction cache (Local Memory)"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "136",
|
||||
"EventName": "L1D_RO_EXCL_WRITES",
|
||||
"BriefDescription": "L1D Read-only Exclusive Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "137",
|
||||
"EventName": "L1I_CACHELINE_INVALIDATES",
|
||||
"BriefDescription": "L1I Cacheline Invalidates",
|
||||
"PublicDescription": "A cache line in the Level-1 I-Cache has been invalidated by a store on the same CPU as the Level-1 I-Cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "138",
|
||||
"EventName": "ITLB1_WRITES",
|
||||
"BriefDescription": "ITLB1 Writes",
|
||||
"PublicDescription": "A translation entry has been written into the Level-1 Instruction Translation Lookaside Buffer"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "139",
|
||||
"EventName": "DTLB1_WRITES",
|
||||
"BriefDescription": "DTLB1 Writes",
|
||||
"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "140",
|
||||
"EventName": "TLB2_PTE_WRITES",
|
||||
"BriefDescription": "TLB2 PTE Writes",
|
||||
"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "141",
|
||||
"EventName": "TLB2_CRSTE_WRITES",
|
||||
"BriefDescription": "TLB2 CRSTE Writes",
|
||||
"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "142",
|
||||
"EventName": "TLB2_CRSTE_HPAGE_WRITES",
|
||||
"BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
|
||||
"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "145",
|
||||
"EventName": "ITLB1_MISSES",
|
||||
"BriefDescription": "ITLB1 Misses",
|
||||
"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle an ITLB1 miss is in progress"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "146",
|
||||
"EventName": "DTLB1_MISSES",
|
||||
"BriefDescription": "DTLB1 Misses",
|
||||
"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle an DTLB1 miss is in progress"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "147",
|
||||
"EventName": "L2C_STORES_SENT",
|
||||
"BriefDescription": "L2C Stores Sent",
|
||||
|
|
|
|||
|
|
@ -1,71 +1,83 @@
|
|||
[
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "0",
|
||||
"EventName": "CPU_CYCLES",
|
||||
"BriefDescription": "CPU Cycles",
|
||||
"PublicDescription": "Cycle Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "1",
|
||||
"EventName": "INSTRUCTIONS",
|
||||
"BriefDescription": "Instructions",
|
||||
"PublicDescription": "Instruction Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "2",
|
||||
"EventName": "L1I_DIR_WRITES",
|
||||
"BriefDescription": "L1I Directory Writes",
|
||||
"PublicDescription": "Level-1 I-Cache Directory Write Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "3",
|
||||
"EventName": "L1I_PENALTY_CYCLES",
|
||||
"BriefDescription": "L1I Penalty Cycles",
|
||||
"PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "4",
|
||||
"EventName": "L1D_DIR_WRITES",
|
||||
"BriefDescription": "L1D Directory Writes",
|
||||
"PublicDescription": "Level-1 D-Cache Directory Write Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "5",
|
||||
"EventName": "L1D_PENALTY_CYCLES",
|
||||
"BriefDescription": "L1D Penalty Cycles",
|
||||
"PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "32",
|
||||
"EventName": "PROBLEM_STATE_CPU_CYCLES",
|
||||
"BriefDescription": "Problem-State CPU Cycles",
|
||||
"PublicDescription": "Problem-State Cycle Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "33",
|
||||
"EventName": "PROBLEM_STATE_INSTRUCTIONS",
|
||||
"BriefDescription": "Problem-State Instructions",
|
||||
"PublicDescription": "Problem-State Instruction Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "34",
|
||||
"EventName": "PROBLEM_STATE_L1I_DIR_WRITES",
|
||||
"BriefDescription": "Problem-State L1I Directory Writes",
|
||||
"PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "35",
|
||||
"EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES",
|
||||
"BriefDescription": "Problem-State L1I Penalty Cycles",
|
||||
"PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "36",
|
||||
"EventName": "PROBLEM_STATE_L1D_DIR_WRITES",
|
||||
"BriefDescription": "Problem-State L1D Directory Writes",
|
||||
"PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "37",
|
||||
"EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES",
|
||||
"BriefDescription": "Problem-State L1D Penalty Cycles",
|
||||
|
|
|
|||
|
|
@ -1,95 +1,111 @@
|
|||
[
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "64",
|
||||
"EventName": "PRNG_FUNCTIONS",
|
||||
"BriefDescription": "PRNG Functions",
|
||||
"PublicDescription": "Total number of the PRNG functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "65",
|
||||
"EventName": "PRNG_CYCLES",
|
||||
"BriefDescription": "PRNG Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "66",
|
||||
"EventName": "PRNG_BLOCKED_FUNCTIONS",
|
||||
"BriefDescription": "PRNG Blocked Functions",
|
||||
"PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "67",
|
||||
"EventName": "PRNG_BLOCKED_CYCLES",
|
||||
"BriefDescription": "PRNG Blocked Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "68",
|
||||
"EventName": "SHA_FUNCTIONS",
|
||||
"BriefDescription": "SHA Functions",
|
||||
"PublicDescription": "Total number of SHA functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "69",
|
||||
"EventName": "SHA_CYCLES",
|
||||
"BriefDescription": "SHA Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "70",
|
||||
"EventName": "SHA_BLOCKED_FUNCTIONS",
|
||||
"BriefDescription": "SHA Blocked Functions",
|
||||
"PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "71",
|
||||
"EventName": "SHA_BLOCKED_CYCLES",
|
||||
"BriefDescription": "SHA Bloced Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "72",
|
||||
"EventName": "DEA_FUNCTIONS",
|
||||
"BriefDescription": "DEA Functions",
|
||||
"PublicDescription": "Total number of the DEA functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "73",
|
||||
"EventName": "DEA_CYCLES",
|
||||
"BriefDescription": "DEA Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "74",
|
||||
"EventName": "DEA_BLOCKED_FUNCTIONS",
|
||||
"BriefDescription": "DEA Blocked Functions",
|
||||
"PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "75",
|
||||
"EventName": "DEA_BLOCKED_CYCLES",
|
||||
"BriefDescription": "DEA Blocked Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "76",
|
||||
"EventName": "AES_FUNCTIONS",
|
||||
"BriefDescription": "AES Functions",
|
||||
"PublicDescription": "Total number of AES functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "77",
|
||||
"EventName": "AES_CYCLES",
|
||||
"BriefDescription": "AES Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "78",
|
||||
"EventName": "AES_BLOCKED_FUNCTIONS",
|
||||
"BriefDescription": "AES Blocked Functions",
|
||||
"PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "79",
|
||||
"EventName": "AES_BLOCKED_CYCLES",
|
||||
"BriefDescription": "AES Blocked Cycles",
|
||||
|
|
|
|||
|
|
@ -1,335 +1,391 @@
|
|||
[
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "128",
|
||||
"EventName": "L1D_RO_EXCL_WRITES",
|
||||
"BriefDescription": "L1D Read-only Exclusive Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "129",
|
||||
"EventName": "DTLB1_WRITES",
|
||||
"BriefDescription": "DTLB1 Writes",
|
||||
"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "130",
|
||||
"EventName": "DTLB1_MISSES",
|
||||
"BriefDescription": "DTLB1 Misses",
|
||||
"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB1 miss is in progress."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "131",
|
||||
"EventName": "DTLB1_HPAGE_WRITES",
|
||||
"BriefDescription": "DTLB1 One-Megabyte Page Writes",
|
||||
"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "132",
|
||||
"EventName": "DTLB1_GPAGE_WRITES",
|
||||
"BriefDescription": "DTLB1 Two-Gigabyte Page Writes",
|
||||
"PublicDescription": "Counter:132 Name:DTLB1_GPAGE_WRITES A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a two-gigabyte page."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "133",
|
||||
"EventName": "L1D_L2D_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D L2D Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "134",
|
||||
"EventName": "ITLB1_WRITES",
|
||||
"BriefDescription": "ITLB1 Writes",
|
||||
"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "135",
|
||||
"EventName": "ITLB1_MISSES",
|
||||
"BriefDescription": "ITLB1 Misses",
|
||||
"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle an ITLB1 miss is in progress"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "136",
|
||||
"EventName": "L1I_L2I_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I L2I Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "137",
|
||||
"EventName": "TLB2_PTE_WRITES",
|
||||
"BriefDescription": "TLB2 PTE Writes",
|
||||
"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "138",
|
||||
"EventName": "TLB2_CRSTE_HPAGE_WRITES",
|
||||
"BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
|
||||
"PublicDescription": "A translation entry has been written to the Level-2 TLB Combined Region Segment Table Entry arrays for a one-megabyte large page translation"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "139",
|
||||
"EventName": "TLB2_CRSTE_WRITES",
|
||||
"BriefDescription": "TLB2 CRSTE Writes",
|
||||
"PublicDescription": "A translation entry has been written to the Level-2 TLB Combined Region Segment Table Entry arrays"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "140",
|
||||
"EventName": "TX_C_TEND",
|
||||
"BriefDescription": "Completed TEND instructions in constrained TX mode",
|
||||
"PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "141",
|
||||
"EventName": "TX_NC_TEND",
|
||||
"BriefDescription": "Completed TEND instructions in non-constrained TX mode",
|
||||
"PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "143",
|
||||
"EventName": "L1C_TLB1_MISSES",
|
||||
"BriefDescription": "L1C TLB1 Misses",
|
||||
"PublicDescription": "Increments by one for any cycle where a Level-1 cache or Level-1 TLB miss is in progress."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "144",
|
||||
"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D On-Chip L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "145",
|
||||
"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV",
|
||||
"BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "146",
|
||||
"EventName": "L1D_ONNODE_L4_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D On-Node L4 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-4 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "147",
|
||||
"EventName": "L1D_ONNODE_L3_SOURCED_WRITES_IV",
|
||||
"BriefDescription": "L1D On-Node L3 Sourced Writes with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-3 cache with intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "148",
|
||||
"EventName": "L1D_ONNODE_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D On-Node L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-3 cache without intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "149",
|
||||
"EventName": "L1D_ONDRAWER_L4_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D On-Drawer L4 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-4 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "150",
|
||||
"EventName": "L1D_ONDRAWER_L3_SOURCED_WRITES_IV",
|
||||
"BriefDescription": "L1D On-Drawer L3 Sourced Writes with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache with intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "151",
|
||||
"EventName": "L1D_ONDRAWER_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D On-Drawer L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache without intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "152",
|
||||
"EventName": "L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D Off-Drawer Same-Column L4 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-4 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "153",
|
||||
"EventName": "L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV",
|
||||
"BriefDescription": "L1D Off-Drawer Same-Column L3 Sourced Writes with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache with intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "154",
|
||||
"EventName": "L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D Off-Drawer Same-Column L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache without intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "155",
|
||||
"EventName": "L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-4 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "156",
|
||||
"EventName": "L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV",
|
||||
"BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache with intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "157",
|
||||
"EventName": "L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache without intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "158",
|
||||
"EventName": "L1D_ONNODE_MEM_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D On-Node Memory Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Node memory"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "159",
|
||||
"EventName": "L1D_ONDRAWER_MEM_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D On-Drawer Memory Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "160",
|
||||
"EventName": "L1D_OFFDRAWER_MEM_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D Off-Drawer Memory Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "161",
|
||||
"EventName": "L1D_ONCHIP_MEM_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D On-Chip Memory Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "162",
|
||||
"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I On-Chip L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "163",
|
||||
"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV",
|
||||
"BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "164",
|
||||
"EventName": "L1I_ONNODE_L4_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I On-Chip L4 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-4 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "165",
|
||||
"EventName": "L1I_ONNODE_L3_SOURCED_WRITES_IV",
|
||||
"BriefDescription": "L1I On-Node L3 Sourced Writes with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-3 cache with intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "166",
|
||||
"EventName": "L1I_ONNODE_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I On-Node L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-3 cache without intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "167",
|
||||
"EventName": "L1I_ONDRAWER_L4_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I On-Drawer L4 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-4 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "168",
|
||||
"EventName": "L1I_ONDRAWER_L3_SOURCED_WRITES_IV",
|
||||
"BriefDescription": "L1I On-Drawer L3 Sourced Writes with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache with intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "169",
|
||||
"EventName": "L1I_ONDRAWER_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I On-Drawer L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache without intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "170",
|
||||
"EventName": "L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I Off-Drawer Same-Column L4 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-4 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "171",
|
||||
"EventName": "L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV",
|
||||
"BriefDescription": "L1I Off-Drawer Same-Column L3 Sourced Writes with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache with intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "172",
|
||||
"EventName": "L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I Off-Drawer Same-Column L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache without intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "173",
|
||||
"EventName": "L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I Off-Drawer Far-Column L4 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-4 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "174",
|
||||
"EventName": "L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV",
|
||||
"BriefDescription": "L1I Off-Drawer Far-Column L3 Sourced Writes with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache with intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "175",
|
||||
"EventName": "L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I Off-Drawer Far-Column L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache without intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "176",
|
||||
"EventName": "L1I_ONNODE_MEM_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I On-Node Memory Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Node memory"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "177",
|
||||
"EventName": "L1I_ONDRAWER_MEM_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I On-Drawer Memory Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "178",
|
||||
"EventName": "L1I_OFFDRAWER_MEM_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I Off-Drawer Memory Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "179",
|
||||
"EventName": "L1I_ONCHIP_MEM_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I On-Chip Memory Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Chip memory"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "218",
|
||||
"EventName": "TX_NC_TABORT",
|
||||
"BriefDescription": "Aborted transactions in non-constrained TX mode",
|
||||
"PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "219",
|
||||
"EventName": "TX_C_TABORT_NO_SPECIAL",
|
||||
"BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic",
|
||||
"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "220",
|
||||
"EventName": "TX_C_TABORT_SPECIAL",
|
||||
"BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
|
||||
"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "448",
|
||||
"EventName": "MT_DIAG_CYCLES_ONE_THR_ACTIVE",
|
||||
"BriefDescription": "Cycle count with one thread active",
|
||||
"PublicDescription": "Cycle count with one thread active"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "449",
|
||||
"EventName": "MT_DIAG_CYCLES_TWO_THR_ACTIVE",
|
||||
"BriefDescription": "Cycle count with two threads active",
|
||||
|
|
|
|||
|
|
@ -0,0 +1,7 @@
|
|||
[
|
||||
{
|
||||
"BriefDescription": "Transaction count",
|
||||
"MetricName": "transaction",
|
||||
"MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL"
|
||||
}
|
||||
]
|
||||
|
|
@ -1,47 +1,55 @@
|
|||
[
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "0",
|
||||
"EventName": "CPU_CYCLES",
|
||||
"BriefDescription": "CPU Cycles",
|
||||
"PublicDescription": "Cycle Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "1",
|
||||
"EventName": "INSTRUCTIONS",
|
||||
"BriefDescription": "Instructions",
|
||||
"PublicDescription": "Instruction Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "2",
|
||||
"EventName": "L1I_DIR_WRITES",
|
||||
"BriefDescription": "L1I Directory Writes",
|
||||
"PublicDescription": "Level-1 I-Cache Directory Write Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "3",
|
||||
"EventName": "L1I_PENALTY_CYCLES",
|
||||
"BriefDescription": "L1I Penalty Cycles",
|
||||
"PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "4",
|
||||
"EventName": "L1D_DIR_WRITES",
|
||||
"BriefDescription": "L1D Directory Writes",
|
||||
"PublicDescription": "Level-1 D-Cache Directory Write Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "5",
|
||||
"EventName": "L1D_PENALTY_CYCLES",
|
||||
"BriefDescription": "L1D Penalty Cycles",
|
||||
"PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "32",
|
||||
"EventName": "PROBLEM_STATE_CPU_CYCLES",
|
||||
"BriefDescription": "Problem-State CPU Cycles",
|
||||
"PublicDescription": "Problem-State Cycle Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "33",
|
||||
"EventName": "PROBLEM_STATE_INSTRUCTIONS",
|
||||
"BriefDescription": "Problem-State Instructions",
|
||||
|
|
|
|||
|
|
@ -1,95 +1,111 @@
|
|||
[
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "64",
|
||||
"EventName": "PRNG_FUNCTIONS",
|
||||
"BriefDescription": "PRNG Functions",
|
||||
"PublicDescription": "Total number of the PRNG functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "65",
|
||||
"EventName": "PRNG_CYCLES",
|
||||
"BriefDescription": "PRNG Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "66",
|
||||
"EventName": "PRNG_BLOCKED_FUNCTIONS",
|
||||
"BriefDescription": "PRNG Blocked Functions",
|
||||
"PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "67",
|
||||
"EventName": "PRNG_BLOCKED_CYCLES",
|
||||
"BriefDescription": "PRNG Blocked Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "68",
|
||||
"EventName": "SHA_FUNCTIONS",
|
||||
"BriefDescription": "SHA Functions",
|
||||
"PublicDescription": "Total number of SHA functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "69",
|
||||
"EventName": "SHA_CYCLES",
|
||||
"BriefDescription": "SHA Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "70",
|
||||
"EventName": "SHA_BLOCKED_FUNCTIONS",
|
||||
"BriefDescription": "SHA Blocked Functions",
|
||||
"PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "71",
|
||||
"EventName": "SHA_BLOCKED_CYCLES",
|
||||
"BriefDescription": "SHA Bloced Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "72",
|
||||
"EventName": "DEA_FUNCTIONS",
|
||||
"BriefDescription": "DEA Functions",
|
||||
"PublicDescription": "Total number of the DEA functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "73",
|
||||
"EventName": "DEA_CYCLES",
|
||||
"BriefDescription": "DEA Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "74",
|
||||
"EventName": "DEA_BLOCKED_FUNCTIONS",
|
||||
"BriefDescription": "DEA Blocked Functions",
|
||||
"PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "75",
|
||||
"EventName": "DEA_BLOCKED_CYCLES",
|
||||
"BriefDescription": "DEA Blocked Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "76",
|
||||
"EventName": "AES_FUNCTIONS",
|
||||
"BriefDescription": "AES Functions",
|
||||
"PublicDescription": "Total number of AES functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "77",
|
||||
"EventName": "AES_CYCLES",
|
||||
"BriefDescription": "AES Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "78",
|
||||
"EventName": "AES_BLOCKED_FUNCTIONS",
|
||||
"BriefDescription": "AES Blocked Functions",
|
||||
"PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "79",
|
||||
"EventName": "AES_BLOCKED_CYCLES",
|
||||
"BriefDescription": "AES Blocked Cycles",
|
||||
|
|
|
|||
|
|
@ -1,317 +1,370 @@
|
|||
[
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "128",
|
||||
"EventName": "L1D_RO_EXCL_WRITES",
|
||||
"BriefDescription": "L1D Read-only Exclusive Writes",
|
||||
"PublicDescription": "Counter:128 Name:L1D_RO_EXCL_WRITES A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "129",
|
||||
"EventName": "DTLB2_WRITES",
|
||||
"BriefDescription": "DTLB2 Writes",
|
||||
"PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "130",
|
||||
"EventName": "DTLB2_MISSES",
|
||||
"BriefDescription": "DTLB2 Misses",
|
||||
"PublicDescription": "A TLB2 miss is in progress for a request made by the data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "131",
|
||||
"EventName": "DTLB2_HPAGE_WRITES",
|
||||
"BriefDescription": "DTLB2 One-Megabyte Page Writes",
|
||||
"PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page or a Last Host Translation was done"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "132",
|
||||
"EventName": "DTLB2_GPAGE_WRITES",
|
||||
"BriefDescription": "DTLB2 Two-Gigabyte Page Writes",
|
||||
"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "133",
|
||||
"EventName": "L1D_L2D_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D L2D Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "134",
|
||||
"EventName": "ITLB2_WRITES",
|
||||
"BriefDescription": "ITLB2 Writes",
|
||||
"PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "135",
|
||||
"EventName": "ITLB2_MISSES",
|
||||
"BriefDescription": "ITLB2 Misses",
|
||||
"PublicDescription": "A TLB2 miss is in progress for a request made by the instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "136",
|
||||
"EventName": "L1I_L2I_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I L2I Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "137",
|
||||
"EventName": "TLB2_PTE_WRITES",
|
||||
"BriefDescription": "TLB2 PTE Writes",
|
||||
"PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "138",
|
||||
"EventName": "TLB2_CRSTE_WRITES",
|
||||
"BriefDescription": "TLB2 CRSTE Writes",
|
||||
"PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "139",
|
||||
"EventName": "TLB2_ENGINES_BUSY",
|
||||
"BriefDescription": "TLB2 Engines Busy",
|
||||
"PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "140",
|
||||
"EventName": "TX_C_TEND",
|
||||
"BriefDescription": "Completed TEND instructions in constrained TX mode",
|
||||
"PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "141",
|
||||
"EventName": "TX_NC_TEND",
|
||||
"BriefDescription": "Completed TEND instructions in non-constrained TX mode",
|
||||
"PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "143",
|
||||
"EventName": "L1C_TLB2_MISSES",
|
||||
"BriefDescription": "L1C TLB2 Misses",
|
||||
"PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is in progress"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "144",
|
||||
"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D On-Chip L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "145",
|
||||
"EventName": "L1D_ONCHIP_MEMORY_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D On-Chip Memory Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "146",
|
||||
"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV",
|
||||
"BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "147",
|
||||
"EventName": "L1D_ONCLUSTER_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D On-Cluster L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Cluster Level-3 cache withountervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "148",
|
||||
"EventName": "L1D_ONCLUSTER_MEMORY_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D On-Cluster Memory Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster memory"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "149",
|
||||
"EventName": "L1D_ONCLUSTER_L3_SOURCED_WRITES_IV",
|
||||
"BriefDescription": "L1D On-Cluster L3 Sourced Writes with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache with intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "150",
|
||||
"EventName": "L1D_OFFCLUSTER_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D Off-Cluster L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "151",
|
||||
"EventName": "L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D Off-Cluster Memory Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Cluster memory"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "152",
|
||||
"EventName": "L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV",
|
||||
"BriefDescription": "L1D Off-Cluster L3 Sourced Writes with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "153",
|
||||
"EventName": "L1D_OFFDRAWER_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D Off-Drawer L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "154",
|
||||
"EventName": "L1D_OFFDRAWER_MEMORY_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D Off-Drawer Memory Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "155",
|
||||
"EventName": "L1D_OFFDRAWER_L3_SOURCED_WRITES_IV",
|
||||
"BriefDescription": "L1D Off-Drawer L3 Sourced Writes with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "156",
|
||||
"EventName": "L1D_ONDRAWER_L4_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D On-Drawer L4 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer Level-4 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "157",
|
||||
"EventName": "L1D_OFFDRAWER_L4_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D Off-Drawer L4 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "158",
|
||||
"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_RO",
|
||||
"BriefDescription": "L1D On-Chip L3 Sourced Writes read-only",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip L3 but a read-only invalidate was done to remove other copies of the cache line"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "162",
|
||||
"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I On-Chip L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache without intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "163",
|
||||
"EventName": "L1I_ONCHIP_MEMORY_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I On-Chip Memory Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from On-Chip memory"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "164",
|
||||
"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV",
|
||||
"BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache with intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "165",
|
||||
"EventName": "L1I_ONCLUSTER_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I On-Cluster L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache without intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "166",
|
||||
"EventName": "L1I_ONCLUSTER_MEMORY_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I On-Cluster Memory Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster memory"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "167",
|
||||
"EventName": "L1I_ONCLUSTER_L3_SOURCED_WRITES_IV",
|
||||
"BriefDescription": "L1I On-Cluster L3 Sourced Writes with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Cluster Level-3 cache with intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "168",
|
||||
"EventName": "L1I_OFFCLUSTER_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I Off-Cluster L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "169",
|
||||
"EventName": "L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I Off-Cluster Memory Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Cluster memory"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "170",
|
||||
"EventName": "L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV",
|
||||
"BriefDescription": "L1I Off-Cluster L3 Sourced Writes with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "171",
|
||||
"EventName": "L1I_OFFDRAWER_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I Off-Drawer L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "172",
|
||||
"EventName": "L1I_OFFDRAWER_MEMORY_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I Off-Drawer Memory Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "173",
|
||||
"EventName": "L1I_OFFDRAWER_L3_SOURCED_WRITES_IV",
|
||||
"BriefDescription": "L1I Off-Drawer L3 Sourced Writes with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "174",
|
||||
"EventName": "L1I_ONDRAWER_L4_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I On-Drawer L4 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer Level-4 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "175",
|
||||
"EventName": "L1I_OFFDRAWER_L4_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I Off-Drawer L4 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "224",
|
||||
"EventName": "BCD_DFP_EXECUTION_SLOTS",
|
||||
"BriefDescription": "BCD DFP Execution Slots",
|
||||
"PublicDescription": "Count of floating point execution slots used for finished Binary Coded Decimal to Decimal Floating Point conversions. Instructions: CDZT, CXZT, CZDT, CZXT"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "225",
|
||||
"EventName": "VX_BCD_EXECUTION_SLOTS",
|
||||
"BriefDescription": "VX BCD Execution Slots",
|
||||
"PublicDescription": "Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMPVMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOPVCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVDVCVDG"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "226",
|
||||
"EventName": "DECIMAL_INSTRUCTIONS",
|
||||
"BriefDescription": "Decimal Instructions",
|
||||
"PublicDescription": "Decimal instructions dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "232",
|
||||
"EventName": "LAST_HOST_TRANSLATIONS",
|
||||
"BriefDescription": "Last host translation done",
|
||||
"PublicDescription": "Last Host Translation done"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "243",
|
||||
"EventName": "TX_NC_TABORT",
|
||||
"BriefDescription": "Aborted transactions in non-constrained TX mode",
|
||||
"PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "244",
|
||||
"EventName": "TX_C_TABORT_NO_SPECIAL",
|
||||
"BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic",
|
||||
"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "245",
|
||||
"EventName": "TX_C_TABORT_SPECIAL",
|
||||
"BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
|
||||
"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "448",
|
||||
"EventName": "MT_DIAG_CYCLES_ONE_THR_ACTIVE",
|
||||
"BriefDescription": "Cycle count with one thread active",
|
||||
"PublicDescription": "Cycle count with one thread active"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "449",
|
||||
"EventName": "MT_DIAG_CYCLES_TWO_THR_ACTIVE",
|
||||
"BriefDescription": "Cycle count with two threads active",
|
||||
|
|
|
|||
|
|
@ -0,0 +1,7 @@
|
|||
[
|
||||
{
|
||||
"BriefDescription": "Transaction count",
|
||||
"MetricName": "transaction",
|
||||
"MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL"
|
||||
}
|
||||
]
|
||||
|
|
@ -1,71 +1,83 @@
|
|||
[
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "0",
|
||||
"EventName": "CPU_CYCLES",
|
||||
"BriefDescription": "CPU Cycles",
|
||||
"PublicDescription": "Cycle Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "1",
|
||||
"EventName": "INSTRUCTIONS",
|
||||
"BriefDescription": "Instructions",
|
||||
"PublicDescription": "Instruction Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "2",
|
||||
"EventName": "L1I_DIR_WRITES",
|
||||
"BriefDescription": "L1I Directory Writes",
|
||||
"PublicDescription": "Level-1 I-Cache Directory Write Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "3",
|
||||
"EventName": "L1I_PENALTY_CYCLES",
|
||||
"BriefDescription": "L1I Penalty Cycles",
|
||||
"PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "4",
|
||||
"EventName": "L1D_DIR_WRITES",
|
||||
"BriefDescription": "L1D Directory Writes",
|
||||
"PublicDescription": "Level-1 D-Cache Directory Write Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "5",
|
||||
"EventName": "L1D_PENALTY_CYCLES",
|
||||
"BriefDescription": "L1D Penalty Cycles",
|
||||
"PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "32",
|
||||
"EventName": "PROBLEM_STATE_CPU_CYCLES",
|
||||
"BriefDescription": "Problem-State CPU Cycles",
|
||||
"PublicDescription": "Problem-State Cycle Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "33",
|
||||
"EventName": "PROBLEM_STATE_INSTRUCTIONS",
|
||||
"BriefDescription": "Problem-State Instructions",
|
||||
"PublicDescription": "Problem-State Instruction Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "34",
|
||||
"EventName": "PROBLEM_STATE_L1I_DIR_WRITES",
|
||||
"BriefDescription": "Problem-State L1I Directory Writes",
|
||||
"PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "35",
|
||||
"EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES",
|
||||
"BriefDescription": "Problem-State L1I Penalty Cycles",
|
||||
"PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "36",
|
||||
"EventName": "PROBLEM_STATE_L1D_DIR_WRITES",
|
||||
"BriefDescription": "Problem-State L1D Directory Writes",
|
||||
"PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "37",
|
||||
"EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES",
|
||||
"BriefDescription": "Problem-State L1D Penalty Cycles",
|
||||
|
|
|
|||
|
|
@ -1,95 +1,111 @@
|
|||
[
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "64",
|
||||
"EventName": "PRNG_FUNCTIONS",
|
||||
"BriefDescription": "PRNG Functions",
|
||||
"PublicDescription": "Total number of the PRNG functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "65",
|
||||
"EventName": "PRNG_CYCLES",
|
||||
"BriefDescription": "PRNG Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "66",
|
||||
"EventName": "PRNG_BLOCKED_FUNCTIONS",
|
||||
"BriefDescription": "PRNG Blocked Functions",
|
||||
"PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "67",
|
||||
"EventName": "PRNG_BLOCKED_CYCLES",
|
||||
"BriefDescription": "PRNG Blocked Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "68",
|
||||
"EventName": "SHA_FUNCTIONS",
|
||||
"BriefDescription": "SHA Functions",
|
||||
"PublicDescription": "Total number of SHA functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "69",
|
||||
"EventName": "SHA_CYCLES",
|
||||
"BriefDescription": "SHA Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "70",
|
||||
"EventName": "SHA_BLOCKED_FUNCTIONS",
|
||||
"BriefDescription": "SHA Blocked Functions",
|
||||
"PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "71",
|
||||
"EventName": "SHA_BLOCKED_CYCLES",
|
||||
"BriefDescription": "SHA Bloced Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "72",
|
||||
"EventName": "DEA_FUNCTIONS",
|
||||
"BriefDescription": "DEA Functions",
|
||||
"PublicDescription": "Total number of the DEA functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "73",
|
||||
"EventName": "DEA_CYCLES",
|
||||
"BriefDescription": "DEA Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "74",
|
||||
"EventName": "DEA_BLOCKED_FUNCTIONS",
|
||||
"BriefDescription": "DEA Blocked Functions",
|
||||
"PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "75",
|
||||
"EventName": "DEA_BLOCKED_CYCLES",
|
||||
"BriefDescription": "DEA Blocked Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "76",
|
||||
"EventName": "AES_FUNCTIONS",
|
||||
"BriefDescription": "AES Functions",
|
||||
"PublicDescription": "Total number of AES functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "77",
|
||||
"EventName": "AES_CYCLES",
|
||||
"BriefDescription": "AES Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "78",
|
||||
"EventName": "AES_BLOCKED_FUNCTIONS",
|
||||
"BriefDescription": "AES Blocked Functions",
|
||||
"PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "79",
|
||||
"EventName": "AES_BLOCKED_CYCLES",
|
||||
"BriefDescription": "AES Blocked Cycles",
|
||||
|
|
|
|||
|
|
@ -1,143 +1,167 @@
|
|||
[
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "128",
|
||||
"EventName": "L1D_L2_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D L2 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from the Level-2 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "129",
|
||||
"EventName": "L1I_L2_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I L2 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from the Level-2 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "130",
|
||||
"EventName": "DTLB1_MISSES",
|
||||
"BriefDescription": "DTLB1 Misses",
|
||||
"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB1 miss is in progress."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "131",
|
||||
"EventName": "ITLB1_MISSES",
|
||||
"BriefDescription": "ITLB1 Misses",
|
||||
"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle a ITLB1 miss is in progress."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "133",
|
||||
"EventName": "L2C_STORES_SENT",
|
||||
"BriefDescription": "L2C Stores Sent",
|
||||
"PublicDescription": "Incremented by one for every store sent to Level-2 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "134",
|
||||
"EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D Off-Book L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an Off Book Level-3 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "135",
|
||||
"EventName": "L1D_ONBOOK_L4_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D On-Book L4 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an On Book Level-4 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "136",
|
||||
"EventName": "L1I_ONBOOK_L4_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I On-Book L4 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an On Book Level-4 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "137",
|
||||
"EventName": "L1D_RO_EXCL_WRITES",
|
||||
"BriefDescription": "L1D Read-only Exclusive Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "138",
|
||||
"EventName": "L1D_OFFBOOK_L4_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D Off-Book L4 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an Off Book Level-4 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "139",
|
||||
"EventName": "L1I_OFFBOOK_L4_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I Off-Book L4 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an Off Book Level-4 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "140",
|
||||
"EventName": "DTLB1_HPAGE_WRITES",
|
||||
"BriefDescription": "DTLB1 One-Megabyte Page Writes",
|
||||
"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "141",
|
||||
"EventName": "L1D_LMEM_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D Local Memory Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 D-Cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "142",
|
||||
"EventName": "L1I_LMEM_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I Local Memory Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 I-Cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "143",
|
||||
"EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I Off-Book L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an Off Book Level-3 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "144",
|
||||
"EventName": "DTLB1_WRITES",
|
||||
"BriefDescription": "DTLB1 Writes",
|
||||
"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "145",
|
||||
"EventName": "ITLB1_WRITES",
|
||||
"BriefDescription": "ITLB1 Writes",
|
||||
"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "146",
|
||||
"EventName": "TLB2_PTE_WRITES",
|
||||
"BriefDescription": "TLB2 PTE Writes",
|
||||
"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "147",
|
||||
"EventName": "TLB2_CRSTE_HPAGE_WRITES",
|
||||
"BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
|
||||
"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "148",
|
||||
"EventName": "TLB2_CRSTE_WRITES",
|
||||
"BriefDescription": "TLB2 CRSTE Writes",
|
||||
"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "150",
|
||||
"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D On-Chip L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an On Chip Level-3 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "152",
|
||||
"EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D Off-Chip L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "153",
|
||||
"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I On-Chip L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an On Chip Level-3 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "155",
|
||||
"EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I Off-Chip L3 Sourced Writes",
|
||||
|
|
|
|||
|
|
@ -1,71 +1,83 @@
|
|||
[
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "0",
|
||||
"EventName": "CPU_CYCLES",
|
||||
"BriefDescription": "CPU Cycles",
|
||||
"PublicDescription": "Cycle Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "1",
|
||||
"EventName": "INSTRUCTIONS",
|
||||
"BriefDescription": "Instructions",
|
||||
"PublicDescription": "Instruction Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "2",
|
||||
"EventName": "L1I_DIR_WRITES",
|
||||
"BriefDescription": "L1I Directory Writes",
|
||||
"PublicDescription": "Level-1 I-Cache Directory Write Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "3",
|
||||
"EventName": "L1I_PENALTY_CYCLES",
|
||||
"BriefDescription": "L1I Penalty Cycles",
|
||||
"PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "4",
|
||||
"EventName": "L1D_DIR_WRITES",
|
||||
"BriefDescription": "L1D Directory Writes",
|
||||
"PublicDescription": "Level-1 D-Cache Directory Write Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "5",
|
||||
"EventName": "L1D_PENALTY_CYCLES",
|
||||
"BriefDescription": "L1D Penalty Cycles",
|
||||
"PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "32",
|
||||
"EventName": "PROBLEM_STATE_CPU_CYCLES",
|
||||
"BriefDescription": "Problem-State CPU Cycles",
|
||||
"PublicDescription": "Problem-State Cycle Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "33",
|
||||
"EventName": "PROBLEM_STATE_INSTRUCTIONS",
|
||||
"BriefDescription": "Problem-State Instructions",
|
||||
"PublicDescription": "Problem-State Instruction Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "34",
|
||||
"EventName": "PROBLEM_STATE_L1I_DIR_WRITES",
|
||||
"BriefDescription": "Problem-State L1I Directory Writes",
|
||||
"PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "35",
|
||||
"EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES",
|
||||
"BriefDescription": "Problem-State L1I Penalty Cycles",
|
||||
"PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "36",
|
||||
"EventName": "PROBLEM_STATE_L1D_DIR_WRITES",
|
||||
"BriefDescription": "Problem-State L1D Directory Writes",
|
||||
"PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "37",
|
||||
"EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES",
|
||||
"BriefDescription": "Problem-State L1D Penalty Cycles",
|
||||
|
|
|
|||
|
|
@ -1,95 +1,111 @@
|
|||
[
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "64",
|
||||
"EventName": "PRNG_FUNCTIONS",
|
||||
"BriefDescription": "PRNG Functions",
|
||||
"PublicDescription": "Total number of the PRNG functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "65",
|
||||
"EventName": "PRNG_CYCLES",
|
||||
"BriefDescription": "PRNG Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "66",
|
||||
"EventName": "PRNG_BLOCKED_FUNCTIONS",
|
||||
"BriefDescription": "PRNG Blocked Functions",
|
||||
"PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "67",
|
||||
"EventName": "PRNG_BLOCKED_CYCLES",
|
||||
"BriefDescription": "PRNG Blocked Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "68",
|
||||
"EventName": "SHA_FUNCTIONS",
|
||||
"BriefDescription": "SHA Functions",
|
||||
"PublicDescription": "Total number of SHA functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "69",
|
||||
"EventName": "SHA_CYCLES",
|
||||
"BriefDescription": "SHA Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "70",
|
||||
"EventName": "SHA_BLOCKED_FUNCTIONS",
|
||||
"BriefDescription": "SHA Blocked Functions",
|
||||
"PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "71",
|
||||
"EventName": "SHA_BLOCKED_CYCLES",
|
||||
"BriefDescription": "SHA Bloced Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "72",
|
||||
"EventName": "DEA_FUNCTIONS",
|
||||
"BriefDescription": "DEA Functions",
|
||||
"PublicDescription": "Total number of the DEA functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "73",
|
||||
"EventName": "DEA_CYCLES",
|
||||
"BriefDescription": "DEA Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "74",
|
||||
"EventName": "DEA_BLOCKED_FUNCTIONS",
|
||||
"BriefDescription": "DEA Blocked Functions",
|
||||
"PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "75",
|
||||
"EventName": "DEA_BLOCKED_CYCLES",
|
||||
"BriefDescription": "DEA Blocked Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "76",
|
||||
"EventName": "AES_FUNCTIONS",
|
||||
"BriefDescription": "AES Functions",
|
||||
"PublicDescription": "Total number of AES functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "77",
|
||||
"EventName": "AES_CYCLES",
|
||||
"BriefDescription": "AES Cycles",
|
||||
"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "78",
|
||||
"EventName": "AES_BLOCKED_FUNCTIONS",
|
||||
"BriefDescription": "AES Blocked Functions",
|
||||
"PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "79",
|
||||
"EventName": "AES_BLOCKED_CYCLES",
|
||||
"BriefDescription": "AES Blocked Cycles",
|
||||
|
|
|
|||
|
|
@ -1,209 +1,244 @@
|
|||
[
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "128",
|
||||
"EventName": "DTLB1_MISSES",
|
||||
"BriefDescription": "DTLB1 Misses",
|
||||
"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB1 miss is in progress."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "129",
|
||||
"EventName": "ITLB1_MISSES",
|
||||
"BriefDescription": "ITLB1 Misses",
|
||||
"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle a ITLB1 miss is in progress."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "130",
|
||||
"EventName": "L1D_L2I_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D L2I Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "131",
|
||||
"EventName": "L1I_L2I_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I L2I Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "132",
|
||||
"EventName": "L1D_L2D_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D L2D Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "133",
|
||||
"EventName": "DTLB1_WRITES",
|
||||
"BriefDescription": "DTLB1 Writes",
|
||||
"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "135",
|
||||
"EventName": "L1D_LMEM_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D Local Memory Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "137",
|
||||
"EventName": "L1I_LMEM_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I Local Memory Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "138",
|
||||
"EventName": "L1D_RO_EXCL_WRITES",
|
||||
"BriefDescription": "L1D Read-only Exclusive Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "139",
|
||||
"EventName": "DTLB1_HPAGE_WRITES",
|
||||
"BriefDescription": "DTLB1 One-Megabyte Page Writes",
|
||||
"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "140",
|
||||
"EventName": "ITLB1_WRITES",
|
||||
"BriefDescription": "ITLB1 Writes",
|
||||
"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "141",
|
||||
"EventName": "TLB2_PTE_WRITES",
|
||||
"BriefDescription": "TLB2 PTE Writes",
|
||||
"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "142",
|
||||
"EventName": "TLB2_CRSTE_HPAGE_WRITES",
|
||||
"BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
|
||||
"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "143",
|
||||
"EventName": "TLB2_CRSTE_WRITES",
|
||||
"BriefDescription": "TLB2 CRSTE Writes",
|
||||
"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "144",
|
||||
"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D On-Chip L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "145",
|
||||
"EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D Off-Chip L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "146",
|
||||
"EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D Off-Book L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "147",
|
||||
"EventName": "L1D_ONBOOK_L4_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D On-Book L4 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Book Level-4 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "148",
|
||||
"EventName": "L1D_OFFBOOK_L4_SOURCED_WRITES",
|
||||
"BriefDescription": "L1D Off-Book L4 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-4 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "149",
|
||||
"EventName": "TX_NC_TEND",
|
||||
"BriefDescription": "Completed TEND instructions in non-constrained TX mode",
|
||||
"PublicDescription": "A TEND instruction has completed in a nonconstrained transactional-execution mode"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "150",
|
||||
"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV",
|
||||
"BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from a On Chip Level-3 cache with intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "151",
|
||||
"EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES_IV",
|
||||
"BriefDescription": "L1D Off-Chip L3 Sourced Writes with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "152",
|
||||
"EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES_IV",
|
||||
"BriefDescription": "L1D Off-Book L3 Sourced Writes with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "153",
|
||||
"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I On-Chip L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "154",
|
||||
"EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I Off-Chip L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "155",
|
||||
"EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I Off-Book L3 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "156",
|
||||
"EventName": "L1I_ONBOOK_L4_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I On-Book L4 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Book Level-4 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "157",
|
||||
"EventName": "L1I_OFFBOOK_L4_SOURCED_WRITES",
|
||||
"BriefDescription": "L1I Off-Book L4 Sourced Writes",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-4 cache"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "158",
|
||||
"EventName": "TX_C_TEND",
|
||||
"BriefDescription": "Completed TEND instructions in constrained TX mode",
|
||||
"PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "159",
|
||||
"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV",
|
||||
"BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "160",
|
||||
"EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES_IV",
|
||||
"BriefDescription": "L1I Off-Chip L3 Sourced Writes with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "161",
|
||||
"EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES_IV",
|
||||
"BriefDescription": "L1I Off-Book L3 Sourced Writes with Intervention",
|
||||
"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "177",
|
||||
"EventName": "TX_NC_TABORT",
|
||||
"BriefDescription": "Aborted transactions in non-constrained TX mode",
|
||||
"PublicDescription": "A transaction abort has occurred in a nonconstrained transactional-execution mode"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "178",
|
||||
"EventName": "TX_C_TABORT_NO_SPECIAL",
|
||||
"BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic",
|
||||
"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete"
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "179",
|
||||
"EventName": "TX_C_TABORT_SPECIAL",
|
||||
"BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
|
||||
|
|
|
|||
|
|
@ -0,0 +1,7 @@
|
|||
[
|
||||
{
|
||||
"BriefDescription": "Transaction count",
|
||||
"MetricName": "transaction",
|
||||
"MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL"
|
||||
}
|
||||
]
|
||||
|
|
@ -233,6 +233,8 @@ static struct map {
|
|||
{ "QPI LL", "uncore_qpi" },
|
||||
{ "SBO", "uncore_sbox" },
|
||||
{ "iMPH-U", "uncore_arb" },
|
||||
{ "CPU-M-CF", "cpum_cf" },
|
||||
{ "CPU-M-SF", "cpum_sf" },
|
||||
{}
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -599,7 +599,7 @@ static int __cmd_test(int argc, const char *argv[], struct intlist *skiplist)
|
|||
for (subi = 0; subi < subn; subi++) {
|
||||
pr_info("%2d.%1d: %-*s:", i, subi + 1, subw,
|
||||
t->subtest.get_desc(subi));
|
||||
err = test_and_print(t, skip, subi);
|
||||
err = test_and_print(t, skip, subi + 1);
|
||||
if (err != TEST_OK && t->subtest.skip_if_fail)
|
||||
skip = true;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1322,6 +1322,14 @@ static int test__intel_pt(struct perf_evlist *evlist)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int test__checkevent_complex_name(struct perf_evlist *evlist)
|
||||
{
|
||||
struct perf_evsel *evsel = perf_evlist__first(evlist);
|
||||
|
||||
TEST_ASSERT_VAL("wrong complex name parsing", strcmp(evsel->name, "COMPLEX_CYCLES_NAME:orig=cycles,desc=chip-clock-ticks") == 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int count_tracepoints(void)
|
||||
{
|
||||
struct dirent *events_ent;
|
||||
|
|
@ -1658,6 +1666,11 @@ static struct evlist_test test__events[] = {
|
|||
.check = test__intel_pt,
|
||||
.id = 52,
|
||||
},
|
||||
{
|
||||
.name = "cycles/name='COMPLEX_CYCLES_NAME:orig=cycles,desc=chip-clock-ticks'/Duk",
|
||||
.check = test__checkevent_complex_name,
|
||||
.id = 53
|
||||
}
|
||||
};
|
||||
|
||||
static struct evlist_test test__events_pmu[] = {
|
||||
|
|
@ -1676,6 +1689,11 @@ static struct evlist_test test__events_pmu[] = {
|
|||
.check = test__checkevent_pmu_partial_time_callgraph,
|
||||
.id = 2,
|
||||
},
|
||||
{
|
||||
.name = "cpu/name='COMPLEX_CYCLES_NAME:orig=cycles,desc=chip-clock-ticks',period=0x1,event=0x2,umask=0x3/ukp",
|
||||
.check = test__checkevent_complex_name,
|
||||
.id = 3,
|
||||
}
|
||||
};
|
||||
|
||||
struct terms_test {
|
||||
|
|
|
|||
|
|
@ -13,11 +13,24 @@
|
|||
libc=$(grep -w libc /proc/self/maps | head -1 | sed -r 's/.*[[:space:]](\/.*)/\1/g')
|
||||
nm -Dg $libc 2>/dev/null | fgrep -q inet_pton || exit 254
|
||||
|
||||
event_pattern='probe_libc:inet_pton(\_[[:digit:]]+)?'
|
||||
|
||||
add_libc_inet_pton_event() {
|
||||
|
||||
event_name=$(perf probe -f -x $libc -a inet_pton 2>&1 | tail -n +2 | head -n -5 | \
|
||||
grep -P -o "$event_pattern(?=[[:space:]]\(on inet_pton in $libc\))")
|
||||
|
||||
if [ $? -ne 0 -o -z "$event_name" ] ; then
|
||||
printf "FAIL: could not add event\n"
|
||||
return 1
|
||||
fi
|
||||
}
|
||||
|
||||
trace_libc_inet_pton_backtrace() {
|
||||
|
||||
expected=`mktemp -u /tmp/expected.XXX`
|
||||
|
||||
echo "ping[][0-9 \.:]+probe_libc:inet_pton: \([[:xdigit:]]+\)" > $expected
|
||||
echo "ping[][0-9 \.:]+$event_name: \([[:xdigit:]]+\)" > $expected
|
||||
echo ".*inet_pton\+0x[[:xdigit:]]+[[:space:]]\($libc|inlined\)$" >> $expected
|
||||
case "$(uname -m)" in
|
||||
s390x)
|
||||
|
|
@ -26,6 +39,12 @@ trace_libc_inet_pton_backtrace() {
|
|||
echo "(__GI_)?getaddrinfo\+0x[[:xdigit:]]+[[:space:]]\($libc|inlined\)$" >> $expected
|
||||
echo "main\+0x[[:xdigit:]]+[[:space:]]\(.*/bin/ping.*\)$" >> $expected
|
||||
;;
|
||||
ppc64|ppc64le)
|
||||
eventattr='max-stack=4'
|
||||
echo "gaih_inet.*\+0x[[:xdigit:]]+[[:space:]]\($libc\)$" >> $expected
|
||||
echo "getaddrinfo\+0x[[:xdigit:]]+[[:space:]]\($libc\)$" >> $expected
|
||||
echo ".*\+0x[[:xdigit:]]+[[:space:]]\(.*/bin/ping.*\)$" >> $expected
|
||||
;;
|
||||
*)
|
||||
eventattr='max-stack=3'
|
||||
echo "getaddrinfo\+0x[[:xdigit:]]+[[:space:]]\($libc\)$" >> $expected
|
||||
|
|
@ -35,7 +54,7 @@ trace_libc_inet_pton_backtrace() {
|
|||
|
||||
perf_data=`mktemp -u /tmp/perf.data.XXX`
|
||||
perf_script=`mktemp -u /tmp/perf.script.XXX`
|
||||
perf record -e probe_libc:inet_pton/$eventattr/ -o $perf_data ping -6 -c 1 ::1 > /dev/null 2>&1
|
||||
perf record -e $event_name/$eventattr/ -o $perf_data ping -6 -c 1 ::1 > /dev/null 2>&1
|
||||
perf script -i $perf_data > $perf_script
|
||||
|
||||
exec 3<$perf_script
|
||||
|
|
@ -46,7 +65,7 @@ trace_libc_inet_pton_backtrace() {
|
|||
echo "$line" | egrep -q "$pattern"
|
||||
if [ $? -ne 0 ] ; then
|
||||
printf "FAIL: expected backtrace entry \"%s\" got \"%s\"\n" "$pattern" "$line"
|
||||
exit 1
|
||||
return 1
|
||||
fi
|
||||
done
|
||||
|
||||
|
|
@ -56,13 +75,20 @@ trace_libc_inet_pton_backtrace() {
|
|||
# even if the perf script output does not match.
|
||||
}
|
||||
|
||||
delete_libc_inet_pton_event() {
|
||||
|
||||
if [ -n "$event_name" ] ; then
|
||||
perf probe -q -d $event_name
|
||||
fi
|
||||
}
|
||||
|
||||
# Check for IPv6 interface existence
|
||||
ip a sh lo | fgrep -q inet6 || exit 2
|
||||
|
||||
skip_if_no_perf_probe && \
|
||||
perf probe -q $libc inet_pton && \
|
||||
add_libc_inet_pton_event && \
|
||||
trace_libc_inet_pton_backtrace
|
||||
err=$?
|
||||
rm -f ${perf_data} ${perf_script} ${expected}
|
||||
perf probe -q -d probe_libc:inet_pton
|
||||
delete_libc_inet_pton_event
|
||||
exit $err
|
||||
|
|
|
|||
|
|
@ -529,7 +529,7 @@ out:
|
|||
|
||||
static int hist_entry__fprintf(struct hist_entry *he, size_t size,
|
||||
char *bf, size_t bfsz, FILE *fp,
|
||||
bool use_callchain)
|
||||
bool ignore_callchains)
|
||||
{
|
||||
int ret;
|
||||
int callchain_ret = 0;
|
||||
|
|
@ -550,7 +550,7 @@ static int hist_entry__fprintf(struct hist_entry *he, size_t size,
|
|||
|
||||
ret = fprintf(fp, "%s\n", bf);
|
||||
|
||||
if (hist_entry__has_callchains(he) && use_callchain)
|
||||
if (hist_entry__has_callchains(he) && !ignore_callchains)
|
||||
callchain_ret = hist_entry_callchain__fprintf(he, total_period,
|
||||
0, fp);
|
||||
|
||||
|
|
@ -755,7 +755,7 @@ int hists__fprintf_headers(struct hists *hists, FILE *fp)
|
|||
|
||||
size_t hists__fprintf(struct hists *hists, bool show_header, int max_rows,
|
||||
int max_cols, float min_pcnt, FILE *fp,
|
||||
bool use_callchain)
|
||||
bool ignore_callchains)
|
||||
{
|
||||
struct rb_node *nd;
|
||||
size_t ret = 0;
|
||||
|
|
@ -799,7 +799,7 @@ size_t hists__fprintf(struct hists *hists, bool show_header, int max_rows,
|
|||
if (percent < min_pcnt)
|
||||
continue;
|
||||
|
||||
ret += hist_entry__fprintf(h, max_cols, line, linesz, fp, use_callchain);
|
||||
ret += hist_entry__fprintf(h, max_cols, line, linesz, fp, ignore_callchains);
|
||||
|
||||
if (max_rows && ++nr_rows >= max_rows)
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -20,9 +20,10 @@ static struct rw_semaphore comm_str_lock = {.lock = PTHREAD_RWLOCK_INITIALIZER,}
|
|||
|
||||
static struct comm_str *comm_str__get(struct comm_str *cs)
|
||||
{
|
||||
if (cs)
|
||||
refcount_inc(&cs->refcnt);
|
||||
return cs;
|
||||
if (cs && refcount_inc_not_zero(&cs->refcnt))
|
||||
return cs;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void comm_str__put(struct comm_str *cs)
|
||||
|
|
@ -67,9 +68,14 @@ struct comm_str *__comm_str__findnew(const char *str, struct rb_root *root)
|
|||
parent = *p;
|
||||
iter = rb_entry(parent, struct comm_str, rb_node);
|
||||
|
||||
/*
|
||||
* If we race with comm_str__put, iter->refcnt is 0
|
||||
* and it will be removed within comm_str__put call
|
||||
* shortly, ignore it in this search.
|
||||
*/
|
||||
cmp = strcmp(str, iter->str);
|
||||
if (!cmp)
|
||||
return comm_str__get(iter);
|
||||
if (!cmp && comm_str__get(iter))
|
||||
return iter;
|
||||
|
||||
if (cmp < 0)
|
||||
p = &(*p)->rb_left;
|
||||
|
|
|
|||
|
|
@ -31,6 +31,8 @@
|
|||
#endif
|
||||
#endif
|
||||
|
||||
#define CS_ETM_INVAL_ADDR 0xdeadbeefdeadbeefUL
|
||||
|
||||
struct cs_etm_decoder {
|
||||
void *data;
|
||||
void (*packet_printer)(const char *msg);
|
||||
|
|
@ -261,8 +263,8 @@ static void cs_etm_decoder__clear_buffer(struct cs_etm_decoder *decoder)
|
|||
decoder->tail = 0;
|
||||
decoder->packet_count = 0;
|
||||
for (i = 0; i < MAX_BUFFER; i++) {
|
||||
decoder->packet_buffer[i].start_addr = 0xdeadbeefdeadbeefUL;
|
||||
decoder->packet_buffer[i].end_addr = 0xdeadbeefdeadbeefUL;
|
||||
decoder->packet_buffer[i].start_addr = CS_ETM_INVAL_ADDR;
|
||||
decoder->packet_buffer[i].end_addr = CS_ETM_INVAL_ADDR;
|
||||
decoder->packet_buffer[i].last_instr_taken_branch = false;
|
||||
decoder->packet_buffer[i].exc = false;
|
||||
decoder->packet_buffer[i].exc_ret = false;
|
||||
|
|
@ -295,8 +297,8 @@ cs_etm_decoder__buffer_packet(struct cs_etm_decoder *decoder,
|
|||
decoder->packet_buffer[et].exc = false;
|
||||
decoder->packet_buffer[et].exc_ret = false;
|
||||
decoder->packet_buffer[et].cpu = *((int *)inode->priv);
|
||||
decoder->packet_buffer[et].start_addr = 0xdeadbeefdeadbeefUL;
|
||||
decoder->packet_buffer[et].end_addr = 0xdeadbeefdeadbeefUL;
|
||||
decoder->packet_buffer[et].start_addr = CS_ETM_INVAL_ADDR;
|
||||
decoder->packet_buffer[et].end_addr = CS_ETM_INVAL_ADDR;
|
||||
|
||||
if (decoder->packet_count == MAX_BUFFER - 1)
|
||||
return OCSD_RESP_WAIT;
|
||||
|
|
|
|||
|
|
@ -939,6 +939,9 @@ static int cs_etm__flush(struct cs_etm_queue *etmq)
|
|||
err = cs_etm__synth_instruction_sample(
|
||||
etmq, addr,
|
||||
etmq->period_instructions);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
etmq->period_instructions = 0;
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -260,6 +260,17 @@ struct perf_evsel *perf_evsel__new_idx(struct perf_event_attr *attr, int idx)
|
|||
evsel->attr.sample_period = 1;
|
||||
}
|
||||
|
||||
if (perf_evsel__is_clock(evsel)) {
|
||||
/*
|
||||
* The evsel->unit points to static alias->unit
|
||||
* so it's ok to use static string in here.
|
||||
*/
|
||||
static const char *unit = "msec";
|
||||
|
||||
evsel->unit = unit;
|
||||
evsel->scale = 1e-6;
|
||||
}
|
||||
|
||||
return evsel;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -402,10 +402,13 @@ bool perf_evsel__is_function_event(struct perf_evsel *evsel);
|
|||
|
||||
static inline bool perf_evsel__is_bpf_output(struct perf_evsel *evsel)
|
||||
{
|
||||
struct perf_event_attr *attr = &evsel->attr;
|
||||
return perf_evsel__match(evsel, SOFTWARE, SW_BPF_OUTPUT);
|
||||
}
|
||||
|
||||
return (attr->config == PERF_COUNT_SW_BPF_OUTPUT) &&
|
||||
(attr->type == PERF_TYPE_SOFTWARE);
|
||||
static inline bool perf_evsel__is_clock(struct perf_evsel *evsel)
|
||||
{
|
||||
return perf_evsel__match(evsel, SOFTWARE, SW_CPU_CLOCK) ||
|
||||
perf_evsel__match(evsel, SOFTWARE, SW_TASK_CLOCK);
|
||||
}
|
||||
|
||||
struct perf_attr_details {
|
||||
|
|
|
|||
|
|
@ -2587,7 +2587,7 @@ static const struct feature_ops feat_ops[HEADER_LAST_FEATURE] = {
|
|||
FEAT_OPR(NUMA_TOPOLOGY, numa_topology, true),
|
||||
FEAT_OPN(BRANCH_STACK, branch_stack, false),
|
||||
FEAT_OPR(PMU_MAPPINGS, pmu_mappings, false),
|
||||
FEAT_OPN(GROUP_DESC, group_desc, false),
|
||||
FEAT_OPR(GROUP_DESC, group_desc, false),
|
||||
FEAT_OPN(AUXTRACE, auxtrace, false),
|
||||
FEAT_OPN(STAT, stat, false),
|
||||
FEAT_OPN(CACHE, cache, true),
|
||||
|
|
|
|||
|
|
@ -181,7 +181,7 @@ size_t events_stats__fprintf(struct events_stats *stats, FILE *fp);
|
|||
|
||||
size_t hists__fprintf(struct hists *hists, bool show_header, int max_rows,
|
||||
int max_cols, float min_pcnt, FILE *fp,
|
||||
bool use_callchain);
|
||||
bool ignore_callchains);
|
||||
size_t perf_evlist__fprintf_nr_events(struct perf_evlist *evlist, FILE *fp);
|
||||
|
||||
void hists__filter_by_dso(struct hists *hists);
|
||||
|
|
|
|||
|
|
@ -407,6 +407,55 @@ out_err:
|
|||
goto out_put;
|
||||
}
|
||||
|
||||
/*
|
||||
* Front-end cache - TID lookups come in blocks,
|
||||
* so most of the time we dont have to look up
|
||||
* the full rbtree:
|
||||
*/
|
||||
static struct thread*
|
||||
__threads__get_last_match(struct threads *threads, struct machine *machine,
|
||||
int pid, int tid)
|
||||
{
|
||||
struct thread *th;
|
||||
|
||||
th = threads->last_match;
|
||||
if (th != NULL) {
|
||||
if (th->tid == tid) {
|
||||
machine__update_thread_pid(machine, th, pid);
|
||||
return thread__get(th);
|
||||
}
|
||||
|
||||
threads->last_match = NULL;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static struct thread*
|
||||
threads__get_last_match(struct threads *threads, struct machine *machine,
|
||||
int pid, int tid)
|
||||
{
|
||||
struct thread *th = NULL;
|
||||
|
||||
if (perf_singlethreaded)
|
||||
th = __threads__get_last_match(threads, machine, pid, tid);
|
||||
|
||||
return th;
|
||||
}
|
||||
|
||||
static void
|
||||
__threads__set_last_match(struct threads *threads, struct thread *th)
|
||||
{
|
||||
threads->last_match = th;
|
||||
}
|
||||
|
||||
static void
|
||||
threads__set_last_match(struct threads *threads, struct thread *th)
|
||||
{
|
||||
if (perf_singlethreaded)
|
||||
__threads__set_last_match(threads, th);
|
||||
}
|
||||
|
||||
/*
|
||||
* Caller must eventually drop thread->refcnt returned with a successful
|
||||
* lookup/new thread inserted.
|
||||
|
|
@ -420,27 +469,16 @@ static struct thread *____machine__findnew_thread(struct machine *machine,
|
|||
struct rb_node *parent = NULL;
|
||||
struct thread *th;
|
||||
|
||||
/*
|
||||
* Front-end cache - TID lookups come in blocks,
|
||||
* so most of the time we dont have to look up
|
||||
* the full rbtree:
|
||||
*/
|
||||
th = threads->last_match;
|
||||
if (th != NULL) {
|
||||
if (th->tid == tid) {
|
||||
machine__update_thread_pid(machine, th, pid);
|
||||
return thread__get(th);
|
||||
}
|
||||
|
||||
threads->last_match = NULL;
|
||||
}
|
||||
th = threads__get_last_match(threads, machine, pid, tid);
|
||||
if (th)
|
||||
return th;
|
||||
|
||||
while (*p != NULL) {
|
||||
parent = *p;
|
||||
th = rb_entry(parent, struct thread, rb_node);
|
||||
|
||||
if (th->tid == tid) {
|
||||
threads->last_match = th;
|
||||
threads__set_last_match(threads, th);
|
||||
machine__update_thread_pid(machine, th, pid);
|
||||
return thread__get(th);
|
||||
}
|
||||
|
|
@ -477,7 +515,7 @@ static struct thread *____machine__findnew_thread(struct machine *machine,
|
|||
* It is now in the rbtree, get a ref
|
||||
*/
|
||||
thread__get(th);
|
||||
threads->last_match = th;
|
||||
threads__set_last_match(threads, th);
|
||||
++threads->nr;
|
||||
}
|
||||
|
||||
|
|
@ -1635,7 +1673,7 @@ static void __machine__remove_thread(struct machine *machine, struct thread *th,
|
|||
struct threads *threads = machine__threads(machine, th->tid);
|
||||
|
||||
if (threads->last_match == th)
|
||||
threads->last_match = NULL;
|
||||
threads__set_last_match(threads, NULL);
|
||||
|
||||
BUG_ON(refcount_read(&th->refcnt) == 0);
|
||||
if (lock)
|
||||
|
|
@ -2272,6 +2310,7 @@ static int unwind_entry(struct unwind_entry *entry, void *arg)
|
|||
{
|
||||
struct callchain_cursor *cursor = arg;
|
||||
const char *srcline = NULL;
|
||||
u64 addr;
|
||||
|
||||
if (symbol_conf.hide_unresolved && entry->sym == NULL)
|
||||
return 0;
|
||||
|
|
@ -2279,7 +2318,13 @@ static int unwind_entry(struct unwind_entry *entry, void *arg)
|
|||
if (append_inlines(cursor, entry->map, entry->sym, entry->ip) == 0)
|
||||
return 0;
|
||||
|
||||
srcline = callchain_srcline(entry->map, entry->sym, entry->ip);
|
||||
/*
|
||||
* Convert entry->ip from a virtual address to an offset in
|
||||
* its corresponding binary.
|
||||
*/
|
||||
addr = map__map_ip(entry->map, entry->ip);
|
||||
|
||||
srcline = callchain_srcline(entry->map, entry->sym, addr);
|
||||
return callchain_cursor_append(cursor, entry->ip,
|
||||
entry->map, entry->sym,
|
||||
false, NULL, 0, 0, 0, srcline);
|
||||
|
|
|
|||
|
|
@ -490,3 +490,25 @@ out:
|
|||
metricgroup__free_egroups(&group_list);
|
||||
return ret;
|
||||
}
|
||||
|
||||
bool metricgroup__has_metric(const char *metric)
|
||||
{
|
||||
struct pmu_events_map *map = perf_pmu__find_map(NULL);
|
||||
struct pmu_event *pe;
|
||||
int i;
|
||||
|
||||
if (!map)
|
||||
return false;
|
||||
|
||||
for (i = 0; ; i++) {
|
||||
pe = &map->table[i];
|
||||
|
||||
if (!pe->name && !pe->metric_group && !pe->metric_name)
|
||||
break;
|
||||
if (!pe->metric_expr)
|
||||
continue;
|
||||
if (match_metric(pe->metric_name, metric))
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -28,4 +28,5 @@ int metricgroup__parse_groups(const struct option *opt,
|
|||
struct rblist *metric_events);
|
||||
|
||||
void metricgroup__print(bool metrics, bool groups, char *filter, bool raw);
|
||||
bool metricgroup__has_metric(const char *metric);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -652,12 +652,6 @@ static int is_arm_pmu_core(const char *name)
|
|||
if (stat(path, &st) == 0)
|
||||
return 1;
|
||||
|
||||
/* Look for cpu sysfs (specific to s390) */
|
||||
scnprintf(path, PATH_MAX, "%s/bus/event_source/devices/%s",
|
||||
sysfs, name);
|
||||
if (stat(path, &st) == 0 && !strncmp(name, "cpum_", 5))
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -913,11 +913,10 @@ void perf_stat__print_shadow_stats(struct perf_evsel *evsel,
|
|||
ratio = total / avg;
|
||||
|
||||
print_metric(ctxp, NULL, "%8.0f", "cycles / elision", ratio);
|
||||
} else if (perf_evsel__match(evsel, SOFTWARE, SW_TASK_CLOCK) ||
|
||||
perf_evsel__match(evsel, SOFTWARE, SW_CPU_CLOCK)) {
|
||||
} else if (perf_evsel__is_clock(evsel)) {
|
||||
if ((ratio = avg_stats(&walltime_nsecs_stats)) != 0)
|
||||
print_metric(ctxp, NULL, "%8.3f", "CPUs utilized",
|
||||
avg / ratio);
|
||||
avg / (ratio * evsel->scale));
|
||||
else
|
||||
print_metric(ctxp, NULL, NULL, "CPUs utilized", 0);
|
||||
} else if (perf_stat_evsel__is(evsel, TOPDOWN_FETCH_BUBBLES)) {
|
||||
|
|
|
|||
|
|
@ -38,6 +38,10 @@ static const char **syscalltbl_native = syscalltbl_powerpc_64;
|
|||
#include <asm/syscalls_32.c>
|
||||
const int syscalltbl_native_max_id = SYSCALLTBL_POWERPC_32_MAX_ID;
|
||||
static const char **syscalltbl_native = syscalltbl_powerpc_32;
|
||||
#elif defined(__aarch64__)
|
||||
#include <asm/syscalls.c>
|
||||
const int syscalltbl_native_max_id = SYSCALLTBL_ARM64_MAX_ID;
|
||||
static const char **syscalltbl_native = syscalltbl_arm64;
|
||||
#endif
|
||||
|
||||
struct syscall {
|
||||
|
|
|
|||
|
|
@ -77,7 +77,7 @@ static int entry(u64 ip, struct unwind_info *ui)
|
|||
if (__report_module(&al, ip, ui))
|
||||
return -1;
|
||||
|
||||
e->ip = al.addr;
|
||||
e->ip = ip;
|
||||
e->map = al.map;
|
||||
e->sym = al.sym;
|
||||
|
||||
|
|
|
|||
|
|
@ -575,7 +575,7 @@ static int entry(u64 ip, struct thread *thread,
|
|||
struct addr_location al;
|
||||
|
||||
e.sym = thread__find_symbol(thread, PERF_RECORD_MISC_USER, ip, &al);
|
||||
e.ip = al.addr;
|
||||
e.ip = ip;
|
||||
e.map = al.map;
|
||||
|
||||
pr_debug("unwind: %s:ip = 0x%" PRIx64 " (0x%" PRIx64 ")\n",
|
||||
|
|
|
|||
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