drm/nouveau/sec: namespace + nvidia gpu names (no binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
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Коммит
25a6402557
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@ -1,4 +1,5 @@
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#ifndef __NVKM_SEC_H__
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#define __NVKM_SEC_H__
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extern struct nouveau_oclass nv98_sec_oclass;
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#include <core/engine.h>
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extern struct nvkm_oclass g98_sec_oclass;
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#endif
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@ -255,7 +255,7 @@ nv50_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
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device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
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device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
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device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass;
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device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
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device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
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@ -313,7 +313,7 @@ nv50_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
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device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
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device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
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device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass;
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device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
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device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
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@ -342,7 +342,7 @@ nv50_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
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device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
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device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
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device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass;
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device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
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device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
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@ -1 +1 @@
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nvkm-y += nvkm/engine/sec/nv98.o
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nvkm-y += nvkm/engine/sec/g98.o
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@ -1,5 +1,5 @@
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/*
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* fuc microcode for nv98 psec engine
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* fuc microcode for g98 psec engine
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* Copyright (C) 2010 Marcin Kościelnicki
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*
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* This program is free software; you can redistribute it and/or modify
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@ -17,7 +17,7 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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.section #nv98_psec_data
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.section #g98_psec_data
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ctx_dma:
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ctx_dma_query: .b32 0
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@ -94,7 +94,7 @@ sec_dtable:
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.align 0x100
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.section #nv98_psec_code
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.section #g98_psec_code
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// $r0 is always set to 0 in our code - this allows some space savings.
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clear b32 $r0
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@ -1,4 +1,4 @@
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uint32_t nv98_psec_data[] = {
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uint32_t g98_psec_data[] = {
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/* 0x0000: ctx_dma */
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/* 0x0000: ctx_dma_query */
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0x00000000,
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@ -150,7 +150,7 @@ uint32_t nv98_psec_data[] = {
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0x00000000,
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};
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uint32_t nv98_psec_code[] = {
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uint32_t g98_psec_code[] = {
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0x17f004bd,
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0x0010fe35,
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0xf10004fe,
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@ -21,32 +21,25 @@
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*
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* Authors: Ben Skeggs
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*/
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#include <engine/sec.h>
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#include <engine/falcon.h>
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#include "fuc/g98.fuc0s.h"
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#include <core/client.h>
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#include <core/os.h>
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#include <core/enum.h>
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#include <core/engctx.h>
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#include <subdev/timer.h>
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#include <subdev/fb.h>
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#include <engine/falcon.h>
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#include <engine/fifo.h>
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#include <engine/sec.h>
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#include "fuc/nv98.fuc0s.h"
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struct nv98_sec_priv {
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struct nouveau_falcon base;
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struct g98_sec_priv {
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struct nvkm_falcon base;
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};
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/*******************************************************************************
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* Crypt object classes
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******************************************************************************/
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static struct nouveau_oclass
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nv98_sec_sclass[] = {
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{ 0x88b4, &nouveau_object_ofuncs },
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static struct nvkm_oclass
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g98_sec_sclass[] = {
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{ 0x88b4, &nvkm_object_ofuncs },
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{},
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};
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@ -54,16 +47,16 @@ nv98_sec_sclass[] = {
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* PSEC context
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******************************************************************************/
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static struct nouveau_oclass
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nv98_sec_cclass = {
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static struct nvkm_oclass
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g98_sec_cclass = {
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.handle = NV_ENGCTX(SEC, 0x98),
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.ofuncs = &(struct nouveau_ofuncs) {
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.ctor = _nouveau_falcon_context_ctor,
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.dtor = _nouveau_falcon_context_dtor,
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.init = _nouveau_falcon_context_init,
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.fini = _nouveau_falcon_context_fini,
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.rd32 = _nouveau_falcon_context_rd32,
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.wr32 = _nouveau_falcon_context_wr32,
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.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = _nvkm_falcon_context_ctor,
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.dtor = _nvkm_falcon_context_dtor,
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.init = _nvkm_falcon_context_init,
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.fini = _nvkm_falcon_context_fini,
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.rd32 = _nvkm_falcon_context_rd32,
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.wr32 = _nvkm_falcon_context_wr32,
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},
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};
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@ -71,7 +64,7 @@ nv98_sec_cclass = {
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* PSEC engine/subdev functions
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******************************************************************************/
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static const struct nouveau_enum nv98_sec_isr_error_name[] = {
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static const struct nvkm_enum g98_sec_isr_error_name[] = {
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{ 0x0000, "ILLEGAL_MTHD" },
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{ 0x0001, "INVALID_BITFIELD" },
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{ 0x0002, "INVALID_ENUM" },
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@ -80,12 +73,12 @@ static const struct nouveau_enum nv98_sec_isr_error_name[] = {
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};
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static void
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nv98_sec_intr(struct nouveau_subdev *subdev)
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g98_sec_intr(struct nvkm_subdev *subdev)
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{
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struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
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struct nouveau_engine *engine = nv_engine(subdev);
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struct nouveau_object *engctx;
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struct nv98_sec_priv *priv = (void *)subdev;
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struct nvkm_fifo *pfifo = nvkm_fifo(subdev);
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struct nvkm_engine *engine = nv_engine(subdev);
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struct nvkm_object *engctx;
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struct g98_sec_priv *priv = (void *)subdev;
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u32 disp = nv_rd32(priv, 0x08701c);
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u32 stat = nv_rd32(priv, 0x087008) & disp & ~(disp >> 16);
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u32 inst = nv_rd32(priv, 0x087050) & 0x3fffffff;
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@ -96,14 +89,14 @@ nv98_sec_intr(struct nouveau_subdev *subdev)
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u32 data = nv_rd32(priv, 0x087044);
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int chid;
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engctx = nouveau_engctx_get(engine, inst);
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engctx = nvkm_engctx_get(engine, inst);
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chid = pfifo->chid(pfifo, engctx);
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if (stat & 0x00000040) {
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nv_error(priv, "DISPATCH_ERROR [");
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nouveau_enum_print(nv98_sec_isr_error_name, ssta);
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nvkm_enum_print(g98_sec_isr_error_name, ssta);
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pr_cont("] ch %d [0x%010llx %s] subc %d mthd 0x%04x data 0x%08x\n",
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chid, (u64)inst << 12, nouveau_client_name(engctx),
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chid, (u64)inst << 12, nvkm_client_name(engctx),
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subc, mthd, data);
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nv_wr32(priv, 0x087004, 0x00000040);
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stat &= ~0x00000040;
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@ -114,43 +107,43 @@ nv98_sec_intr(struct nouveau_subdev *subdev)
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nv_wr32(priv, 0x087004, stat);
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}
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nouveau_engctx_put(engctx);
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nvkm_engctx_put(engctx);
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}
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static int
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nv98_sec_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 size,
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struct nouveau_object **pobject)
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g98_sec_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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{
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struct nv98_sec_priv *priv;
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struct g98_sec_priv *priv;
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int ret;
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ret = nouveau_falcon_create(parent, engine, oclass, 0x087000, true,
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"PSEC", "sec", &priv);
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ret = nvkm_falcon_create(parent, engine, oclass, 0x087000, true,
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"PSEC", "sec", &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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nv_subdev(priv)->unit = 0x00004000;
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nv_subdev(priv)->intr = nv98_sec_intr;
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nv_engine(priv)->cclass = &nv98_sec_cclass;
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nv_engine(priv)->sclass = nv98_sec_sclass;
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nv_falcon(priv)->code.data = nv98_psec_code;
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nv_falcon(priv)->code.size = sizeof(nv98_psec_code);
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nv_falcon(priv)->data.data = nv98_psec_data;
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nv_falcon(priv)->data.size = sizeof(nv98_psec_data);
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nv_subdev(priv)->intr = g98_sec_intr;
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nv_engine(priv)->cclass = &g98_sec_cclass;
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nv_engine(priv)->sclass = g98_sec_sclass;
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nv_falcon(priv)->code.data = g98_psec_code;
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nv_falcon(priv)->code.size = sizeof(g98_psec_code);
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nv_falcon(priv)->data.data = g98_psec_data;
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nv_falcon(priv)->data.size = sizeof(g98_psec_data);
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return 0;
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}
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struct nouveau_oclass
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nv98_sec_oclass = {
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struct nvkm_oclass
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g98_sec_oclass = {
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.handle = NV_ENGINE(SEC, 0x98),
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.ofuncs = &(struct nouveau_ofuncs) {
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.ctor = nv98_sec_ctor,
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.dtor = _nouveau_falcon_dtor,
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.init = _nouveau_falcon_init,
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.fini = _nouveau_falcon_fini,
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.rd32 = _nouveau_falcon_rd32,
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.wr32 = _nouveau_falcon_wr32,
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.ofuncs = &(struct nvkm_ofuncs) {
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.ctor = g98_sec_ctor,
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.dtor = _nvkm_falcon_dtor,
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.init = _nvkm_falcon_init,
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.fini = _nvkm_falcon_fini,
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.rd32 = _nvkm_falcon_rd32,
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.wr32 = _nvkm_falcon_wr32,
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},
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};
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