qed: Add basic L2 interface
This patch adds a public API for a network driver to work on top of QED. The interface itself is very minimal - it's mostly infrastructure, as the only content it has after this patch is a query for HW-based information required for the creation of a network interface [I.e., no actual protocol-specific configurations are supported]. Signed-off-by: Manish Chopra <Manish.Chopra@qlogic.com> Signed-off-by: Yuval Mintz <Yuval.Mintz@qlogic.com> Signed-off-by: Ariel Elior <Ariel.Elior@qlogic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yuval Mintz
David S. Miller
Родитель
fe56b9e6a8
Коммит
25c089d78f
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@ -1,4 +1,4 @@
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obj-$(CONFIG_QED) := qed.o
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qed-y := qed_cxt.o qed_dev.o qed_hw.o qed_init_fw_funcs.o qed_init_ops.o \
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qed_int.o qed_main.o qed_mcp.o qed_sp_commands.o qed_spq.o
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qed_int.o qed_main.o qed_mcp.o qed_sp_commands.o qed_spq.o qed_l2.o
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@ -25,6 +25,7 @@
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#include <linux/qed/qed_if.h>
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#include "qed_hsi.h"
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extern const struct qed_common_ops qed_common_ops_pass;
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#define DRV_MODULE_VERSION "8.4.0.0"
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#define MAX_HWFNS_PER_DEVICE (4)
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@ -91,13 +92,22 @@ struct qed_qm_iids {
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enum QED_RESOURCES {
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QED_SB,
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QED_L2_QUEUE,
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QED_VPORT,
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QED_RSS_ENG,
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QED_PQ,
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QED_RL,
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QED_MAC,
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QED_VLAN,
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QED_ILT,
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QED_MAX_RESC,
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};
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enum QED_FEATURE {
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QED_PF_L2_QUE,
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QED_MAX_FEATURES,
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};
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struct qed_hw_info {
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/* PCI personality */
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enum qed_pci_personality personality;
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@ -105,6 +115,7 @@ struct qed_hw_info {
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/* Resource Allocation scheme results */
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u32 resc_start[QED_MAX_RESC];
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u32 resc_num[QED_MAX_RESC];
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u32 feat_num[QED_MAX_FEATURES];
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#define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
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#define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
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@ -266,6 +277,9 @@ struct qed_hwfn {
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struct qed_mcp_info *mcp_info;
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struct qed_hw_cid_data *p_tx_cids;
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struct qed_hw_cid_data *p_rx_cids;
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struct qed_dmae_info dmae_info;
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/* QM init */
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@ -89,6 +89,15 @@ void qed_resc_free(struct qed_dev *cdev)
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kfree(cdev->reset_stats);
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for_each_hwfn(cdev, i) {
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struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
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kfree(p_hwfn->p_tx_cids);
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p_hwfn->p_tx_cids = NULL;
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kfree(p_hwfn->p_rx_cids);
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p_hwfn->p_rx_cids = NULL;
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}
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for_each_hwfn(cdev, i) {
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struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
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@ -202,6 +211,29 @@ int qed_resc_alloc(struct qed_dev *cdev)
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if (!cdev->fw_data)
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return -ENOMEM;
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/* Allocate Memory for the Queue->CID mapping */
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for_each_hwfn(cdev, i) {
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struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
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int tx_size = sizeof(struct qed_hw_cid_data) *
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RESC_NUM(p_hwfn, QED_L2_QUEUE);
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int rx_size = sizeof(struct qed_hw_cid_data) *
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RESC_NUM(p_hwfn, QED_L2_QUEUE);
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p_hwfn->p_tx_cids = kzalloc(tx_size, GFP_KERNEL);
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if (!p_hwfn->p_tx_cids) {
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DP_NOTICE(p_hwfn,
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"Failed to allocate memory for Tx Cids\n");
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goto alloc_err;
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}
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p_hwfn->p_rx_cids = kzalloc(rx_size, GFP_KERNEL);
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if (!p_hwfn->p_rx_cids) {
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DP_NOTICE(p_hwfn,
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"Failed to allocate memory for Rx Cids\n");
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goto alloc_err;
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}
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}
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for_each_hwfn(cdev, i) {
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struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
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@ -881,6 +913,20 @@ static void get_function_id(struct qed_hwfn *p_hwfn)
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PXP_CONCRETE_FID_PORT);
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}
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static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
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{
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u32 *feat_num = p_hwfn->hw_info.feat_num;
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int num_features = 1;
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feat_num[QED_PF_L2_QUE] = min_t(u32, RESC_NUM(p_hwfn, QED_SB) /
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num_features,
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RESC_NUM(p_hwfn, QED_L2_QUEUE));
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DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
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"#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n",
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feat_num[QED_PF_L2_QUE], RESC_NUM(p_hwfn, QED_SB),
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num_features);
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}
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static void qed_hw_get_resc(struct qed_hwfn *p_hwfn)
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{
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u32 *resc_start = p_hwfn->hw_info.resc_start;
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@ -893,29 +939,45 @@ static void qed_hw_get_resc(struct qed_hwfn *p_hwfn)
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resc_num[QED_SB] = min_t(u32,
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(MAX_SB_PER_PATH_BB / num_funcs),
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qed_int_get_num_sbs(p_hwfn, NULL));
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resc_num[QED_L2_QUEUE] = MAX_NUM_L2_QUEUES_BB / num_funcs;
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resc_num[QED_VPORT] = MAX_NUM_VPORTS_BB / num_funcs;
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resc_num[QED_RSS_ENG] = ETH_RSS_ENGINE_NUM_BB / num_funcs;
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resc_num[QED_PQ] = MAX_QM_TX_QUEUES_BB / num_funcs;
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resc_num[QED_RL] = 8;
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resc_num[QED_MAC] = ETH_NUM_MAC_FILTERS / num_funcs;
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resc_num[QED_VLAN] = (ETH_NUM_VLAN_FILTERS - 1 /*For vlan0*/) /
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num_funcs;
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resc_num[QED_ILT] = 950;
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for (i = 0; i < QED_MAX_RESC; i++)
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resc_start[i] = resc_num[i] * p_hwfn->rel_pf_id;
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qed_hw_set_feat(p_hwfn);
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DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE,
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"The numbers for each resource are:\n"
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"SB = %d start = %d\n"
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"L2_QUEUE = %d start = %d\n"
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"VPORT = %d start = %d\n"
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"PQ = %d start = %d\n"
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"RL = %d start = %d\n"
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"MAC = %d start = %d\n"
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"VLAN = %d start = %d\n"
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"ILT = %d start = %d\n",
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p_hwfn->hw_info.resc_num[QED_SB],
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p_hwfn->hw_info.resc_start[QED_SB],
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p_hwfn->hw_info.resc_num[QED_L2_QUEUE],
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p_hwfn->hw_info.resc_start[QED_L2_QUEUE],
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p_hwfn->hw_info.resc_num[QED_VPORT],
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p_hwfn->hw_info.resc_start[QED_VPORT],
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p_hwfn->hw_info.resc_num[QED_PQ],
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p_hwfn->hw_info.resc_start[QED_PQ],
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p_hwfn->hw_info.resc_num[QED_RL],
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p_hwfn->hw_info.resc_start[QED_RL],
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p_hwfn->hw_info.resc_num[QED_MAC],
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p_hwfn->hw_info.resc_start[QED_MAC],
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p_hwfn->hw_info.resc_num[QED_VLAN],
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p_hwfn->hw_info.resc_start[QED_VLAN],
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p_hwfn->hw_info.resc_num[QED_ILT],
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p_hwfn->hw_info.resc_start[QED_ILT]);
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}
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@ -17,6 +17,7 @@
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#include <linux/list.h>
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#include <linux/slab.h>
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#include <linux/qed/common_hsi.h>
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#include <linux/qed/eth_common.h>
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struct qed_hwfn;
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struct qed_ptt;
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@ -0,0 +1,87 @@
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/* QLogic qed NIC Driver
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* Copyright (c) 2015 QLogic Corporation
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*
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* This software is available under the terms of the GNU General Public License
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* (GPL) Version 2, available from the file COPYING in the main directory of
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* this source tree.
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*/
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#include <linux/types.h>
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#include <asm/byteorder.h>
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#include <asm/param.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/etherdevice.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/stddef.h>
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#include <linux/string.h>
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#include <linux/version.h>
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#include <linux/workqueue.h>
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#include <linux/bitops.h>
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#include <linux/bug.h>
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#include "qed.h"
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#include <linux/qed/qed_chain.h>
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#include "qed_cxt.h"
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#include "qed_dev_api.h"
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#include <linux/qed/qed_eth_if.h>
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#include "qed_hsi.h"
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#include "qed_hw.h"
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#include "qed_int.h"
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#include "qed_reg_addr.h"
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#include "qed_sp.h"
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static int qed_fill_eth_dev_info(struct qed_dev *cdev,
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struct qed_dev_eth_info *info)
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{
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int i;
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memset(info, 0, sizeof(*info));
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info->num_tc = 1;
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if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) {
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for_each_hwfn(cdev, i)
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info->num_queues += FEAT_NUM(&cdev->hwfns[i],
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QED_PF_L2_QUE);
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if (cdev->int_params.fp_msix_cnt)
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info->num_queues = min_t(u8, info->num_queues,
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cdev->int_params.fp_msix_cnt);
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} else {
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info->num_queues = cdev->num_hwfns;
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}
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info->num_vlan_filters = RESC_NUM(&cdev->hwfns[0], QED_VLAN);
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ether_addr_copy(info->port_mac,
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cdev->hwfns[0].hw_info.hw_mac_addr);
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qed_fill_dev_info(cdev, &info->common);
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return 0;
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}
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static const struct qed_eth_ops qed_eth_ops_pass = {
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.common = &qed_common_ops_pass,
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.fill_dev_info = &qed_fill_eth_dev_info,
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};
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const struct qed_eth_ops *qed_get_eth_ops(u32 version)
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{
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if (version != QED_ETH_INTERFACE_VERSION) {
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pr_notice("Cannot supply ethtool operations [%08x != %08x]\n",
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version, QED_ETH_INTERFACE_VERSION);
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return NULL;
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}
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return &qed_eth_ops_pass;
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}
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EXPORT_SYMBOL(qed_get_eth_ops);
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void qed_put_eth_ops(void)
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{
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/* TODO - reference count for module? */
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}
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EXPORT_SYMBOL(qed_put_eth_ops);
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@ -0,0 +1,279 @@
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/* QLogic qed NIC Driver
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* Copyright (c) 2015 QLogic Corporation
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*
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* This software is available under the terms of the GNU General Public License
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* (GPL) Version 2, available from the file COPYING in the main directory of
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* this source tree.
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*/
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#ifndef __ETH_COMMON__
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#define __ETH_COMMON__
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/********************/
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/* ETH FW CONSTANTS */
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/********************/
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#define ETH_CACHE_LINE_SIZE 64
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#define ETH_MAX_RAMROD_PER_CON 8
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#define ETH_TX_BD_PAGE_SIZE_BYTES 4096
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#define ETH_RX_BD_PAGE_SIZE_BYTES 4096
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#define ETH_RX_SGE_PAGE_SIZE_BYTES 4096
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#define ETH_RX_CQE_PAGE_SIZE_BYTES 4096
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#define ETH_RX_NUM_NEXT_PAGE_BDS 2
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#define ETH_RX_NUM_NEXT_PAGE_SGES 2
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#define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1
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#define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18
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#define ETH_TX_MAX_LSO_HDR_NBD 4
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#define ETH_TX_MIN_BDS_PER_LSO_PKT 3
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#define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3
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#define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2
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#define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2
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#define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 12 + 8))
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#define ETH_TX_MAX_LSO_HDR_BYTES 510
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#define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
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#define ETH_REG_CQE_PBL_SIZE 3
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/* num of MAC/VLAN filters */
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#define ETH_NUM_MAC_FILTERS 512
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#define ETH_NUM_VLAN_FILTERS 512
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/* approx. multicast constants */
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#define ETH_MULTICAST_BIN_FROM_MAC_SEED 0
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#define ETH_MULTICAST_MAC_BINS 256
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#define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32)
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/* ethernet vport update constants */
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#define ETH_FILTER_RULES_COUNT 10
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#define ETH_RSS_IND_TABLE_ENTRIES_NUM 128
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#define ETH_RSS_KEY_SIZE_REGS 10
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#define ETH_RSS_ENGINE_NUM_K2 207
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#define ETH_RSS_ENGINE_NUM_BB 127
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/* TPA constants */
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#define ETH_TPA_MAX_AGGS_NUM 64
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#define ETH_TPA_CQE_START_SGL_SIZE 3
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#define ETH_TPA_CQE_CONT_SGL_SIZE 6
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#define ETH_TPA_CQE_END_SGL_SIZE 4
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/* Queue Zone sizes */
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#define TSTORM_QZONE_SIZE 0
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#define MSTORM_QZONE_SIZE sizeof(struct mstorm_eth_queue_zone)
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#define USTORM_QZONE_SIZE sizeof(struct ustorm_eth_queue_zone)
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#define XSTORM_QZONE_SIZE 0
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#define YSTORM_QZONE_SIZE sizeof(struct ystorm_eth_queue_zone)
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#define PSTORM_QZONE_SIZE 0
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/* Interrupt coalescing TimeSet */
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struct coalescing_timeset {
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u8 timeset;
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u8 valid;
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};
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struct eth_tx_1st_bd_flags {
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u8 bitfields;
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#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1
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#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 0
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#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1
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#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT 1
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#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1
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#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT 2
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#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1
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#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT 3
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#define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1
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#define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT 4
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#define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1
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#define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 5
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#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1
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#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6
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#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1
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#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7
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};
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/* The parsing information data fo rthe first tx bd of a given packet. */
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struct eth_tx_data_1st_bd {
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__le16 vlan;
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u8 nbds;
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struct eth_tx_1st_bd_flags bd_flags;
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__le16 fw_use_only;
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};
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/* The parsing information data for the second tx bd of a given packet. */
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struct eth_tx_data_2nd_bd {
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__le16 tunn_ip_size;
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__le16 bitfields;
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#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK 0x1FFF
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#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT 0
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#define ETH_TX_DATA_2ND_BD_RESERVED0_MASK 0x7
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#define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13
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__le16 bitfields2;
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#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF
|
||||
#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0
|
||||
#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3
|
||||
#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4
|
||||
#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK 0x3
|
||||
#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT 6
|
||||
#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3
|
||||
#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT 8
|
||||
#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK 0x1
|
||||
#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT 10
|
||||
#define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK 0x1
|
||||
#define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT 11
|
||||
#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK 0x1
|
||||
#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT 12
|
||||
#define ETH_TX_DATA_2ND_BD_L4_UDP_MASK 0x1
|
||||
#define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT 13
|
||||
#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK 0x1
|
||||
#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT 14
|
||||
#define ETH_TX_DATA_2ND_BD_RESERVED1_MASK 0x1
|
||||
#define ETH_TX_DATA_2ND_BD_RESERVED1_SHIFT 15
|
||||
};
|
||||
|
||||
/* Regular ETH Rx FP CQE. */
|
||||
struct eth_fast_path_rx_reg_cqe {
|
||||
u8 type;
|
||||
u8 bitfields;
|
||||
#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK 0x7
|
||||
#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0
|
||||
#define ETH_FAST_PATH_RX_REG_CQE_TC_MASK 0xF
|
||||
#define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT 3
|
||||
#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1
|
||||
#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7
|
||||
__le16 pkt_len;
|
||||
struct parsing_and_err_flags pars_flags;
|
||||
__le16 vlan_tag;
|
||||
__le32 rss_hash;
|
||||
__le16 len_on_bd;
|
||||
u8 placement_offset;
|
||||
u8 reserved;
|
||||
__le16 pbl[ETH_REG_CQE_PBL_SIZE];
|
||||
u8 reserved1[10];
|
||||
};
|
||||
|
||||
/* The L4 pseudo checksum mode for Ethernet */
|
||||
enum eth_l4_pseudo_checksum_mode {
|
||||
ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH,
|
||||
ETH_L4_PSEUDO_CSUM_ZERO_LENGTH,
|
||||
MAX_ETH_L4_PSEUDO_CHECKSUM_MODE
|
||||
};
|
||||
|
||||
struct eth_rx_bd {
|
||||
struct regpair addr;
|
||||
};
|
||||
|
||||
/* regular ETH Rx SP CQE */
|
||||
struct eth_slow_path_rx_cqe {
|
||||
u8 type;
|
||||
u8 ramrod_cmd_id;
|
||||
u8 error_flag;
|
||||
u8 reserved[27];
|
||||
__le16 echo;
|
||||
};
|
||||
|
||||
/* union for all ETH Rx CQE types */
|
||||
union eth_rx_cqe {
|
||||
struct eth_fast_path_rx_reg_cqe fast_path_regular;
|
||||
struct eth_slow_path_rx_cqe slow_path;
|
||||
};
|
||||
|
||||
/* ETH Rx CQE type */
|
||||
enum eth_rx_cqe_type {
|
||||
ETH_RX_CQE_TYPE_UNUSED,
|
||||
ETH_RX_CQE_TYPE_REGULAR,
|
||||
ETH_RX_CQE_TYPE_SLOW_PATH,
|
||||
MAX_ETH_RX_CQE_TYPE
|
||||
};
|
||||
|
||||
/* ETH Rx producers data */
|
||||
struct eth_rx_prod_data {
|
||||
__le16 bd_prod;
|
||||
__le16 sge_prod;
|
||||
__le16 cqe_prod;
|
||||
__le16 reserved;
|
||||
};
|
||||
|
||||
/* The first tx bd of a given packet */
|
||||
struct eth_tx_1st_bd {
|
||||
struct regpair addr;
|
||||
__le16 nbytes;
|
||||
struct eth_tx_data_1st_bd data;
|
||||
};
|
||||
|
||||
/* The second tx bd of a given packet */
|
||||
struct eth_tx_2nd_bd {
|
||||
struct regpair addr;
|
||||
__le16 nbytes;
|
||||
struct eth_tx_data_2nd_bd data;
|
||||
};
|
||||
|
||||
/* The parsing information data for the third tx bd of a given packet. */
|
||||
struct eth_tx_data_3rd_bd {
|
||||
__le16 lso_mss;
|
||||
u8 bitfields;
|
||||
#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF
|
||||
#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0
|
||||
#define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF
|
||||
#define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT 4
|
||||
u8 resereved0[3];
|
||||
};
|
||||
|
||||
/* The third tx bd of a given packet */
|
||||
struct eth_tx_3rd_bd {
|
||||
struct regpair addr;
|
||||
__le16 nbytes;
|
||||
struct eth_tx_data_3rd_bd data;
|
||||
};
|
||||
|
||||
/* The common non-special TX BD ring element */
|
||||
struct eth_tx_bd {
|
||||
struct regpair addr;
|
||||
__le16 nbytes;
|
||||
__le16 reserved0;
|
||||
__le32 reserved1;
|
||||
};
|
||||
|
||||
union eth_tx_bd_types {
|
||||
struct eth_tx_1st_bd first_bd;
|
||||
struct eth_tx_2nd_bd second_bd;
|
||||
struct eth_tx_3rd_bd third_bd;
|
||||
struct eth_tx_bd reg_bd;
|
||||
};
|
||||
|
||||
/* Mstorm Queue Zone */
|
||||
struct mstorm_eth_queue_zone {
|
||||
struct eth_rx_prod_data rx_producers;
|
||||
__le32 reserved[2];
|
||||
};
|
||||
|
||||
/* Ustorm Queue Zone */
|
||||
struct ustorm_eth_queue_zone {
|
||||
struct coalescing_timeset int_coalescing_timeset;
|
||||
__le16 reserved[3];
|
||||
};
|
||||
|
||||
/* Ystorm Queue Zone */
|
||||
struct ystorm_eth_queue_zone {
|
||||
struct coalescing_timeset int_coalescing_timeset;
|
||||
__le16 reserved[3];
|
||||
};
|
||||
|
||||
/* ETH doorbell data */
|
||||
struct eth_db_data {
|
||||
u8 params;
|
||||
#define ETH_DB_DATA_DEST_MASK 0x3
|
||||
#define ETH_DB_DATA_DEST_SHIFT 0
|
||||
#define ETH_DB_DATA_AGG_CMD_MASK 0x3
|
||||
#define ETH_DB_DATA_AGG_CMD_SHIFT 2
|
||||
#define ETH_DB_DATA_BYPASS_EN_MASK 0x1
|
||||
#define ETH_DB_DATA_BYPASS_EN_SHIFT 4
|
||||
#define ETH_DB_DATA_RESERVED_MASK 0x1
|
||||
#define ETH_DB_DATA_RESERVED_SHIFT 5
|
||||
#define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3
|
||||
#define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6
|
||||
u8 agg_flags;
|
||||
__le16 bd_prod;
|
||||
};
|
||||
|
||||
#endif /* __ETH_COMMON__ */
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/* QLogic qed NIC Driver
|
||||
* Copyright (c) 2015 QLogic Corporation
|
||||
*
|
||||
* This software is available under the terms of the GNU General Public License
|
||||
* (GPL) Version 2, available from the file COPYING in the main directory of
|
||||
* this source tree.
|
||||
*/
|
||||
|
||||
#ifndef _QED_ETH_IF_H
|
||||
#define _QED_ETH_IF_H
|
||||
|
||||
#include <linux/list.h>
|
||||
#include <linux/if_link.h>
|
||||
#include <linux/qed/eth_common.h>
|
||||
#include <linux/qed/qed_if.h>
|
||||
|
||||
struct qed_dev_eth_info {
|
||||
struct qed_dev_info common;
|
||||
|
||||
u8 num_queues;
|
||||
u8 num_tc;
|
||||
|
||||
u8 port_mac[ETH_ALEN];
|
||||
u8 num_vlan_filters;
|
||||
};
|
||||
|
||||
struct qed_eth_ops {
|
||||
const struct qed_common_ops *common;
|
||||
|
||||
int (*fill_dev_info)(struct qed_dev *cdev,
|
||||
struct qed_dev_eth_info *info);
|
||||
|
||||
};
|
||||
|
||||
const struct qed_eth_ops *qed_get_eth_ops(u32 version);
|
||||
void qed_put_eth_ops(void);
|
||||
|
||||
#endif
|
||||
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