[AGP] intel_agp: Add support for Intel 4 series chipsets
Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Zhenyu Wang
Dave Airlie
Родитель
598d144823
Коммит
25ce77abf8
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@ -34,6 +34,12 @@
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#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
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#define PCI_DEVICE_ID_INTEL_IGD_HB 0x2A40
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#define PCI_DEVICE_ID_INTEL_IGD_IG 0x2A42
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#define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00
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#define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02
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#define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
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#define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
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#define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
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#define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22
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/* cover 915 and 945 variants */
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#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
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@ -55,6 +61,10 @@
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agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
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agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
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#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \
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agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
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agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB)
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extern int agp_memory_reserved;
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@ -80,8 +90,13 @@ extern int agp_memory_reserved;
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#define I915_PTEADDR 0x1C
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#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
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#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
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#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
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#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
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#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
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#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
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#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
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#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
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#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
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#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
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#define I915_IFPADDR 0x60
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/* Intel 965G registers */
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@ -506,6 +521,10 @@ static void intel_i830_init_gtt_entries(void)
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size = 512;
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}
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size += 4;
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} else if (IS_G4X) {
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/* On 4 series hardware, GTT stolen is separate from graphics
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* stolen, ignore it in stolen gtt entries counting */
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size = 0;
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} else {
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/* On previous hardware, the GTT size was just what was
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* required to map the aperture.
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@ -554,30 +573,54 @@ static void intel_i830_init_gtt_entries(void)
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break;
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case I915_GMCH_GMS_STOLEN_48M:
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/* Check it's really I915G */
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if (IS_I915 || IS_I965 || IS_G33)
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if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
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gtt_entries = MB(48) - KB(size);
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else
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gtt_entries = 0;
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break;
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case I915_GMCH_GMS_STOLEN_64M:
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/* Check it's really I915G */
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if (IS_I915 || IS_I965 || IS_G33)
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if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
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gtt_entries = MB(64) - KB(size);
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else
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gtt_entries = 0;
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break;
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case G33_GMCH_GMS_STOLEN_128M:
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if (IS_G33 || IS_I965)
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if (IS_G33 || IS_I965 || IS_G4X)
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gtt_entries = MB(128) - KB(size);
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else
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gtt_entries = 0;
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break;
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case G33_GMCH_GMS_STOLEN_256M:
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if (IS_G33 || IS_I965)
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if (IS_G33 || IS_I965 || IS_G4X)
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gtt_entries = MB(256) - KB(size);
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else
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gtt_entries = 0;
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break;
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case INTEL_GMCH_GMS_STOLEN_96M:
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if (IS_I965 || IS_G4X)
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gtt_entries = MB(96) - KB(size);
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else
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gtt_entries = 0;
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break;
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case INTEL_GMCH_GMS_STOLEN_160M:
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if (IS_I965 || IS_G4X)
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gtt_entries = MB(160) - KB(size);
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else
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gtt_entries = 0;
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break;
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case INTEL_GMCH_GMS_STOLEN_224M:
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if (IS_I965 || IS_G4X)
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gtt_entries = MB(224) - KB(size);
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else
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gtt_entries = 0;
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break;
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case INTEL_GMCH_GMS_STOLEN_352M:
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if (IS_I965 || IS_G4X)
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gtt_entries = MB(352) - KB(size);
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else
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gtt_entries = 0;
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break;
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default:
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gtt_entries = 0;
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break;
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@ -1136,6 +1179,20 @@ static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
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return addr | bridge->driver->masks[type].mask;
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}
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static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
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{
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switch (agp_bridge->dev->device) {
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case PCI_DEVICE_ID_INTEL_IGD_HB:
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case PCI_DEVICE_ID_INTEL_IGD_E_HB:
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case PCI_DEVICE_ID_INTEL_Q45_HB:
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case PCI_DEVICE_ID_INTEL_G45_HB:
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*gtt_offset = *gtt_size = MB(2);
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break;
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default:
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*gtt_offset = *gtt_size = KB(512);
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}
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}
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/* The intel i965 automatically initializes the agp aperture during POST.
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* Use the memory already set aside for in the GTT.
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*/
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@ -1156,10 +1213,7 @@ static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
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temp &= 0xfff00000;
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if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_HB)
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gtt_offset = gtt_size = MB(2);
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else
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gtt_offset = gtt_size = KB(512);
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intel_i965_get_gtt_range(>t_offset, >t_size);
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intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
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@ -2065,6 +2119,12 @@ static const struct intel_driver_description {
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NULL, &intel_g33_driver },
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{ PCI_DEVICE_ID_INTEL_IGD_HB, PCI_DEVICE_ID_INTEL_IGD_IG, 0,
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"Intel Integrated Graphics Device", NULL, &intel_i965_driver },
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{ PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0,
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"Intel Integrated Graphics Device", NULL, &intel_i965_driver },
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{ PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
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"Q45/Q43", NULL, &intel_i965_driver },
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{ PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
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"G45/G43", NULL, &intel_i965_driver },
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{ 0, 0, 0, NULL, NULL, NULL }
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};
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@ -2256,6 +2316,9 @@ static struct pci_device_id agp_intel_pci_table[] = {
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ID(PCI_DEVICE_ID_INTEL_Q35_HB),
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ID(PCI_DEVICE_ID_INTEL_Q33_HB),
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ID(PCI_DEVICE_ID_INTEL_IGD_HB),
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ID(PCI_DEVICE_ID_INTEL_IGD_E_HB),
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ID(PCI_DEVICE_ID_INTEL_Q45_HB),
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ID(PCI_DEVICE_ID_INTEL_G45_HB),
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{ }
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};
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