clk: vc5: Enable addition output configurations of the Versaclock
The existing driver is expecting the Versaclock to be pre-programmed, and only sets the output frequency. Unfortunately, not all devices are pre-programmed, and the Versaclock chip has more options beyond just the frequency. This patch enables the following additional features: - Programmable voltage: 1.8V, 2.5V, or 3.3V - Slew Percentage of normal: 85%, 90%, or 100% - Output Type: LVPECL, CMOS, HCSL, or LVDS Signed-off-by: Adam Ford <aford173@gmail.com> Link: https://lore.kernel.org/r/20200603154329.31579-3-aford173@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Adam Ford
Stephen Boyd
Родитель
34662f6e30
Коммит
260249f929
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@ -24,6 +24,8 @@
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <dt-bindings/clk/versaclock.h>
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/* VersaClock5 registers */
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#define VC5_OTP_CONTROL 0x00
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@ -89,6 +91,28 @@
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/* Clock control register for clock 1,2 */
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#define VC5_CLK_OUTPUT_CFG(idx, n) (0x60 + ((idx) * 0x2) + (n))
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#define VC5_CLK_OUTPUT_CFG0_CFG_SHIFT 5
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#define VC5_CLK_OUTPUT_CFG0_CFG_MASK GENMASK(7, VC5_CLK_OUTPUT_CFG0_CFG_SHIFT)
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#define VC5_CLK_OUTPUT_CFG0_CFG_LVPECL (VC5_LVPECL)
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#define VC5_CLK_OUTPUT_CFG0_CFG_CMOS (VC5_CMOS)
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#define VC5_CLK_OUTPUT_CFG0_CFG_HCSL33 (VC5_HCSL33)
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#define VC5_CLK_OUTPUT_CFG0_CFG_LVDS (VC5_LVDS)
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#define VC5_CLK_OUTPUT_CFG0_CFG_CMOS2 (VC5_CMOS2)
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#define VC5_CLK_OUTPUT_CFG0_CFG_CMOSD (VC5_CMOSD)
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#define VC5_CLK_OUTPUT_CFG0_CFG_HCSL25 (VC5_HCSL25)
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#define VC5_CLK_OUTPUT_CFG0_PWR_SHIFT 3
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#define VC5_CLK_OUTPUT_CFG0_PWR_MASK GENMASK(4, VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
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#define VC5_CLK_OUTPUT_CFG0_PWR_18 (0<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
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#define VC5_CLK_OUTPUT_CFG0_PWR_25 (2<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
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#define VC5_CLK_OUTPUT_CFG0_PWR_33 (3<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
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#define VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT 0
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#define VC5_CLK_OUTPUT_CFG0_SLEW_MASK GENMASK(1, VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
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#define VC5_CLK_OUTPUT_CFG0_SLEW_80 (0<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
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#define VC5_CLK_OUTPUT_CFG0_SLEW_85 (1<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
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#define VC5_CLK_OUTPUT_CFG0_SLEW_90 (2<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
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#define VC5_CLK_OUTPUT_CFG0_SLEW_100 (3<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
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#define VC5_CLK_OUTPUT_CFG1_EN_CLKBUF BIT(0)
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#define VC5_CLK_OE_SHDN 0x68
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@ -143,6 +167,8 @@ struct vc5_hw_data {
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u32 div_int;
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u32 div_frc;
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unsigned int num;
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unsigned int clk_output_cfg0;
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unsigned int clk_output_cfg0_mask;
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};
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struct vc5_driver_data {
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@ -567,6 +593,17 @@ static int vc5_clk_out_prepare(struct clk_hw *hw)
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regmap_update_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
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VC5_CLK_OUTPUT_CFG1_EN_CLKBUF,
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VC5_CLK_OUTPUT_CFG1_EN_CLKBUF);
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if (hwdata->clk_output_cfg0_mask) {
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dev_dbg(&vc5->client->dev, "Update output %d mask 0x%0X val 0x%0X\n",
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hwdata->num, hwdata->clk_output_cfg0_mask,
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hwdata->clk_output_cfg0);
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regmap_update_bits(vc5->regmap,
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VC5_CLK_OUTPUT_CFG(hwdata->num, 0),
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hwdata->clk_output_cfg0_mask,
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hwdata->clk_output_cfg0);
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}
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return 0;
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}
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@ -666,6 +703,120 @@ static int vc5_map_index_to_output(const enum vc5_model model,
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}
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}
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static int vc5_update_mode(struct device_node *np_output,
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struct vc5_hw_data *clk_out)
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{
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u32 value;
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if (!of_property_read_u32(np_output, "idt,mode", &value)) {
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clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_CFG_MASK;
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switch (value) {
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case VC5_CLK_OUTPUT_CFG0_CFG_LVPECL:
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case VC5_CLK_OUTPUT_CFG0_CFG_CMOS:
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case VC5_CLK_OUTPUT_CFG0_CFG_HCSL33:
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case VC5_CLK_OUTPUT_CFG0_CFG_LVDS:
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case VC5_CLK_OUTPUT_CFG0_CFG_CMOS2:
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case VC5_CLK_OUTPUT_CFG0_CFG_CMOSD:
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case VC5_CLK_OUTPUT_CFG0_CFG_HCSL25:
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clk_out->clk_output_cfg0 |=
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value << VC5_CLK_OUTPUT_CFG0_CFG_SHIFT;
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break;
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default:
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return -EINVAL;
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}
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}
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return 0;
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}
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static int vc5_update_power(struct device_node *np_output,
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struct vc5_hw_data *clk_out)
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{
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u32 value;
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if (!of_property_read_u32(np_output,
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"idt,voltage-microvolts", &value)) {
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clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_PWR_MASK;
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switch (value) {
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case 1800000:
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clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_18;
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break;
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case 2500000:
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clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_25;
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break;
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case 3300000:
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clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_33;
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break;
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default:
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return -EINVAL;
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}
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}
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return 0;
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}
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static int vc5_update_slew(struct device_node *np_output,
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struct vc5_hw_data *clk_out)
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{
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u32 value;
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if (!of_property_read_u32(np_output, "idt,slew-percent", &value)) {
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clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_SLEW_MASK;
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switch (value) {
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case 80:
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clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_80;
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break;
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case 85:
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clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_85;
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break;
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case 90:
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clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_90;
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break;
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case 100:
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clk_out->clk_output_cfg0 |=
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VC5_CLK_OUTPUT_CFG0_SLEW_100;
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break;
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default:
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return -EINVAL;
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}
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}
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return 0;
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}
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static int vc5_get_output_config(struct i2c_client *client,
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struct vc5_hw_data *clk_out)
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{
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struct device_node *np_output;
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char *child_name;
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int ret = 0;
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child_name = kasprintf(GFP_KERNEL, "OUT%d", clk_out->num + 1);
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np_output = of_get_child_by_name(client->dev.of_node, child_name);
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kfree(child_name);
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if (!np_output)
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goto output_done;
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ret = vc5_update_mode(np_output, clk_out);
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if (ret)
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goto output_error;
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ret = vc5_update_power(np_output, clk_out);
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if (ret)
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goto output_error;
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ret = vc5_update_slew(np_output, clk_out);
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output_error:
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if (ret) {
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dev_err(&client->dev,
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"Invalid clock output configuration OUT%d\n",
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clk_out->num + 1);
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}
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of_node_put(np_output);
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output_done:
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return ret;
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}
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static const struct of_device_id clk_vc5_of_match[];
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static int vc5_probe(struct i2c_client *client, const struct i2c_device_id *id)
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@ -863,6 +1014,11 @@ static int vc5_probe(struct i2c_client *client, const struct i2c_device_id *id)
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init.name);
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goto err_clk;
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}
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/* Fetch Clock Output configuration from DT (if specified) */
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ret = vc5_get_output_config(client, &vc5->clk_out[n]);
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if (ret)
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goto err_clk;
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}
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ret = of_clk_add_hw_provider(client->dev.of_node, vc5_of_clk_get, vc5);
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