drm/amd/display: add CLKMGR changes for DCN32/321
Add support for managing DCN3.2.x clocks. v2: squash in smu interface updates (Alex) v3: Drop unused SMU header (Alex) Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Jerry Zuo <jerry.zuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Aurabindo Pillai
Alex Deucher
Родитель
dda4fb85e4
Коммит
265280b998
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@ -172,4 +172,39 @@ AMD_DAL_CLK_MGR_DCN316 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn316/,$(CLK_MGR_
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AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN316)
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###############################################################################
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# DCN32
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###############################################################################
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CLK_MGR_DCN32 = dcn32_clk_mgr.o dcn32_clk_mgr_smu_msg.o
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AMD_DAL_CLK_MGR_DCN32 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn32/,$(CLK_MGR_DCN32))
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ifdef CONFIG_X86
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CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -msse
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endif
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ifdef CONFIG_PPC64
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CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -mhard-float -maltivec
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endif
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ifdef CONFIG_CC_IS_GCC
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ifeq ($(call cc-ifversion, -lt, 0701, y), y)
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IS_OLD_GCC = 1
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endif
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CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -mhard-float
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endif
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ifdef CONFIG_X86
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ifdef IS_OLD_GCC
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# Stack alignment mismatch, proceed with caution.
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# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
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# (8B stack alignment).
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CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -mpreferred-stack-boundary=4
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else
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CFLAGS_$(AMDDALPATH)/dc/clk_mgr/dcn32/dcn32_clk_mgr.o := -msse2
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endif
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endif
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AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN32)
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endif
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@ -45,6 +45,7 @@
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#include "dcn31/dcn31_clk_mgr.h"
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#include "dcn315/dcn315_clk_mgr.h"
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#include "dcn316/dcn316_clk_mgr.h"
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#include "dcn32/dcn32_clk_mgr.h"
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int clk_mgr_helper_get_active_display_cnt(
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@ -316,8 +317,19 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
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return &clk_mgr->base.base;
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}
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break;
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#endif
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case AMDGPU_FAMILY_GC_11_0_0: {
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struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
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if (clk_mgr == NULL) {
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BREAK_TO_DEBUGGER();
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return NULL;
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}
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dcn32_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
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return &clk_mgr->base;
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break;
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#endif
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}
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default:
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ASSERT(0); /* Unknown Asic */
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break;
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@ -360,6 +372,9 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)
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dcn316_clk_mgr_destroy(clk_mgr);
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break;
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case AMDGPU_FAMILY_GC_11_0_0:
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dcn32_clk_mgr_destroy(clk_mgr);
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break;
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default:
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break;
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}
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@ -129,7 +129,7 @@ static noinline void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
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/* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */
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clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true;
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clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dummy_pstate_latency_us;
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clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 0;
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clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;
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clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
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clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
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@ -137,6 +137,14 @@ static noinline void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
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clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF;
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clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;
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clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;
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clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = 1600;
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clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 38;
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clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = 8000;
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clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9;
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clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = 10000;
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clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8;
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clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = 16000;
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clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5;
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/* Set D - MALL - SR enter and exit times adjusted for MALL */
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clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true;
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@ -517,6 +525,8 @@ static void dcn30_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct d
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if (!clk_mgr->smu_present)
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return;
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/* TODO - DP2.0 HW: calculate link 128b/132 link rate in clock manager with new formula */
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clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
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for (i = 0; i < MAX_PIPES * 2; i++) {
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@ -620,7 +630,8 @@ void dcn3_clk_mgr_construct(
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void dcn3_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
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{
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kfree(clk_mgr->base.bw_params);
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if (clk_mgr->base.bw_params)
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kfree(clk_mgr->base.bw_params);
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if (clk_mgr->wm_range_table)
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dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,
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@ -26,6 +26,66 @@
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#ifndef __DCN30_CLK_MGR_H__
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#define __DCN30_CLK_MGR_H__
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//CLK1_CLK_PLL_REQ
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#ifndef CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT
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#define CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
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#define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
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#define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
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#define CLK11_CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
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#define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
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#define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
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//CLK1_CLK0_DFS_CNTL
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#define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER__SHIFT 0x0
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#define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER_MASK 0x0000007FL
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/*DPREF clock related*/
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#define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0
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#define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL
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#define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0
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#define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL
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#define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0
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#define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL
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#define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT 0x0
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#define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK 0x0000007FL
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//CLK3_0_CLK3_CLK_PLL_REQ
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#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
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#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
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#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
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#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
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#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
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#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
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#define mmCLK0_CLK2_DFS_CNTL 0x16C55
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#define mmCLK00_CLK0_CLK2_DFS_CNTL 0x16C55
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#define mmCLK01_CLK0_CLK2_DFS_CNTL 0x16E55
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#define mmCLK02_CLK0_CLK2_DFS_CNTL 0x17055
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#define mmCLK0_CLK3_DFS_CNTL 0x16C60
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#define mmCLK00_CLK0_CLK3_DFS_CNTL 0x16C60
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#define mmCLK01_CLK0_CLK3_DFS_CNTL 0x16E60
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#define mmCLK02_CLK0_CLK3_DFS_CNTL 0x17060
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#define mmCLK03_CLK0_CLK3_DFS_CNTL 0x17260
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#define mmCLK0_CLK_PLL_REQ 0x16C10
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#define mmCLK00_CLK0_CLK_PLL_REQ 0x16C10
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#define mmCLK01_CLK0_CLK_PLL_REQ 0x16E10
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#define mmCLK02_CLK0_CLK_PLL_REQ 0x17010
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#define mmCLK03_CLK0_CLK_PLL_REQ 0x17210
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#define mmCLK1_CLK_PLL_REQ 0x1B00D
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#define mmCLK10_CLK1_CLK_PLL_REQ 0x1B00D
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#define mmCLK11_CLK1_CLK_PLL_REQ 0x1B20D
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#define mmCLK12_CLK1_CLK_PLL_REQ 0x1B40D
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#define mmCLK13_CLK1_CLK_PLL_REQ 0x1B60D
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#define mmCLK2_CLK_PLL_REQ 0x17E0D
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/*AMCLK*/
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#define mmCLK11_CLK1_CLK0_DFS_CNTL 0x1B23F
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#define mmCLK11_CLK1_CLK_PLL_REQ 0x1B20D
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#endif
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void dcn3_init_clocks(struct clk_mgr *clk_mgr_base);
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void dcn3_clk_mgr_construct(struct dc_context *ctx,
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@ -0,0 +1,65 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright 2022 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef DALSMC_H
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#define DALSMC_H
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#define DALSMC_VERSION 0x1
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// SMU Response Codes:
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#define DALSMC_Result_OK 0x1
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#define DALSMC_Result_Failed 0xFF
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#define DALSMC_Result_UnknownCmd 0xFE
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#define DALSMC_Result_CmdRejectedPrereq 0xFD
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#define DALSMC_Result_CmdRejectedBusy 0xFC
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// Message Definitions:
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#define DALSMC_MSG_TestMessage 0x1
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#define DALSMC_MSG_GetSmuVersion 0x2
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#define DALSMC_MSG_GetDriverIfVersion 0x3
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#define DALSMC_MSG_GetMsgHeaderVersion 0x4
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#define DALSMC_MSG_SetDalDramAddrHigh 0x5
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#define DALSMC_MSG_SetDalDramAddrLow 0x6
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#define DALSMC_MSG_TransferTableSmu2Dram 0x7
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#define DALSMC_MSG_TransferTableDram2Smu 0x8
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#define DALSMC_MSG_SetHardMinByFreq 0x9
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#define DALSMC_MSG_SetHardMaxByFreq 0xA
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#define DALSMC_MSG_GetDpmFreqByIndex 0xB
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#define DALSMC_MSG_GetDcModeMaxDpmFreq 0xC
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#define DALSMC_MSG_SetMinDeepSleepDcfclk 0xD
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#define DALSMC_MSG_NumOfDisplays 0xE
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#define DALSMC_MSG_SetExternalClientDfCstateAllow 0xF
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#define DALSMC_MSG_BacoAudioD3PME 0x10
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#define DALSMC_MSG_SetFclkSwitchAllow 0x11
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#define DALSMC_MSG_SetCabForUclkPstate 0x12
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#define DALSMC_MSG_SetWorstCaseUclkLatency 0x13
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#define DALSMC_Message_Count 0x14
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typedef enum {
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FCLK_SWITCH_DISALLOW,
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FCLK_SWITCH_ALLOW,
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} FclkSwitchAllow_e;
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#endif
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@ -0,0 +1,628 @@
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/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
|
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* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
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*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
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* OTHER DEALINGS IN THE SOFTWARE.
|
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*
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* Authors: AMD
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*
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*/
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#include "dccg.h"
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#include "clk_mgr_internal.h"
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#include "dcn32/dcn32_clk_mgr_smu_msg.h"
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#include "dcn20/dcn20_clk_mgr.h"
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#include "dce100/dce_clk_mgr.h"
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#include "reg_helper.h"
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#include "core_types.h"
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#include "dm_helpers.h"
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#include "atomfirmware.h"
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#include "smu13_driver_if.h"
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#include "dcn/dcn_3_2_0_offset.h"
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#include "dcn/dcn_3_2_0_sh_mask.h"
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#include "dcn32/dcn32_clk_mgr.h"
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#define DCN_BASE__INST0_SEG1 0x000000C0
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#define mmCLK1_CLK_PLL_REQ 0x16E37
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#define mmCLK1_CLK0_DFS_CNTL 0x16E69
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#define mmCLK1_CLK1_DFS_CNTL 0x16E6C
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#define mmCLK1_CLK2_DFS_CNTL 0x16E6F
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#define mmCLK1_CLK3_DFS_CNTL 0x16E72
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#define mmCLK1_CLK4_DFS_CNTL 0x16E75
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#define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001ffUL
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#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000f000UL
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#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xffff0000UL
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#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x00000000
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#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0x0000000c
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#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x00000010
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#define mmCLK01_CLK0_CLK_PLL_REQ 0x16E37
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#define mmCLK01_CLK0_CLK0_DFS_CNTL 0x16E64
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#define mmCLK01_CLK0_CLK1_DFS_CNTL 0x16E67
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#define mmCLK01_CLK0_CLK2_DFS_CNTL 0x16E6A
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#define mmCLK01_CLK0_CLK3_DFS_CNTL 0x16E6D
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#define mmCLK01_CLK0_CLK4_DFS_CNTL 0x16E70
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#define CLK0_CLK_PLL_REQ__FbMult_int_MASK 0x000001ffL
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#define CLK0_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000f000L
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#define CLK0_CLK_PLL_REQ__FbMult_frac_MASK 0xffff0000L
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#define CLK0_CLK_PLL_REQ__FbMult_int__SHIFT 0x00000000
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#define CLK0_CLK_PLL_REQ__PllSpineDiv__SHIFT 0x0000000c
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#define CLK0_CLK_PLL_REQ__FbMult_frac__SHIFT 0x00000010
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#undef FN
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#define FN(reg_name, field_name) \
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clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
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#define REG(reg) \
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(clk_mgr->regs->reg)
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#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
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#define BASE(seg) BASE_INNER(seg)
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|
||||
#define SR(reg_name)\
|
||||
.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
|
||||
reg ## reg_name
|
||||
|
||||
#define CLK_SR_DCN32(reg_name)\
|
||||
.reg_name = mm ## reg_name
|
||||
|
||||
static const struct clk_mgr_registers clk_mgr_regs_dcn32 = {
|
||||
CLK_REG_LIST_DCN32()
|
||||
};
|
||||
|
||||
static const struct clk_mgr_shift clk_mgr_shift_dcn32 = {
|
||||
CLK_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
|
||||
};
|
||||
|
||||
static const struct clk_mgr_mask clk_mgr_mask_dcn32 = {
|
||||
CLK_COMMON_MASK_SH_LIST_DCN32(_MASK)
|
||||
};
|
||||
|
||||
|
||||
#define CLK_SR_DCN321(reg_name, block, inst)\
|
||||
.reg_name = mm ## block ## _ ## reg_name
|
||||
|
||||
static const struct clk_mgr_registers clk_mgr_regs_dcn321 = {
|
||||
CLK_REG_LIST_DCN321()
|
||||
};
|
||||
|
||||
static const struct clk_mgr_shift clk_mgr_shift_dcn321 = {
|
||||
CLK_COMMON_MASK_SH_LIST_DCN321(__SHIFT)
|
||||
};
|
||||
|
||||
static const struct clk_mgr_mask clk_mgr_mask_dcn321 = {
|
||||
CLK_COMMON_MASK_SH_LIST_DCN321(_MASK)
|
||||
};
|
||||
|
||||
|
||||
/* Query SMU for all clock states for a particular clock */
|
||||
static void dcn32_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0,
|
||||
unsigned int *num_levels)
|
||||
{
|
||||
unsigned int i;
|
||||
char *entry_i = (char *)entry_0;
|
||||
|
||||
uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
|
||||
|
||||
if (ret & (1 << 31))
|
||||
/* fine-grained, only min and max */
|
||||
*num_levels = 2;
|
||||
else
|
||||
/* discrete, a number of fixed states */
|
||||
/* will set num_levels to 0 on failure */
|
||||
*num_levels = ret & 0xFF;
|
||||
|
||||
/* if the initial message failed, num_levels will be 0 */
|
||||
for (i = 0; i < *num_levels; i++) {
|
||||
*((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
|
||||
entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
|
||||
}
|
||||
}
|
||||
|
||||
static void dcn32_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
|
||||
{
|
||||
/* defaults */
|
||||
double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us;
|
||||
double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us;
|
||||
double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us;
|
||||
double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us;
|
||||
/* For min clocks use as reported by PM FW and report those as min */
|
||||
uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz;
|
||||
uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
|
||||
uint16_t setb_min_uclk_mhz = min_uclk_mhz;
|
||||
uint16_t setb_min_dcfclk_mhz = min_dcfclk_mhz;
|
||||
/* For Set B ranges use min clocks state 2 when available, and report those to PM FW */
|
||||
if (clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz)
|
||||
setb_min_dcfclk_mhz = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz;
|
||||
if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz)
|
||||
setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz;
|
||||
|
||||
/* Set A - Normal - default values */
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_latency_us;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;
|
||||
|
||||
/* Set B - Performance - higher clocks, using DPM[2] DCFCLK and UCLK */
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.fclk_change_latency_us = fclk_change_latency_us;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = setb_min_dcfclk_mhz;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = setb_min_uclk_mhz;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF;
|
||||
|
||||
/* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */
|
||||
/* 'DalDummyClockChangeLatencyNs' registry key option set to 0x7FFFFFFF can be used to disable Set C for dummy p-state */
|
||||
if (clk_mgr->base.ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = 38;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.fclk_change_latency_us = fclk_change_latency_us;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;
|
||||
clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz * 16;
|
||||
clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 38;
|
||||
clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memclk_mhz * 16;
|
||||
clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9;
|
||||
clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz * 16;
|
||||
clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8;
|
||||
clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[3].memclk_mhz * 16;
|
||||
clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5;
|
||||
}
|
||||
/* Set D - MALL - SR enter and exit time specific to MALL, TBD after bringup or later phase for now use DRAM values / 2 */
|
||||
/* For MALL DRAM clock change latency is N/A, for watermak calculations use lowest value dummy P state latency */
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.fclk_change_latency_us = fclk_change_latency_us;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = sr_exit_time_us / 2; // TBD
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us / 2; // TBD
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz;
|
||||
clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF;
|
||||
}
|
||||
|
||||
void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
|
||||
{
|
||||
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
|
||||
unsigned int num_levels;
|
||||
|
||||
memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
|
||||
clk_mgr_base->clks.p_state_change_support = true;
|
||||
clk_mgr_base->clks.prev_p_state_change_support = true;
|
||||
clk_mgr_base->clks.fclk_prev_p_state_change_support = true;
|
||||
clk_mgr->smu_present = false;
|
||||
|
||||
if (!clk_mgr_base->bw_params)
|
||||
return;
|
||||
|
||||
if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))
|
||||
clk_mgr->smu_present = true;
|
||||
|
||||
if (!clk_mgr->smu_present)
|
||||
return;
|
||||
|
||||
dcn30_smu_check_driver_if_version(clk_mgr);
|
||||
dcn30_smu_check_msg_header_version(clk_mgr);
|
||||
|
||||
/* DCFCLK */
|
||||
dcn32_init_single_clock(clk_mgr, PPCLK_DCFCLK,
|
||||
&clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
|
||||
&num_levels);
|
||||
|
||||
/* SOCCLK */
|
||||
dcn32_init_single_clock(clk_mgr, PPCLK_SOCCLK,
|
||||
&clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
|
||||
&num_levels);
|
||||
/* DTBCLK */
|
||||
dcn32_init_single_clock(clk_mgr, PPCLK_DTBCLK,
|
||||
&clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
|
||||
&num_levels);
|
||||
|
||||
/* DISPCLK */
|
||||
dcn32_init_single_clock(clk_mgr, PPCLK_DISPCLK,
|
||||
&clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
|
||||
&num_levels);
|
||||
|
||||
|
||||
/* Get UCLK, update bounding box */
|
||||
clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);
|
||||
|
||||
/* WM range table */
|
||||
dcn32_build_wm_range_table(clk_mgr);
|
||||
}
|
||||
|
||||
static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
|
||||
struct dc_state *context,
|
||||
bool safe_to_lower)
|
||||
{
|
||||
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
|
||||
struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
|
||||
struct dc *dc = clk_mgr_base->ctx->dc;
|
||||
int display_count;
|
||||
bool update_dppclk = false;
|
||||
bool update_dispclk = false;
|
||||
bool enter_display_off = false;
|
||||
bool dpp_clock_lowered = false;
|
||||
struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
|
||||
bool force_reset = false;
|
||||
bool update_uclk = false;
|
||||
bool p_state_change_support;
|
||||
bool fclk_p_state_change_support;
|
||||
int total_plane_count;
|
||||
|
||||
if (dc->work_arounds.skip_clock_update)
|
||||
return;
|
||||
|
||||
if (clk_mgr_base->clks.dispclk_khz == 0 ||
|
||||
(dc->debug.force_clock_mode & 0x1)) {
|
||||
/* This is from resume or boot up, if forced_clock cfg option used,
|
||||
* we bypass program dispclk and DPPCLK, but need set them for S3.
|
||||
*/
|
||||
force_reset = true;
|
||||
|
||||
dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
|
||||
|
||||
/* Force_clock_mode 0x1: force reset the clock even it is the same clock
|
||||
* as long as it is in Passive level.
|
||||
*/
|
||||
}
|
||||
display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
|
||||
|
||||
if (display_count == 0)
|
||||
enter_display_off = true;
|
||||
|
||||
if (enter_display_off == safe_to_lower)
|
||||
dcn30_smu_set_num_of_displays(clk_mgr, display_count);
|
||||
|
||||
if (dc->debug.force_min_dcfclk_mhz > 0)
|
||||
new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
|
||||
new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
|
||||
|
||||
if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
|
||||
clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
|
||||
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
|
||||
}
|
||||
|
||||
if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
|
||||
clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
|
||||
dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));
|
||||
}
|
||||
|
||||
if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
|
||||
/* We don't actually care about socclk, don't notify SMU of hard min */
|
||||
clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
|
||||
|
||||
clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
|
||||
clk_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support;
|
||||
|
||||
total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
|
||||
p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0);
|
||||
fclk_p_state_change_support = new_clocks->fclk_p_state_change_support || (total_plane_count == 0);
|
||||
if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
|
||||
clk_mgr_base->clks.p_state_change_support = p_state_change_support;
|
||||
|
||||
/* to disable P-State switching, set UCLK min = max */
|
||||
if (!clk_mgr_base->clks.p_state_change_support)
|
||||
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
|
||||
clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
|
||||
}
|
||||
|
||||
if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) {
|
||||
clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;
|
||||
|
||||
/* To disable FCLK P-state switching, send FCLK_PSTATE_NOTSUPPORTED message to PMFW */
|
||||
if (!clk_mgr_base->clks.fclk_p_state_change_support) {
|
||||
/* Handle code for sending a message to PMFW that FCLK P-state change is not supported */
|
||||
dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_NOTSUPPORTED);
|
||||
}
|
||||
}
|
||||
|
||||
/* Always update saved value, even if new value not set due to P-State switching unsupported */
|
||||
if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
|
||||
clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
|
||||
update_uclk = true;
|
||||
}
|
||||
|
||||
/* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
|
||||
if (clk_mgr_base->clks.p_state_change_support &&
|
||||
(update_uclk || !clk_mgr_base->clks.prev_p_state_change_support))
|
||||
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
|
||||
|
||||
if (clk_mgr_base->clks.fclk_p_state_change_support &&
|
||||
(update_uclk || !clk_mgr_base->clks.fclk_prev_p_state_change_support)) {
|
||||
/* Handle the code for sending a message to PMFW that FCLK P-state change is supported */
|
||||
dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_SUPPORTED);
|
||||
}
|
||||
|
||||
if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
|
||||
if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
|
||||
dpp_clock_lowered = true;
|
||||
|
||||
clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
|
||||
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
|
||||
update_dppclk = true;
|
||||
}
|
||||
|
||||
if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
|
||||
clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
|
||||
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz));
|
||||
update_dispclk = true;
|
||||
}
|
||||
|
||||
if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
|
||||
if (dpp_clock_lowered) {
|
||||
/* if clock is being lowered, increase DTO before lowering refclk */
|
||||
dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
|
||||
dcn20_update_clocks_update_dentist(clk_mgr, context);
|
||||
} else {
|
||||
/* if clock is being raised, increase refclk before lowering DTO */
|
||||
if (update_dppclk || update_dispclk)
|
||||
dcn20_update_clocks_update_dentist(clk_mgr, context);
|
||||
/* There is a check inside dcn20_update_clocks_update_dpp_dto which ensures
|
||||
* that we do not lower dto when it is not safe to lower. We do not need to
|
||||
* compare the current and new dppclk before calling this function.
|
||||
*/
|
||||
dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
|
||||
}
|
||||
}
|
||||
|
||||
if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
|
||||
/*update dmcu for wait_loop count*/
|
||||
dmcu->funcs->set_psr_wait_loop(dmcu,
|
||||
clk_mgr_base->clks.dispclk_khz / 1000 / 7);
|
||||
}
|
||||
|
||||
void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr)
|
||||
{
|
||||
struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;
|
||||
int ss_info_num = bp->funcs->get_ss_entry_number(
|
||||
bp, AS_SIGNAL_TYPE_GPU_PLL);
|
||||
|
||||
if (ss_info_num) {
|
||||
struct spread_spectrum_info info = { { 0 } };
|
||||
enum bp_result result = bp->funcs->get_spread_spectrum_info(
|
||||
bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info);
|
||||
|
||||
/* SSInfo.spreadSpectrumPercentage !=0 would be sign
|
||||
* that SS is enabled
|
||||
*/
|
||||
if (result == BP_RESULT_OK &&
|
||||
info.spread_spectrum_percentage != 0) {
|
||||
clk_mgr->ss_on_dprefclk = true;
|
||||
clk_mgr->dprefclk_ss_divider = info.spread_percentage_divider;
|
||||
|
||||
if (info.type.CENTER_MODE == 0) {
|
||||
/* Currently for DP Reference clock we
|
||||
* need only SS percentage for
|
||||
* downspread
|
||||
*/
|
||||
clk_mgr->dprefclk_ss_percentage =
|
||||
info.spread_spectrum_percentage;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
static void dcn32_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
|
||||
{
|
||||
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
|
||||
WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
|
||||
|
||||
if (!clk_mgr->smu_present)
|
||||
return;
|
||||
|
||||
if (!table)
|
||||
return;
|
||||
|
||||
memset(table, 0, sizeof(*table));
|
||||
|
||||
dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);
|
||||
dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF);
|
||||
dcn32_smu_transfer_wm_table_dram_2_smu(clk_mgr);
|
||||
}
|
||||
|
||||
/* Set min memclk to minimum, either constrained by the current mode or DPM0 */
|
||||
static void dcn32_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)
|
||||
{
|
||||
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
|
||||
|
||||
if (!clk_mgr->smu_present)
|
||||
return;
|
||||
|
||||
if (current_mode) {
|
||||
if (clk_mgr_base->clks.p_state_change_support)
|
||||
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
|
||||
khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
|
||||
else
|
||||
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
|
||||
clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
|
||||
} else {
|
||||
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
|
||||
clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
|
||||
}
|
||||
}
|
||||
|
||||
/* Set max memclk to highest DPM value */
|
||||
static void dcn32_set_hard_max_memclk(struct clk_mgr *clk_mgr_base)
|
||||
{
|
||||
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
|
||||
|
||||
if (!clk_mgr->smu_present)
|
||||
return;
|
||||
|
||||
dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,
|
||||
clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
|
||||
}
|
||||
|
||||
/* Get current memclk states, update bounding box */
|
||||
static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
|
||||
{
|
||||
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
|
||||
unsigned int num_levels;
|
||||
|
||||
if (!clk_mgr->smu_present)
|
||||
return;
|
||||
|
||||
/* Refresh memclk states */
|
||||
dcn32_init_single_clock(clk_mgr, PPCLK_UCLK,
|
||||
&clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
|
||||
&num_levels);
|
||||
clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1;
|
||||
|
||||
/* Refresh bounding box */
|
||||
clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(
|
||||
clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);
|
||||
}
|
||||
|
||||
static bool dcn32_are_clock_states_equal(struct dc_clocks *a,
|
||||
struct dc_clocks *b)
|
||||
{
|
||||
if (a->dispclk_khz != b->dispclk_khz)
|
||||
return false;
|
||||
else if (a->dppclk_khz != b->dppclk_khz)
|
||||
return false;
|
||||
else if (a->dcfclk_khz != b->dcfclk_khz)
|
||||
return false;
|
||||
else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
|
||||
return false;
|
||||
else if (a->dramclk_khz != b->dramclk_khz)
|
||||
return false;
|
||||
else if (a->p_state_change_support != b->p_state_change_support)
|
||||
return false;
|
||||
else if (a->fclk_p_state_change_support != b->fclk_p_state_change_support)
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static void dcn32_enable_pme_wa(struct clk_mgr *clk_mgr_base)
|
||||
{
|
||||
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
|
||||
|
||||
if (!clk_mgr->smu_present)
|
||||
return;
|
||||
|
||||
dcn30_smu_set_pme_workaround(clk_mgr);
|
||||
}
|
||||
|
||||
static bool dcn32_is_smu_present(struct clk_mgr *clk_mgr_base)
|
||||
{
|
||||
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
|
||||
return clk_mgr->smu_present;
|
||||
}
|
||||
|
||||
|
||||
static struct clk_mgr_funcs dcn32_funcs = {
|
||||
.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
|
||||
.update_clocks = dcn32_update_clocks,
|
||||
.init_clocks = dcn32_init_clocks,
|
||||
.notify_wm_ranges = dcn32_notify_wm_ranges,
|
||||
.set_hard_min_memclk = dcn32_set_hard_min_memclk,
|
||||
.set_hard_max_memclk = dcn32_set_hard_max_memclk,
|
||||
.get_memclk_states_from_smu = dcn32_get_memclk_states_from_smu,
|
||||
.are_clock_states_equal = dcn32_are_clock_states_equal,
|
||||
.enable_pme_wa = dcn32_enable_pme_wa,
|
||||
.is_smu_present = dcn32_is_smu_present,
|
||||
};
|
||||
|
||||
void dcn32_clk_mgr_construct(
|
||||
struct dc_context *ctx,
|
||||
struct clk_mgr_internal *clk_mgr,
|
||||
struct pp_smu_funcs *pp_smu,
|
||||
struct dccg *dccg)
|
||||
{
|
||||
clk_mgr->base.ctx = ctx;
|
||||
clk_mgr->base.funcs = &dcn32_funcs;
|
||||
if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) {
|
||||
clk_mgr->regs = &clk_mgr_regs_dcn321;
|
||||
clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn321;
|
||||
clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn321;
|
||||
} else {
|
||||
clk_mgr->regs = &clk_mgr_regs_dcn32;
|
||||
clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn32;
|
||||
clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn32;
|
||||
}
|
||||
|
||||
clk_mgr->dccg = dccg;
|
||||
clk_mgr->dfs_bypass_disp_clk = 0;
|
||||
|
||||
clk_mgr->dprefclk_ss_percentage = 0;
|
||||
clk_mgr->dprefclk_ss_divider = 1000;
|
||||
clk_mgr->ss_on_dprefclk = false;
|
||||
clk_mgr->dfs_ref_freq_khz = 100000;
|
||||
|
||||
clk_mgr->base.dprefclk_khz = 717000; /* Changed as per DCN3.2_clock_frequency doc */
|
||||
clk_mgr->dccg->ref_dtbclk_khz = 477800;
|
||||
|
||||
/* integer part is now VCO frequency in kHz */
|
||||
clk_mgr->base.dentist_vco_freq_khz = 4300000;//dcn32_get_vco_frequency_from_reg(clk_mgr);
|
||||
/* in case we don't get a value from the register, use default */
|
||||
if (clk_mgr->base.dentist_vco_freq_khz == 0)
|
||||
clk_mgr->base.dentist_vco_freq_khz = 4300000; /* Updated as per HW docs */
|
||||
|
||||
if (clk_mgr->base.boot_snapshot.dprefclk != 0) {
|
||||
//ASSERT(clk_mgr->base.dprefclk_khz == clk_mgr->base.boot_snapshot.dprefclk);
|
||||
//clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk;
|
||||
}
|
||||
dcn32_clock_read_ss_info(clk_mgr);
|
||||
|
||||
clk_mgr->dfs_bypass_enabled = false;
|
||||
|
||||
clk_mgr->smu_present = false;
|
||||
|
||||
clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL);
|
||||
|
||||
/* need physical address of table to give to PMFW */
|
||||
clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,
|
||||
DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),
|
||||
&clk_mgr->wm_range_table_addr);
|
||||
}
|
||||
|
||||
void dcn32_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
|
||||
{
|
||||
if (clk_mgr->base.bw_params)
|
||||
kfree(clk_mgr->base.bw_params);
|
||||
|
||||
if (clk_mgr->wm_range_table)
|
||||
dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,
|
||||
clk_mgr->wm_range_table);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* Copyright 2021 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
#ifndef __DCN32_CLK_MGR_H_
|
||||
#define __DCN32_CLK_MGR_H_
|
||||
|
||||
void dcn32_init_clocks(struct clk_mgr *clk_mgr_base);
|
||||
|
||||
void dcn32_clk_mgr_construct(struct dc_context *ctx,
|
||||
struct clk_mgr_internal *clk_mgr,
|
||||
struct pp_smu_funcs *pp_smu,
|
||||
struct dccg *dccg);
|
||||
|
||||
void dcn32_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);
|
||||
|
||||
|
||||
|
||||
#endif /* __DCN32_CLK_MGR_H_ */
|
||||
|
|
@ -0,0 +1,117 @@
|
|||
/*
|
||||
* Copyright 2021 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
|
||||
#include "dcn32_clk_mgr_smu_msg.h"
|
||||
|
||||
#include "clk_mgr_internal.h"
|
||||
#include "reg_helper.h"
|
||||
|
||||
#define mmDAL_MSG_REG 0x1628A
|
||||
#define mmDAL_ARG_REG 0x16273
|
||||
#define mmDAL_RESP_REG 0x16274
|
||||
|
||||
#define DALSMC_MSG_TransferTableDram2Smu 0x8
|
||||
|
||||
#define REG(reg_name) \
|
||||
mm ## reg_name
|
||||
|
||||
#include "logger_types.h"
|
||||
#include "dalsmc.h"
|
||||
#include "smu13_driver_if.h"
|
||||
|
||||
#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
|
||||
|
||||
|
||||
/*
|
||||
* Function to be used instead of REG_WAIT macro because the wait ends when
|
||||
* the register is NOT EQUAL to zero, and because the translation in msg_if.h
|
||||
* won't work with REG_WAIT.
|
||||
*/
|
||||
static uint32_t dcn32_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
|
||||
{
|
||||
uint32_t reg = 0;
|
||||
|
||||
do {
|
||||
reg = REG_READ(DAL_RESP_REG);
|
||||
if (reg)
|
||||
break;
|
||||
|
||||
if (delay_us >= 1000)
|
||||
msleep(delay_us/1000);
|
||||
else if (delay_us > 0)
|
||||
udelay(delay_us);
|
||||
} while (max_retries--);
|
||||
|
||||
return reg;
|
||||
}
|
||||
|
||||
static bool dcn32_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out)
|
||||
{
|
||||
/* Wait for response register to be ready */
|
||||
dcn32_smu_wait_for_response(clk_mgr, 10, 200000);
|
||||
|
||||
/* Clear response register */
|
||||
REG_WRITE(DAL_RESP_REG, 0);
|
||||
|
||||
/* Set the parameter register for the SMU message */
|
||||
REG_WRITE(DAL_ARG_REG, param_in);
|
||||
|
||||
/* Trigger the message transaction by writing the message ID */
|
||||
REG_WRITE(DAL_MSG_REG, msg_id);
|
||||
|
||||
/* Wait for response */
|
||||
if (dcn32_smu_wait_for_response(clk_mgr, 10, 200000) == DALSMC_Result_OK) {
|
||||
if (param_out)
|
||||
*param_out = REG_READ(DAL_ARG_REG);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
void dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable)
|
||||
{
|
||||
smu_print("FCLK P-state support value is : %d\n", enable);
|
||||
|
||||
dcn32_smu_send_msg_with_param(clk_mgr,
|
||||
DALSMC_MSG_SetFclkSwitchAllow, enable ? FCLK_PSTATE_SUPPORTED : FCLK_PSTATE_NOTSUPPORTED, NULL);
|
||||
}
|
||||
|
||||
void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
|
||||
{
|
||||
smu_print("SMU Transfer WM table DRAM 2 SMU\n");
|
||||
|
||||
dcn32_smu_send_msg_with_param(clk_mgr,
|
||||
DALSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS, NULL);
|
||||
}
|
||||
|
||||
void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways)
|
||||
{
|
||||
smu_print("Numways for SubVP : %d\n", num_ways);
|
||||
|
||||
dcn32_smu_send_msg_with_param(clk_mgr, DALSMC_MSG_SetCabForUclkPstate, num_ways, NULL);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
* Copyright 2021 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DCN32_CLK_MGR_SMU_MSG_H_
|
||||
#define __DCN32_CLK_MGR_SMU_MSG_H_
|
||||
|
||||
#include "core_types.h"
|
||||
#include "dcn30/dcn30_clk_mgr_smu_msg.h"
|
||||
|
||||
#define FCLK_PSTATE_NOTSUPPORTED 0x00
|
||||
#define FCLK_PSTATE_SUPPORTED 0x01
|
||||
|
||||
/* TODO Remove this MSG ID define after it becomes available in dalsmc */
|
||||
#define DALSMC_MSG_SetFclkSwitchAllow 0x11
|
||||
#define DALSMC_MSG_SetCabForUclkPstate 0x12
|
||||
#define DALSMC_Result_OK 0x1
|
||||
|
||||
void
|
||||
dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr,
|
||||
bool enable);
|
||||
|
||||
void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
|
||||
|
||||
void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways);
|
||||
|
||||
|
||||
#endif /* __DCN32_CLK_MGR_SMU_MSG_H_ */
|
||||
|
|
@ -0,0 +1,108 @@
|
|||
/*
|
||||
* Copyright 2021 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
#ifndef SMU13_DRIVER_IF_DCN32_H
|
||||
#define SMU13_DRIVER_IF_DCN32_H
|
||||
|
||||
// *** IMPORTANT ***
|
||||
// PMFW TEAM: Always increment the interface version on any change to this file
|
||||
#define SMU13_DRIVER_IF_VERSION 0x18
|
||||
|
||||
//Only Clks that have DPM descriptors are listed here
|
||||
typedef enum {
|
||||
PPCLK_GFXCLK = 0,
|
||||
PPCLK_SOCCLK,
|
||||
PPCLK_UCLK,
|
||||
PPCLK_FCLK,
|
||||
PPCLK_DCLK_0,
|
||||
PPCLK_VCLK_0,
|
||||
PPCLK_DCLK_1,
|
||||
PPCLK_VCLK_1,
|
||||
PPCLK_DISPCLK,
|
||||
PPCLK_DPPCLK,
|
||||
PPCLK_DPREFCLK,
|
||||
PPCLK_DCFCLK,
|
||||
PPCLK_DTBCLK,
|
||||
PPCLK_COUNT,
|
||||
} PPCLK_e;
|
||||
|
||||
typedef enum {
|
||||
UCLK_DIV_BY_1 = 0,
|
||||
UCLK_DIV_BY_2,
|
||||
UCLK_DIV_BY_4,
|
||||
UCLK_DIV_BY_8,
|
||||
} UCLK_DIV_e;
|
||||
|
||||
typedef struct {
|
||||
uint8_t WmSetting;
|
||||
uint8_t Flags;
|
||||
uint8_t Padding[2];
|
||||
|
||||
} WatermarkRowGeneric_t;
|
||||
|
||||
#define NUM_WM_RANGES 4
|
||||
|
||||
typedef enum {
|
||||
WATERMARKS_CLOCK_RANGE = 0,
|
||||
WATERMARKS_DUMMY_PSTATE,
|
||||
WATERMARKS_MALL,
|
||||
WATERMARKS_COUNT,
|
||||
} WATERMARKS_FLAGS_e;
|
||||
|
||||
typedef struct {
|
||||
// Watermarks
|
||||
WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES];
|
||||
} Watermarks_t;
|
||||
|
||||
typedef struct {
|
||||
Watermarks_t Watermarks;
|
||||
uint32_t Spare[16];
|
||||
|
||||
uint32_t MmHubPadding[8]; // SMU internal use
|
||||
} WatermarksExternal_t;
|
||||
|
||||
// These defines are used with the following messages:
|
||||
// SMC_MSG_TransferTableDram2Smu
|
||||
// SMC_MSG_TransferTableSmu2Dram
|
||||
|
||||
// Table transfer status
|
||||
#define TABLE_TRANSFER_OK 0x0
|
||||
#define TABLE_TRANSFER_FAILED 0xFF
|
||||
#define TABLE_TRANSFER_PENDING 0xAB
|
||||
|
||||
// Table types
|
||||
#define TABLE_PMFW_PPTABLE 0
|
||||
#define TABLE_COMBO_PPTABLE 1
|
||||
#define TABLE_WATERMARKS 2
|
||||
#define TABLE_AVFS_PSM_DEBUG 3
|
||||
#define TABLE_PMSTATUSLOG 4
|
||||
#define TABLE_SMU_METRICS 5
|
||||
#define TABLE_DRIVER_SMU_CONFIG 6
|
||||
#define TABLE_ACTIVITY_MONITOR_COEFF 7
|
||||
#define TABLE_OVERDRIVE 8
|
||||
#define TABLE_I2C_COMMANDS 9
|
||||
#define TABLE_DRIVER_INFO 10
|
||||
#define TABLE_COUNT 11
|
||||
|
||||
#endif
|
||||
|
|
@ -3975,6 +3975,9 @@ static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_
|
|||
return true;
|
||||
}
|
||||
|
||||
bool FORCE_RATE = false;
|
||||
uint32_t FORCE_LANE_COUNT = 0;
|
||||
|
||||
void decide_link_settings(struct dc_stream_state *stream,
|
||||
struct dc_link_settings *link_setting)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -418,12 +418,15 @@ struct dc_clocks {
|
|||
enum dcn_zstate_support_state zstate_support;
|
||||
bool dtbclk_en;
|
||||
int ref_dtbclk_khz;
|
||||
int dtbclk_khz;
|
||||
bool fclk_p_state_change_support;
|
||||
enum dcn_pwr_state pwr_state;
|
||||
/*
|
||||
* Elements below are not compared for the purposes of
|
||||
* optimization required
|
||||
*/
|
||||
bool prev_p_state_change_support;
|
||||
bool fclk_prev_p_state_change_support;
|
||||
enum dtm_pstate dtm_level;
|
||||
int max_supported_dppclk_khz;
|
||||
int max_supported_dispclk_khz;
|
||||
|
|
|
|||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -125,6 +125,7 @@ struct nv_wm_range_entry {
|
|||
double pstate_latency_us;
|
||||
double sr_exit_time_us;
|
||||
double sr_enter_plus_exit_time_us;
|
||||
double fclk_change_latency_us;
|
||||
} dml_input;
|
||||
};
|
||||
|
||||
|
|
@ -142,6 +143,7 @@ struct clk_state_registers_and_bypass {
|
|||
uint32_t dprefclk;
|
||||
uint32_t dispclk;
|
||||
uint32_t dppclk;
|
||||
uint32_t dtbclk;
|
||||
|
||||
uint32_t dppclk_bypass;
|
||||
uint32_t dcfclk_bypass;
|
||||
|
|
|
|||
|
|
@ -112,9 +112,10 @@ enum dentist_divider_range {
|
|||
CLK_SRI(CLK3_CLK_PLL_REQ, CLK3, 0), \
|
||||
CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0)
|
||||
|
||||
// TODO:
|
||||
#define CLK_REG_LIST_DCN3() \
|
||||
SR(DENTIST_DISPCLK_CNTL)
|
||||
CLK_COMMON_REG_LIST_DCN_BASE(), \
|
||||
CLK_SRI(CLK0_CLK_PLL_REQ, CLK02, 0), \
|
||||
CLK_SRI(CLK0_CLK2_DFS_CNTL, CLK02, 0)
|
||||
|
||||
#define CLK_SF(reg_name, field_name, post_fix)\
|
||||
.field_name = reg_name ## __ ## field_name ## post_fix
|
||||
|
|
@ -155,6 +156,34 @@ enum dentist_divider_range {
|
|||
CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, mask_sh),\
|
||||
CLK_SF(CLK4_0_CLK4_CLK_PLL_REQ, FbMult_int, mask_sh)
|
||||
|
||||
#define CLK_REG_LIST_DCN32() \
|
||||
SR(DENTIST_DISPCLK_CNTL), \
|
||||
CLK_SR_DCN32(CLK1_CLK_PLL_REQ), \
|
||||
CLK_SR_DCN32(CLK1_CLK0_DFS_CNTL), \
|
||||
CLK_SR_DCN32(CLK1_CLK1_DFS_CNTL), \
|
||||
CLK_SR_DCN32(CLK1_CLK2_DFS_CNTL), \
|
||||
CLK_SR_DCN32(CLK1_CLK3_DFS_CNTL), \
|
||||
CLK_SR_DCN32(CLK1_CLK4_DFS_CNTL)
|
||||
|
||||
#define CLK_COMMON_MASK_SH_LIST_DCN32(mask_sh) \
|
||||
CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\
|
||||
CLK_SF(CLK1_CLK_PLL_REQ, FbMult_int, mask_sh),\
|
||||
CLK_SF(CLK1_CLK_PLL_REQ, FbMult_frac, mask_sh)
|
||||
|
||||
#define CLK_REG_LIST_DCN321() \
|
||||
SR(DENTIST_DISPCLK_CNTL), \
|
||||
CLK_SR_DCN321(CLK0_CLK_PLL_REQ, CLK01, 0), \
|
||||
CLK_SR_DCN321(CLK0_CLK0_DFS_CNTL, CLK01, 0), \
|
||||
CLK_SR_DCN321(CLK0_CLK1_DFS_CNTL, CLK01, 0), \
|
||||
CLK_SR_DCN321(CLK0_CLK2_DFS_CNTL, CLK01, 0), \
|
||||
CLK_SR_DCN321(CLK0_CLK3_DFS_CNTL, CLK01, 0), \
|
||||
CLK_SR_DCN321(CLK0_CLK4_DFS_CNTL, CLK01, 0)
|
||||
|
||||
#define CLK_COMMON_MASK_SH_LIST_DCN321(mask_sh) \
|
||||
CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\
|
||||
CLK_SF(CLK0_CLK_PLL_REQ, FbMult_int, mask_sh),\
|
||||
CLK_SF(CLK0_CLK_PLL_REQ, FbMult_frac, mask_sh)
|
||||
|
||||
#define CLK_REG_FIELD_LIST(type) \
|
||||
type DPREFCLK_SRC_SEL; \
|
||||
type DENTIST_DPREFCLK_WDIVIDER; \
|
||||
|
|
@ -199,6 +228,18 @@ struct clk_mgr_registers {
|
|||
uint32_t CLK0_CLK2_DFS_CNTL;
|
||||
uint32_t CLK0_CLK_PLL_REQ;
|
||||
|
||||
uint32_t CLK1_CLK_PLL_REQ;
|
||||
uint32_t CLK1_CLK0_DFS_CNTL;
|
||||
uint32_t CLK1_CLK1_DFS_CNTL;
|
||||
uint32_t CLK1_CLK2_DFS_CNTL;
|
||||
uint32_t CLK1_CLK3_DFS_CNTL;
|
||||
uint32_t CLK1_CLK4_DFS_CNTL;
|
||||
|
||||
uint32_t CLK0_CLK0_DFS_CNTL;
|
||||
uint32_t CLK0_CLK1_DFS_CNTL;
|
||||
uint32_t CLK0_CLK3_DFS_CNTL;
|
||||
uint32_t CLK0_CLK4_DFS_CNTL;
|
||||
|
||||
uint32_t MP1_SMN_C2PMSG_67;
|
||||
uint32_t MP1_SMN_C2PMSG_83;
|
||||
uint32_t MP1_SMN_C2PMSG_91;
|
||||
|
|
|
|||
Загрузка…
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