Merge branch 'pm-cpufreq'
Additional cpufreq updates for 4.18-rc1: fixes and cleanups in the core and drivers and intel_pstate extension to do iowait boosting on systems with HWP that improves performance quite a bit. * pm-cpufreq: cpufreq: imx6q: check speed grades for i.MX6ULL cpufreq: governors: Fix long idle detection logic in load calculation cpufreq: intel_pstate: enable boost for Skylake Xeon cpufreq: intel_pstate: New sysfs entry to control HWP boost cpufreq: intel_pstate: HWP boost performance on IO wakeup cpufreq: intel_pstate: Add HWP boost utility and sched util hooks cpufreq: ti-cpufreq: Use devres managed API in probe() cpufreq: ti-cpufreq: Fix an incorrect error return value cpufreq: ACPI: make function acpi_cpufreq_fast_switch() static cpufreq: kryo: allow building as a loadable module
This commit is contained in:
Rafael J. Wysocki
Коммит
2652df3af7
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@ -125,7 +125,7 @@ config ARM_OMAP2PLUS_CPUFREQ
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default ARCH_OMAP2PLUS
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config ARM_QCOM_CPUFREQ_KRYO
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bool "Qualcomm Kryo based CPUFreq"
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tristate "Qualcomm Kryo based CPUFreq"
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depends on ARM64
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depends on QCOM_QFPROM
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depends on QCOM_SMEM
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@ -465,8 +465,8 @@ static int acpi_cpufreq_target(struct cpufreq_policy *policy,
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return result;
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}
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unsigned int acpi_cpufreq_fast_switch(struct cpufreq_policy *policy,
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unsigned int target_freq)
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static unsigned int acpi_cpufreq_fast_switch(struct cpufreq_policy *policy,
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unsigned int target_freq)
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{
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struct acpi_cpufreq_data *data = policy->driver_data;
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struct acpi_processor_performance *perf;
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@ -165,7 +165,7 @@ unsigned int dbs_update(struct cpufreq_policy *policy)
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* calls, so the previous load value can be used then.
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*/
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load = j_cdbs->prev_load;
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} else if (unlikely(time_elapsed > 2 * sampling_rate &&
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} else if (unlikely((int)idle_time > 2 * sampling_rate &&
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j_cdbs->prev_load)) {
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/*
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* If the CPU had gone completely idle and a task has
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@ -185,10 +185,8 @@ unsigned int dbs_update(struct cpufreq_policy *policy)
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* clear prev_load to guarantee that the load will be
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* computed again next time.
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*
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* Detecting this situation is easy: the governor's
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* utilization update handler would not have run during
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* CPU-idle periods. Hence, an unusually large
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* 'time_elapsed' (as compared to the sampling rate)
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* Detecting this situation is easy: an unusually large
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* 'idle_time' (as compared to the sampling rate)
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* indicates this scenario.
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*/
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load = j_cdbs->prev_load;
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@ -217,8 +215,8 @@ unsigned int dbs_update(struct cpufreq_policy *policy)
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j_cdbs->prev_load = load;
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}
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if (time_elapsed > 2 * sampling_rate) {
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unsigned int periods = time_elapsed / sampling_rate;
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if (unlikely((int)idle_time > 2 * sampling_rate)) {
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unsigned int periods = idle_time / sampling_rate;
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if (periods < idle_periods)
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idle_periods = periods;
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@ -266,6 +266,8 @@ put_node:
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}
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#define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2
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#define OCOTP_CFG3_6ULL_SPEED_792MHZ 0x2
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#define OCOTP_CFG3_6ULL_SPEED_900MHZ 0x3
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static void imx6ul_opp_check_speed_grading(struct device *dev)
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{
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@ -287,16 +289,30 @@ static void imx6ul_opp_check_speed_grading(struct device *dev)
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* Speed GRADING[1:0] defines the max speed of ARM:
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* 2b'00: Reserved;
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* 2b'01: 528000000Hz;
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* 2b'10: 696000000Hz;
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* 2b'11: Reserved;
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* 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL;
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* 2b'11: 900000000Hz on i.MX6ULL only;
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* We need to set the max speed of ARM according to fuse map.
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*/
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val = readl_relaxed(base + OCOTP_CFG3);
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val >>= OCOTP_CFG3_SPEED_SHIFT;
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val &= 0x3;
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if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
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if (dev_pm_opp_disable(dev, 696000000))
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dev_warn(dev, "failed to disable 696MHz OPP\n");
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if (of_machine_is_compatible("fsl,imx6ul")) {
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if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
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if (dev_pm_opp_disable(dev, 696000000))
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dev_warn(dev, "failed to disable 696MHz OPP\n");
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}
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if (of_machine_is_compatible("fsl,imx6ull")) {
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if (val != OCOTP_CFG3_6ULL_SPEED_792MHZ)
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if (dev_pm_opp_disable(dev, 792000000))
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dev_warn(dev, "failed to disable 792MHz OPP\n");
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if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ)
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if (dev_pm_opp_disable(dev, 900000000))
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dev_warn(dev, "failed to disable 900MHz OPP\n");
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}
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iounmap(base);
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put_node:
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of_node_put(np);
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@ -356,7 +372,8 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev)
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goto put_reg;
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}
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if (of_machine_is_compatible("fsl,imx6ul"))
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if (of_machine_is_compatible("fsl,imx6ul") ||
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of_machine_is_compatible("fsl,imx6ull"))
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imx6ul_opp_check_speed_grading(cpu_dev);
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else
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imx6q_opp_check_speed_grading(cpu_dev);
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@ -221,6 +221,11 @@ struct global_params {
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* preference/bias
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* @epp_saved: Saved EPP/EPB during system suspend or CPU offline
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* operation
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* @hwp_req_cached: Cached value of the last HWP Request MSR
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* @hwp_cap_cached: Cached value of the last HWP Capabilities MSR
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* @last_io_update: Last time when IO wake flag was set
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* @sched_flags: Store scheduler flags for possible cross CPU update
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* @hwp_boost_min: Last HWP boosted min performance
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*
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* This structure stores per CPU instance data for all CPUs.
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*/
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@ -253,6 +258,11 @@ struct cpudata {
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s16 epp_policy;
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s16 epp_default;
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s16 epp_saved;
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u64 hwp_req_cached;
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u64 hwp_cap_cached;
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u64 last_io_update;
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unsigned int sched_flags;
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u32 hwp_boost_min;
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};
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static struct cpudata **all_cpu_data;
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@ -285,6 +295,7 @@ static struct pstate_funcs pstate_funcs __read_mostly;
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static int hwp_active __read_mostly;
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static bool per_cpu_limits __read_mostly;
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static bool hwp_boost __read_mostly;
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static struct cpufreq_driver *intel_pstate_driver __read_mostly;
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@ -689,6 +700,7 @@ static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max,
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u64 cap;
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rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
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WRITE_ONCE(all_cpu_data[cpu]->hwp_cap_cached, cap);
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if (global.no_turbo)
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*current_max = HWP_GUARANTEED_PERF(cap);
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else
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@ -763,6 +775,7 @@ update_epp:
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intel_pstate_set_epb(cpu, epp);
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}
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skip_epp:
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WRITE_ONCE(cpu_data->hwp_req_cached, value);
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wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
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}
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@ -1020,6 +1033,30 @@ static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
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return count;
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}
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static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
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struct attribute *attr, char *buf)
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{
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return sprintf(buf, "%u\n", hwp_boost);
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}
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static ssize_t store_hwp_dynamic_boost(struct kobject *a, struct attribute *b,
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const char *buf, size_t count)
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{
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unsigned int input;
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int ret;
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ret = kstrtouint(buf, 10, &input);
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if (ret)
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return ret;
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mutex_lock(&intel_pstate_driver_lock);
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hwp_boost = !!input;
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intel_pstate_update_policies();
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mutex_unlock(&intel_pstate_driver_lock);
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return count;
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}
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show_one(max_perf_pct, max_perf_pct);
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show_one(min_perf_pct, min_perf_pct);
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@ -1029,6 +1066,7 @@ define_one_global_rw(max_perf_pct);
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define_one_global_rw(min_perf_pct);
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define_one_global_ro(turbo_pct);
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define_one_global_ro(num_pstates);
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define_one_global_rw(hwp_dynamic_boost);
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static struct attribute *intel_pstate_attributes[] = {
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&status.attr,
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@ -1069,6 +1107,11 @@ static void __init intel_pstate_sysfs_expose_params(void)
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rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
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WARN_ON(rc);
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if (hwp_active) {
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rc = sysfs_create_file(intel_pstate_kobject,
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&hwp_dynamic_boost.attr);
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WARN_ON(rc);
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}
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}
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/************************** sysfs end ************************/
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@ -1381,6 +1424,116 @@ static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
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intel_pstate_set_min_pstate(cpu);
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}
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/*
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* Long hold time will keep high perf limits for long time,
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* which negatively impacts perf/watt for some workloads,
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* like specpower. 3ms is based on experiements on some
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* workoads.
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*/
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static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
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static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
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{
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u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
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u32 max_limit = (hwp_req & 0xff00) >> 8;
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u32 min_limit = (hwp_req & 0xff);
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u32 boost_level1;
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/*
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* Cases to consider (User changes via sysfs or boot time):
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* If, P0 (Turbo max) = P1 (Guaranteed max) = min:
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* No boost, return.
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* If, P0 (Turbo max) > P1 (Guaranteed max) = min:
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* Should result in one level boost only for P0.
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* If, P0 (Turbo max) = P1 (Guaranteed max) > min:
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* Should result in two level boost:
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* (min + p1)/2 and P1.
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* If, P0 (Turbo max) > P1 (Guaranteed max) > min:
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* Should result in three level boost:
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* (min + p1)/2, P1 and P0.
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*/
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/* If max and min are equal or already at max, nothing to boost */
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if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
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return;
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if (!cpu->hwp_boost_min)
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cpu->hwp_boost_min = min_limit;
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/* level at half way mark between min and guranteed */
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boost_level1 = (HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) + min_limit) >> 1;
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if (cpu->hwp_boost_min < boost_level1)
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cpu->hwp_boost_min = boost_level1;
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else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
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cpu->hwp_boost_min = HWP_GUARANTEED_PERF(cpu->hwp_cap_cached);
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else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) &&
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max_limit != HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
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cpu->hwp_boost_min = max_limit;
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else
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return;
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hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
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wrmsrl(MSR_HWP_REQUEST, hwp_req);
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cpu->last_update = cpu->sample.time;
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}
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|
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static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
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{
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if (cpu->hwp_boost_min) {
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bool expired;
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|
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/* Check if we are idle for hold time to boost down */
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expired = time_after64(cpu->sample.time, cpu->last_update +
|
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hwp_boost_hold_time_ns);
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if (expired) {
|
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wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
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cpu->hwp_boost_min = 0;
|
||||
}
|
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}
|
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cpu->last_update = cpu->sample.time;
|
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}
|
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|
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static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
|
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u64 time)
|
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{
|
||||
cpu->sample.time = time;
|
||||
|
||||
if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
|
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bool do_io = false;
|
||||
|
||||
cpu->sched_flags = 0;
|
||||
/*
|
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* Set iowait_boost flag and update time. Since IO WAIT flag
|
||||
* is set all the time, we can't just conclude that there is
|
||||
* some IO bound activity is scheduled on this CPU with just
|
||||
* one occurrence. If we receive at least two in two
|
||||
* consecutive ticks, then we treat as boost candidate.
|
||||
*/
|
||||
if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
|
||||
do_io = true;
|
||||
|
||||
cpu->last_io_update = time;
|
||||
|
||||
if (do_io)
|
||||
intel_pstate_hwp_boost_up(cpu);
|
||||
|
||||
} else {
|
||||
intel_pstate_hwp_boost_down(cpu);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
|
||||
u64 time, unsigned int flags)
|
||||
{
|
||||
struct cpudata *cpu = container_of(data, struct cpudata, update_util);
|
||||
|
||||
cpu->sched_flags |= flags;
|
||||
|
||||
if (smp_processor_id() == cpu->cpu)
|
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intel_pstate_update_util_hwp_local(cpu, time);
|
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}
|
||||
|
||||
static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
|
||||
{
|
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struct sample *sample = &cpu->sample;
|
||||
|
|
@ -1641,6 +1794,12 @@ static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
|
|||
{}
|
||||
};
|
||||
|
||||
static const struct x86_cpu_id intel_pstate_hwp_boost_ids[] = {
|
||||
ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
|
||||
ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs),
|
||||
{}
|
||||
};
|
||||
|
||||
static int intel_pstate_init_cpu(unsigned int cpunum)
|
||||
{
|
||||
struct cpudata *cpu;
|
||||
|
|
@ -1671,6 +1830,10 @@ static int intel_pstate_init_cpu(unsigned int cpunum)
|
|||
intel_pstate_disable_ee(cpunum);
|
||||
|
||||
intel_pstate_hwp_enable(cpu);
|
||||
|
||||
id = x86_match_cpu(intel_pstate_hwp_boost_ids);
|
||||
if (id)
|
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hwp_boost = true;
|
||||
}
|
||||
|
||||
intel_pstate_get_cpu_pstates(cpu);
|
||||
|
|
@ -1684,7 +1847,7 @@ static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
|
|||
{
|
||||
struct cpudata *cpu = all_cpu_data[cpu_num];
|
||||
|
||||
if (hwp_active)
|
||||
if (hwp_active && !hwp_boost)
|
||||
return;
|
||||
|
||||
if (cpu->update_util_set)
|
||||
|
|
@ -1693,7 +1856,9 @@ static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
|
|||
/* Prevent intel_pstate_update_util() from using stale data. */
|
||||
cpu->sample.time = 0;
|
||||
cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
|
||||
intel_pstate_update_util);
|
||||
(hwp_active ?
|
||||
intel_pstate_update_util_hwp :
|
||||
intel_pstate_update_util));
|
||||
cpu->update_util_set = true;
|
||||
}
|
||||
|
||||
|
|
@ -1805,8 +1970,16 @@ static int intel_pstate_set_policy(struct cpufreq_policy *policy)
|
|||
intel_pstate_set_update_util_hook(policy->cpu);
|
||||
}
|
||||
|
||||
if (hwp_active)
|
||||
if (hwp_active) {
|
||||
/*
|
||||
* When hwp_boost was active before and dynamically it
|
||||
* was turned off, in that case we need to clear the
|
||||
* update util hook.
|
||||
*/
|
||||
if (!hwp_boost)
|
||||
intel_pstate_clear_update_util_hook(policy->cpu);
|
||||
intel_pstate_hwp_set(policy->cpu);
|
||||
}
|
||||
|
||||
mutex_unlock(&intel_pstate_limits_lock);
|
||||
|
||||
|
|
|
|||
|
|
@ -217,7 +217,7 @@ static int ti_cpufreq_probe(struct platform_device *pdev)
|
|||
if (!match)
|
||||
return -ENODEV;
|
||||
|
||||
opp_data = kzalloc(sizeof(*opp_data), GFP_KERNEL);
|
||||
opp_data = devm_kzalloc(&pdev->dev, sizeof(*opp_data), GFP_KERNEL);
|
||||
if (!opp_data)
|
||||
return -ENOMEM;
|
||||
|
||||
|
|
@ -226,8 +226,7 @@ static int ti_cpufreq_probe(struct platform_device *pdev)
|
|||
opp_data->cpu_dev = get_cpu_device(0);
|
||||
if (!opp_data->cpu_dev) {
|
||||
pr_err("%s: Failed to get device for CPU0\n", __func__);
|
||||
ret = ENODEV;
|
||||
goto free_opp_data;
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
opp_data->opp_node = dev_pm_opp_of_get_opp_desc_node(opp_data->cpu_dev);
|
||||
|
|
@ -285,8 +284,6 @@ register_cpufreq_dt:
|
|||
|
||||
fail_put_node:
|
||||
of_node_put(opp_data->opp_node);
|
||||
free_opp_data:
|
||||
kfree(opp_data);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
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