PCI: Make Enhanced Allocation bitmasks more obvious
Expand bitmask #defines completely. This puts the shift in the code instead of in the #define, but it makes it more obvious in the header file how fields in the register are laid out. No functional change. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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111839917f
Коммит
26635112d4
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@ -2195,7 +2195,7 @@ static int pci_ea_read(struct pci_dev *dev, int offset)
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int ent_size, ent_offset = offset;
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int ent_size, ent_offset = offset;
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resource_size_t start, end;
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resource_size_t start, end;
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unsigned long flags;
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unsigned long flags;
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u32 dw0, base, max_offset;
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u32 dw0, bei, base, max_offset;
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u8 prop;
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u8 prop;
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bool support_64 = (sizeof(resource_size_t) >= 8);
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bool support_64 = (sizeof(resource_size_t) >= 8);
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@ -2208,20 +2208,21 @@ static int pci_ea_read(struct pci_dev *dev, int offset)
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if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
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if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
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goto out;
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goto out;
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prop = PCI_EA_PP(dw0);
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bei = (dw0 & PCI_EA_BEI) >> 4;
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prop = (dw0 & PCI_EA_PP) >> 8;
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/*
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/*
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* If the Property is in the reserved range, try the Secondary
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* If the Property is in the reserved range, try the Secondary
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* Property instead.
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* Property instead.
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*/
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*/
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if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
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if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
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prop = PCI_EA_SP(dw0);
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prop = (dw0 & PCI_EA_SP) >> 16;
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if (prop > PCI_EA_P_BRIDGE_IO)
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if (prop > PCI_EA_P_BRIDGE_IO)
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goto out;
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goto out;
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res = pci_ea_get_resource(dev, PCI_EA_BEI(dw0), prop);
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res = pci_ea_get_resource(dev, bei, prop);
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if (!res) {
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if (!res) {
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dev_err(&dev->dev, "Unsupported EA entry BEI: %u\n",
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dev_err(&dev->dev, "Unsupported EA entry BEI: %u\n", bei);
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PCI_EA_BEI(dw0));
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goto out;
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goto out;
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}
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}
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@ -2293,7 +2294,7 @@ static int pci_ea_read(struct pci_dev *dev, int offset)
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res->end = end;
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res->end = end;
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res->flags = flags;
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res->flags = flags;
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dev_printk(KERN_DEBUG, &dev->dev, "EA - BEI %2u, Prop 0x%02x: %pR\n",
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dev_printk(KERN_DEBUG, &dev->dev, "EA - BEI %2u, Prop 0x%02x: %pR\n",
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PCI_EA_BEI(dw0), prop, res);
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bei, prop, res);
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out:
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out:
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return offset + ent_size;
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return offset + ent_size;
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}
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}
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@ -361,7 +361,7 @@
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#define PCI_EA_FIRST_ENT 4 /* First EA Entry in List */
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#define PCI_EA_FIRST_ENT 4 /* First EA Entry in List */
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#define PCI_EA_FIRST_ENT_BRIDGE 8 /* First EA Entry for Bridges */
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#define PCI_EA_FIRST_ENT_BRIDGE 8 /* First EA Entry for Bridges */
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#define PCI_EA_ES 0x00000007 /* Entry Size */
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#define PCI_EA_ES 0x00000007 /* Entry Size */
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#define PCI_EA_BEI(x) (((x) >> 4) & 0xf) /* BAR Equivalent Indicator */
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#define PCI_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */
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/* 0-5 map to BARs 0-5 respectively */
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/* 0-5 map to BARs 0-5 respectively */
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#define PCI_EA_BEI_BAR0 0
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#define PCI_EA_BEI_BAR0 0
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#define PCI_EA_BEI_BAR5 5
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#define PCI_EA_BEI_BAR5 5
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@ -372,8 +372,8 @@
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#define PCI_EA_BEI_VF_BAR0 9
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#define PCI_EA_BEI_VF_BAR0 9
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#define PCI_EA_BEI_VF_BAR5 14
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#define PCI_EA_BEI_VF_BAR5 14
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#define PCI_EA_BEI_RESERVED 15 /* Reserved - Treat like ENI */
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#define PCI_EA_BEI_RESERVED 15 /* Reserved - Treat like ENI */
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#define PCI_EA_PP(x) (((x) >> 8) & 0xff) /* Primary Properties */
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#define PCI_EA_PP 0x0000ff00 /* Primary Properties */
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#define PCI_EA_SP(x) (((x) >> 16) & 0xff) /* Secondary Properties */
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#define PCI_EA_SP 0x00ff0000 /* Secondary Properties */
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#define PCI_EA_P_MEM 0x00 /* Non-Prefetch Memory */
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#define PCI_EA_P_MEM 0x00 /* Non-Prefetch Memory */
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#define PCI_EA_P_MEM_PREFETCH 0x01 /* Prefetchable Memory */
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#define PCI_EA_P_MEM_PREFETCH 0x01 /* Prefetchable Memory */
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#define PCI_EA_P_IO 0x02 /* I/O Space */
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#define PCI_EA_P_IO 0x02 /* I/O Space */
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