drm/radeon: switch to a finer grained reset for cayman/TN
No change in functionality as we currently set all the reset flags. Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
Родитель
0ecebb9e0d
Коммит
271d6fed65
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@ -1306,15 +1306,13 @@ void cayman_dma_fini(struct radeon_device *rdev)
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radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);
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}
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static int cayman_gpu_soft_reset(struct radeon_device *rdev)
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static void cayman_gpu_soft_reset_gfx(struct radeon_device *rdev)
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{
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struct evergreen_mc_save save;
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u32 grbm_reset = 0, tmp;
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u32 grbm_reset = 0;
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if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
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return 0;
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return;
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dev_info(rdev->dev, "GPU softreset \n");
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dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
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RREG32(GRBM_STATUS));
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dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
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@ -1331,41 +1329,10 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev)
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RREG32(CP_BUSY_STAT));
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dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
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RREG32(CP_STAT));
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dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
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RREG32(DMA_STATUS_REG));
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dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
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RREG32(0x14F8));
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dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
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RREG32(0x14D8));
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dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
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RREG32(0x14FC));
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dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
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RREG32(0x14DC));
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evergreen_mc_stop(rdev, &save);
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if (evergreen_mc_wait_for_idle(rdev)) {
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dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
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}
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/* Disable CP parsing/prefetching */
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WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
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/* dma0 */
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tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
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tmp &= ~DMA_RB_ENABLE;
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WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
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/* dma1 */
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tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
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tmp &= ~DMA_RB_ENABLE;
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WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
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/* Reset dma */
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WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
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RREG32(SRBM_SOFT_RESET);
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udelay(50);
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WREG32(SRBM_SOFT_RESET, 0);
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/* reset all the gfx blocks */
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grbm_reset = (SOFT_RESET_CP |
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SOFT_RESET_CB |
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@ -1387,8 +1354,6 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev)
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udelay(50);
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WREG32(GRBM_SOFT_RESET, 0);
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(void)RREG32(GRBM_SOFT_RESET);
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/* Wait a little for things to settle down */
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udelay(50);
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dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
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RREG32(GRBM_STATUS));
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@ -1406,15 +1371,81 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev)
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RREG32(CP_BUSY_STAT));
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dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
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RREG32(CP_STAT));
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}
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static void cayman_gpu_soft_reset_dma(struct radeon_device *rdev)
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{
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u32 tmp;
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if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
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return;
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dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
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RREG32(DMA_STATUS_REG));
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/* dma0 */
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tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
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tmp &= ~DMA_RB_ENABLE;
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WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
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/* dma1 */
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tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
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tmp &= ~DMA_RB_ENABLE;
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WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
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/* Reset dma */
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WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
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RREG32(SRBM_SOFT_RESET);
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udelay(50);
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WREG32(SRBM_SOFT_RESET, 0);
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dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
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RREG32(DMA_STATUS_REG));
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}
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static int cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
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{
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struct evergreen_mc_save save;
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if (reset_mask == 0)
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return 0;
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dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
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dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
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RREG32(0x14F8));
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dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
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RREG32(0x14D8));
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dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
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RREG32(0x14FC));
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dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
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RREG32(0x14DC));
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evergreen_mc_stop(rdev, &save);
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if (evergreen_mc_wait_for_idle(rdev)) {
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dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
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}
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if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))
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cayman_gpu_soft_reset_gfx(rdev);
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if (reset_mask & RADEON_RESET_DMA)
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cayman_gpu_soft_reset_dma(rdev);
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/* Wait a little for things to settle down */
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udelay(50);
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evergreen_mc_resume(rdev, &save);
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return 0;
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}
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int cayman_asic_reset(struct radeon_device *rdev)
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{
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return cayman_gpu_soft_reset(rdev);
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return cayman_gpu_soft_reset(rdev, (RADEON_RESET_GFX |
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RADEON_RESET_COMPUTE |
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RADEON_RESET_DMA));
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}
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/**
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