powerpc/85xx: Add support for Emerson/Artesyn MVME2500.
Add support for the Artesyn MVME2500 Single Board Computer. The MVME2500 is a 6U form factor VME64 computer with: - A single Freescale QorIQ P2010 CPU - 1 GB of DDR3 onboard memory - Three Gigabit Ethernets - Five 16550 compatible UARTS - One USB 2.0 port, one SHDC socket and one SATA connector - One PCI/PCI eXpress Mezzanine Card (PMC/XMC) Slot - MultiProcessor Interrupt Controller (MPIC) - A DS1375T Real Time Clock (RTC) and 512 KB of Non-Volatile Memory - Two 64 KB EEPROMs - U-Boot in 16 SPI Flash This patch is based on linux-3.18 and has been boot tested. Signed-off-by: Alessio Igor Bogani <alessio.bogani@elettra.eu> Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
Alessio Igor Bogani
Scott Wood
Родитель
bb344ca5b9
Коммит
2727ed5471
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@ -0,0 +1,280 @@
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/*
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* Device tree source for the Emerson/Artesyn MVME2500
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*
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* Copyright 2014 Elettra-Sincrotrone Trieste S.C.p.A.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* Based on: P2020 DS Device Tree Source
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* Copyright 2009 Freescale Semiconductor Inc.
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*/
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/include/ "fsl/p2020si-pre.dtsi"
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/ {
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model = "MVME2500";
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compatible = "artesyn,MVME2500";
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aliases {
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serial2 = &serial2;
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serial3 = &serial3;
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serial4 = &serial4;
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serial5 = &serial5;
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};
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memory {
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device_type = "memory";
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};
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soc: soc@ffe00000 {
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ranges = <0x0 0 0xffe00000 0x100000>;
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i2c@3000 {
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hwmon@4c {
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compatible = "adi,adt7461";
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reg = <0x4c>;
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};
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rtc@68 {
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compatible = "dallas,ds1337";
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reg = <0x68>;
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interrupts = <8 1 0 0>;
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};
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eeprom@54 {
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compatible = "atmel,24c64";
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reg = <0x54>;
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};
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eeprom@52 {
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compatible = "atmel,24c512";
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reg = <0x52>;
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};
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eeprom@53 {
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compatible = "atmel,24c512";
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reg = <0x53>;
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};
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eeprom@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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};
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};
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spi0: spi@7000 {
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fsl,espi-num-chipselects = <2>;
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flash@0 {
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compatible = "atmel,at25df641";
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reg = <0>;
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spi-max-frequency = <10000000>;
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};
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flash@1 {
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compatible = "atmel,at25df641";
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reg = <1>;
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spi-max-frequency = <10000000>;
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};
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};
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usb@22000 {
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dr_mode = "host";
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phy_type = "ulpi";
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};
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enet0: ethernet@24000 {
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tbi-handle = <&tbi0>;
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phy-handle = <&phy1>;
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phy-connection-type = "rgmii-id";
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};
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mdio@24520 {
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phy1: ethernet-phy@1 {
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compatible = "brcm,bcm54616S";
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interrupts = <6 1 0 0>;
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reg = <0x1>;
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};
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phy2: ethernet-phy@2 {
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compatible = "brcm,bcm54616S";
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interrupts = <6 1 0 0>;
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reg = <0x2>;
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};
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phy3: ethernet-phy@3 {
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compatible = "brcm,bcm54616S";
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interrupts = <5 1 0 0>;
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reg = <0x3>;
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};
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phy7: ethernet-phy@7 {
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compatible = "brcm,bcm54616S";
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interrupts = <7 1 0 0>;
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reg = <0x7>;
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet1: ethernet@25000 {
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tbi-handle = <&tbi1>;
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phy-handle = <&phy7>;
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phy-connection-type = "rgmii-id";
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};
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mdio@25520 {
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet2: ethernet@26000 {
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tbi-handle = <&tbi2>;
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phy-handle = <&phy3>;
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phy-connection-type = "rgmii-id";
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};
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mdio@26520 {
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tbi2: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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lbc: localbus@ffe05000 {
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reg = <0 0xffe05000 0 0x1000>;
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ranges = <0x0 0x0 0x0 0xfff00000 0x00080000
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0x1 0x0 0x0 0xffc40000 0x00010000
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0x2 0x0 0x0 0xffc50000 0x00010000
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0x3 0x0 0x0 0xffc60000 0x00010000
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0x4 0x0 0x0 0xffc70000 0x00010000
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0x6 0x0 0x0 0xffc80000 0x00010000
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0x5 0x0 0x0 0xffdf0000 0x00008000>;
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serial2: serial@1,0 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x1 0x0 0x100>;
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clock-frequency = <1843200>;
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interrupts = <11 2 0 0>;
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};
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serial3: serial@2,0 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x2 0x0 0x100>;
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clock-frequency = <1843200>;
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interrupts = <1 2 0 0>;
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};
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serial4: serial@3,0 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x3 0x0 0x100>;
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clock-frequency = <1843200>;
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interrupts = <2 2 0 0>;
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};
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serial5: serial@4,0 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4 0x0 0x100>;
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clock-frequency = <1843200>;
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interrupts = <3 2 0 0>;
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};
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mram@0,0 {
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compatible = "everspin,mram", "mtd-ram";
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reg = <0x0 0x0 0x80000>;
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bank-width = <2>;
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};
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board-control@5,0 {
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compatible = "artesyn,mvme2500-fpga";
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reg = <0x5 0x0 0x01000>;
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};
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cpld@6,0 {
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compatible = "artesyn,mvme2500-cpld";
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reg = <0x6 0x0 0x10000>;
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interrupts = <9 1 0 0>;
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};
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};
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pci0: pcie@ffe08000 {
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reg = <0 0xffe08000 0 0x1000>;
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ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0x80000000
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0x2000000 0x0 0x80000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x10000>;
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};
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};
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pci1: pcie@ffe09000 {
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reg = <0 0xffe09000 0 0x1000>;
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ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xa0000000
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0x2000000 0x0 0xa0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x10000>;
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};
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};
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pci2: pcie@ffe0a000 {
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reg = <0 0xffe0a000 0 0x1000>;
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ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xc0000000
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0x2000000 0x0 0xc0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x10000>;
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};
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};
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};
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/include/ "fsl/p2020si-post.dtsi"
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/ {
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soc@ffe00000 {
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serial@4600 {
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status = "disabled";
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};
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i2c@3100 {
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status = "disabled";
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};
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sdhc@2e000 {
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compatible = "fsl,p2020-esdhc", "fsl,esdhc";
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non-removable;
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};
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};
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};
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@ -42,6 +42,7 @@ CONFIG_TQM8548=y
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CONFIG_TQM8555=y
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CONFIG_TQM8560=y
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CONFIG_SBC8548=y
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CONFIG_MVME2500=y
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CONFIG_QUICC_ENGINE=y
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CONFIG_QE_GPIO=y
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CONFIG_HIGHMEM=y
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@ -49,6 +50,8 @@ CONFIG_BINFMT_MISC=m
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CONFIG_MATH_EMULATION=y
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CONFIG_FORCE_MAX_ZONEORDER=12
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CONFIG_PCI=y
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CONFIG_PCIEPORTBUS=y
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# CONFIG_PCIEASPM is not set
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CONFIG_PCI_MSI=y
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CONFIG_RAPIDIO=y
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CONFIG_NET=y
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@ -85,10 +88,14 @@ CONFIG_FTL=y
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CONFIG_MTD_CFI=y
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CONFIG_MTD_CFI_INTELEXT=y
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CONFIG_MTD_CFI_AMDSTD=y
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CONFIG_MTD_PHYSMAP=y
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CONFIG_MTD_PHYSMAP_OF=y
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CONFIG_MTD_PLATRAM=y
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CONFIG_MTD_M25P80=y
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CONFIG_MTD_NAND=y
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CONFIG_MTD_NAND_FSL_ELBC=y
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CONFIG_MTD_NAND_FSL_IFC=y
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CONFIG_MTD_SPI_NOR=y
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CONFIG_MTD_UBI=y
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CONFIG_BLK_DEV_LOOP=y
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CONFIG_BLK_DEV_NBD=y
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@ -120,6 +127,7 @@ CONFIG_MARVELL_PHY=y
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CONFIG_DAVICOM_PHY=y
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CONFIG_CICADA_PHY=y
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CONFIG_VITESSE_PHY=y
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CONFIG_BROADCOM_PHY=y
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CONFIG_FIXED_PHY=y
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CONFIG_INPUT_FF_MEMLESS=m
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# CONFIG_INPUT_MOUSEDEV is not set
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@ -128,8 +136,8 @@ CONFIG_INPUT_FF_MEMLESS=m
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CONFIG_SERIO_LIBPS2=y
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CONFIG_SERIAL_8250=y
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CONFIG_SERIAL_8250_CONSOLE=y
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CONFIG_SERIAL_8250_NR_UARTS=2
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CONFIG_SERIAL_8250_RUNTIME_UARTS=2
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CONFIG_SERIAL_8250_NR_UARTS=6
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CONFIG_SERIAL_8250_RUNTIME_UARTS=6
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CONFIG_SERIAL_8250_MANY_PORTS=y
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CONFIG_SERIAL_8250_DETECT_IRQ=y
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CONFIG_SERIAL_8250_RSA=y
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@ -142,7 +150,8 @@ CONFIG_SPI=y
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CONFIG_SPI_FSL_SPI=y
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CONFIG_SPI_FSL_ESPI=y
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CONFIG_GPIO_MPC8XXX=y
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# CONFIG_HWMON is not set
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CONFIG_HWMON=m
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CONFIG_SENSORS_LM90=m
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CONFIG_FB=y
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CONFIG_FB_FSL_DIU=y
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# CONFIG_VGA_CONSOLE is not set
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@ -185,6 +194,7 @@ CONFIG_MMC_SDHCI_PLTFM=y
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CONFIG_MMC_SDHCI_OF_ESDHC=y
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CONFIG_EDAC=y
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CONFIG_EDAC_MM_EDAC=y
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CONFIG_EDAC_MPC85XX=y
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CONFIG_RTC_CLASS=y
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CONFIG_RTC_DRV_DS1307=y
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CONFIG_RTC_DRV_DS1374=y
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@ -241,6 +241,12 @@ config SGY_CTS1000
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help
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Enable this to support functionality in Servergy's CTS-1000 systems.
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config MVME2500
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bool "Artesyn MVME2500"
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select DEFAULT_UIMAGE
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help
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This option enables support for the Emerson/Artesyn MVME2500 board.
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endif # PPC32
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config PPC_QEMU_E500
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@ -31,3 +31,4 @@ obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
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obj-$(CONFIG_GE_IMP3A) += ge_imp3a.o
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obj-$(CONFIG_PPC_QEMU_E500) += qemu_e500.o
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obj-$(CONFIG_SGY_CTS1000) += sgy_cts1000.o
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obj-$(CONFIG_MVME2500) += mvme2500.o
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@ -0,0 +1,74 @@
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/*
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* Board setup routines for the Emerson/Artesyn MVME2500
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*
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* Copyright 2014 Elettra-Sincrotrone Trieste S.C.p.A.
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*
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* Based on earlier code by:
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*
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* Xianghua Xiao (x.xiao@freescale.com)
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* Tom Armistead (tom.armistead@emerson.com)
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* Copyright 2012 Emerson
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* Author Alessio Igor Bogani <alessio.bogani@elettra.eu>
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*
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*/
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#include <linux/pci.h>
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#include <asm/udbg.h>
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#include <asm/mpic.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#include "mpc85xx.h"
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void __init mvme2500_pic_init(void)
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{
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struct mpic *mpic = mpic_alloc(NULL, 0,
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MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU,
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0, 256, " OpenPIC ");
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BUG_ON(mpic == NULL);
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mpic_init(mpic);
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}
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/*
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* Setup the architecture
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*/
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static void __init mvme2500_setup_arch(void)
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{
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if (ppc_md.progress)
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ppc_md.progress("mvme2500_setup_arch()", 0);
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fsl_pci_assign_primary();
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pr_info("MVME2500 board from Artesyn\n");
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}
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machine_arch_initcall(mvme2500, mpc85xx_common_publish_devices);
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init mvme2500_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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return of_flat_dt_is_compatible(root, "artesyn,MVME2500");
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}
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define_machine(mvme2500) {
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.name = "MVME2500",
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.probe = mvme2500_probe,
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.setup_arch = mvme2500_setup_arch,
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.init_IRQ = mvme2500_pic_init,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
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#endif
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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