pch_phub: Support new device ML7223
Support new device OKI SEMICONDUCTOR ML7223 IOH(Input/Output Hub). The ML7223 IOH is for MP(Media Phone) use. The ML7223 is companion chip for Intel Atom E6xx series. The ML7223 is completely compatible for Intel EG20T PCH. Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Tomoya MORINAGA
Greg Kroah-Hartman
Родитель
aa273ae521
Коммит
275640b0d8
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@ -459,7 +459,7 @@ config BMP085
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module will be called bmp085.
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config PCH_PHUB
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tristate "PCH Packet Hub of Intel Topcliff / OKI SEMICONDUCTOR ML7213"
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tristate "Intel EG20T PCH / OKI SEMICONDUCTOR IOH(ML7213/ML7223) PHUB"
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depends on PCI
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help
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This driver is for PCH(Platform controller Hub) PHUB(Packet Hub) of
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@ -467,10 +467,12 @@ config PCH_PHUB
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processor. The Topcliff has MAC address and Option ROM data in SROM.
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This driver can access MAC address and Option ROM data in SROM.
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This driver also can be used for OKI SEMICONDUCTOR's ML7213 which is
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for IVI(In-Vehicle Infotainment) use.
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ML7213 is companion chip for Intel Atom E6xx series.
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ML7213 is completely compatible for Intel EG20T PCH.
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This driver also can be used for OKI SEMICONDUCTOR IOH(Input/
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Output Hub), ML7213 and ML7223.
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ML7213 IOH is for IVI(In-Vehicle Infotainment) use and ML7223 IOH is
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for MP(Media Phone) use.
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ML7213/ML7223 is companion chip for Intel Atom E6xx series.
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ML7213/ML7223 is completely compatible for Intel EG20T PCH.
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To compile this driver as a module, choose M here: the module will
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be called pch_phub.
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@ -34,12 +34,18 @@
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#define PHUB_TIMEOUT 0x05 /* Time out value for Status Register */
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#define PCH_PHUB_ROM_WRITE_ENABLE 0x01 /* Enabling for writing ROM */
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#define PCH_PHUB_ROM_WRITE_DISABLE 0x00 /* Disabling for writing ROM */
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#define PCH_PHUB_MAC_START_ADDR 0x20C /* MAC data area start address offset */
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#define PCH_PHUB_ROM_START_ADDR_EG20T 0x14 /* ROM data area start address offset
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#define PCH_PHUB_MAC_START_ADDR_EG20T 0x14 /* MAC data area start address
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offset */
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#define PCH_PHUB_MAC_START_ADDR_ML7223 0x20C /* MAC data area start address
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offset */
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#define PCH_PHUB_ROM_START_ADDR_EG20T 0x80 /* ROM data area start address offset
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(Intel EG20T PCH)*/
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#define PCH_PHUB_ROM_START_ADDR_ML7213 0x400 /* ROM data area start address
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offset(OKI SEMICONDUCTOR ML7213)
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*/
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#define PCH_PHUB_ROM_START_ADDR_ML7223 0x400 /* ROM data area start address
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offset(OKI SEMICONDUCTOR ML7223)
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*/
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/* MAX number of INT_REDUCE_CONTROL registers */
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#define MAX_NUM_INT_REDUCE_CONTROL_REG 128
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@ -63,6 +69,10 @@
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#define PCI_VENDOR_ID_ROHM 0x10db
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#define PCI_DEVICE_ID_ROHM_ML7213_PHUB 0x801A
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/* Macros for ML7223 */
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#define PCI_DEVICE_ID_ROHM_ML7223_mPHUB 0x8012 /* for Bus-m */
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#define PCI_DEVICE_ID_ROHM_ML7223_nPHUB 0x8002 /* for Bus-n */
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/* SROM ACCESS Macro */
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#define PCH_WORD_ADDR_MASK (~((1 << 2) - 1))
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@ -100,6 +110,9 @@
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* @clkcfg_reg: CLK CFG register val
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* @pch_phub_base_address: Register base address
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* @pch_phub_extrom_base_address: external rom base address
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* @pch_mac_start_address: MAC address area start address
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* @pch_opt_rom_start_address: Option ROM start address
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* @ioh_type: Save IOH type
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*/
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struct pch_phub_reg {
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u32 phub_id_reg;
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@ -117,6 +130,9 @@ struct pch_phub_reg {
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u32 clkcfg_reg;
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void __iomem *pch_phub_base_address;
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void __iomem *pch_phub_extrom_base_address;
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u32 pch_mac_start_address;
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u32 pch_opt_rom_start_address;
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int ioh_type;
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};
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/* SROM SPEC for MAC address assignment offset */
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@ -319,7 +335,7 @@ static void pch_phub_read_serial_rom_val(struct pch_phub_reg *chip,
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{
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unsigned int mem_addr;
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mem_addr = PCH_PHUB_ROM_START_ADDR_EG20T +
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mem_addr = chip->pch_mac_start_address +
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pch_phub_mac_offset[offset_address];
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pch_phub_read_serial_rom(chip, mem_addr, data);
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@ -336,7 +352,7 @@ static int pch_phub_write_serial_rom_val(struct pch_phub_reg *chip,
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int retval;
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unsigned int mem_addr;
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mem_addr = PCH_PHUB_ROM_START_ADDR_EG20T +
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mem_addr = chip->pch_mac_start_address +
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pch_phub_mac_offset[offset_address];
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retval = pch_phub_write_serial_rom(chip, mem_addr, data);
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@ -384,6 +400,48 @@ static int pch_phub_gbe_serial_rom_conf(struct pch_phub_reg *chip)
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return retval;
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}
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/* pch_phub_gbe_serial_rom_conf_mp - makes SerialROM header format configuration
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* for Gigabit Ethernet MAC address
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*/
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static int pch_phub_gbe_serial_rom_conf_mp(struct pch_phub_reg *chip)
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{
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int retval;
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u32 offset_addr;
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offset_addr = 0x200;
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retval = pch_phub_write_serial_rom(chip, 0x03 + offset_addr, 0xbc);
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retval |= pch_phub_write_serial_rom(chip, 0x02 + offset_addr, 0x00);
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retval |= pch_phub_write_serial_rom(chip, 0x01 + offset_addr, 0x40);
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retval |= pch_phub_write_serial_rom(chip, 0x00 + offset_addr, 0x02);
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retval |= pch_phub_write_serial_rom(chip, 0x07 + offset_addr, 0x00);
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retval |= pch_phub_write_serial_rom(chip, 0x06 + offset_addr, 0x00);
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retval |= pch_phub_write_serial_rom(chip, 0x05 + offset_addr, 0x00);
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retval |= pch_phub_write_serial_rom(chip, 0x04 + offset_addr, 0x80);
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retval |= pch_phub_write_serial_rom(chip, 0x0b + offset_addr, 0xbc);
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retval |= pch_phub_write_serial_rom(chip, 0x0a + offset_addr, 0x00);
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retval |= pch_phub_write_serial_rom(chip, 0x09 + offset_addr, 0x40);
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retval |= pch_phub_write_serial_rom(chip, 0x08 + offset_addr, 0x18);
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retval |= pch_phub_write_serial_rom(chip, 0x13 + offset_addr, 0xbc);
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retval |= pch_phub_write_serial_rom(chip, 0x12 + offset_addr, 0x00);
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retval |= pch_phub_write_serial_rom(chip, 0x11 + offset_addr, 0x40);
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retval |= pch_phub_write_serial_rom(chip, 0x10 + offset_addr, 0x19);
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retval |= pch_phub_write_serial_rom(chip, 0x1b + offset_addr, 0xbc);
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retval |= pch_phub_write_serial_rom(chip, 0x1a + offset_addr, 0x00);
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retval |= pch_phub_write_serial_rom(chip, 0x19 + offset_addr, 0x40);
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retval |= pch_phub_write_serial_rom(chip, 0x18 + offset_addr, 0x3a);
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retval |= pch_phub_write_serial_rom(chip, 0x1f + offset_addr, 0x01);
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retval |= pch_phub_write_serial_rom(chip, 0x1e + offset_addr, 0x00);
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retval |= pch_phub_write_serial_rom(chip, 0x1d + offset_addr, 0x00);
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retval |= pch_phub_write_serial_rom(chip, 0x1c + offset_addr, 0x00);
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return retval;
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}
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/**
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* pch_phub_read_gbe_mac_addr() - Read Gigabit Ethernet MAC address
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* @offset_address: Gigabit Ethernet MAC address offset value.
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@ -406,7 +464,10 @@ static int pch_phub_write_gbe_mac_addr(struct pch_phub_reg *chip, u8 *data)
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int retval;
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int i;
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retval = pch_phub_gbe_serial_rom_conf(chip);
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if (chip->ioh_type == 1) /* EG20T */
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retval = pch_phub_gbe_serial_rom_conf(chip);
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else /* ML7223 */
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retval = pch_phub_gbe_serial_rom_conf_mp(chip);
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if (retval)
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return retval;
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@ -441,12 +502,16 @@ static ssize_t pch_phub_bin_read(struct file *filp, struct kobject *kobj,
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}
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/* Get Rom signature */
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pch_phub_read_serial_rom(chip, 0x80, (unsigned char *)&rom_signature);
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pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address,
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(unsigned char *)&rom_signature);
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rom_signature &= 0xff;
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pch_phub_read_serial_rom(chip, 0x81, (unsigned char *)&tmp);
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pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address + 1,
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(unsigned char *)&tmp);
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rom_signature |= (tmp & 0xff) << 8;
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if (rom_signature == 0xAA55) {
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pch_phub_read_serial_rom(chip, 0x82, &rom_length);
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pch_phub_read_serial_rom(chip,
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chip->pch_opt_rom_start_address + 2,
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&rom_length);
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orom_size = rom_length * 512;
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if (orom_size < off) {
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addr_offset = 0;
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@ -458,8 +523,9 @@ static ssize_t pch_phub_bin_read(struct file *filp, struct kobject *kobj,
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}
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for (addr_offset = 0; addr_offset < count; addr_offset++) {
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pch_phub_read_serial_rom(chip, 0x80 + addr_offset + off,
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&buf[addr_offset]);
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pch_phub_read_serial_rom(chip,
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chip->pch_opt_rom_start_address + addr_offset + off,
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&buf[addr_offset]);
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}
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} else {
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err = -ENODATA;
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@ -502,8 +568,9 @@ static ssize_t pch_phub_bin_write(struct file *filp, struct kobject *kobj,
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if (PCH_PHUB_OROM_SIZE < off + addr_offset)
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goto return_ok;
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ret = pch_phub_write_serial_rom(chip, 0x80 + addr_offset + off,
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buf[addr_offset]);
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ret = pch_phub_write_serial_rom(chip,
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chip->pch_opt_rom_start_address + addr_offset + off,
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buf[addr_offset]);
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if (ret) {
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err = ret;
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goto return_err;
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@ -603,19 +670,22 @@ static int __devinit pch_phub_probe(struct pci_dev *pdev,
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dev_dbg(&pdev->dev, "%s : pci_iomap SUCCESS and value "
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"in pch_phub_base_address variable is %p\n", __func__,
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chip->pch_phub_base_address);
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chip->pch_phub_extrom_base_address = pci_map_rom(pdev, &rom_size);
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if (chip->pch_phub_extrom_base_address == 0) {
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dev_err(&pdev->dev, "%s : pci_map_rom FAILED", __func__);
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ret = -ENOMEM;
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goto err_pci_map;
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if (id->driver_data != 3) {
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chip->pch_phub_extrom_base_address =\
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pci_map_rom(pdev, &rom_size);
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if (chip->pch_phub_extrom_base_address == 0) {
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dev_err(&pdev->dev, "%s: pci_map_rom FAILED", __func__);
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ret = -ENOMEM;
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goto err_pci_map;
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}
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dev_dbg(&pdev->dev, "%s : "
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"pci_map_rom SUCCESS and value in "
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"pch_phub_extrom_base_address variable is %p\n",
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__func__, chip->pch_phub_extrom_base_address);
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}
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dev_dbg(&pdev->dev, "%s : "
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"pci_map_rom SUCCESS and value in "
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"pch_phub_extrom_base_address variable is %p\n", __func__,
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chip->pch_phub_extrom_base_address);
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if (id->driver_data == 1) {
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if (id->driver_data == 1) { /* EG20T PCH */
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retval = sysfs_create_file(&pdev->dev.kobj,
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&dev_attr_pch_mac.attr);
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if (retval)
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@ -642,7 +712,9 @@ static int __devinit pch_phub_probe(struct pci_dev *pdev,
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iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14);
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/* set the interrupt delay value */
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iowrite32(0x25, chip->pch_phub_base_address + 0x44);
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} else if (id->driver_data == 2) {
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chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
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chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
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} else if (id->driver_data == 2) { /* ML7213 IOH */
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retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
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if (retval)
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goto err_sysfs_create;
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@ -653,7 +725,38 @@ static int __devinit pch_phub_probe(struct pci_dev *pdev,
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* Device8(USB OHCI #0/ USB EHCI #0):a
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*/
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iowrite32(0x000affa0, chip->pch_phub_base_address + 0x14);
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chip->pch_opt_rom_start_address =\
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PCH_PHUB_ROM_START_ADDR_ML7213;
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} else if (id->driver_data == 3) { /* ML7223 IOH Bus-m*/
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/* set the prefech value
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* Device8(GbE)
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*/
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iowrite32(0x000a0000, chip->pch_phub_base_address + 0x14);
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chip->pch_opt_rom_start_address =\
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PCH_PHUB_ROM_START_ADDR_ML7223;
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chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
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} else if (id->driver_data == 4) { /* ML7223 IOH Bus-n*/
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retval = sysfs_create_file(&pdev->dev.kobj,
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&dev_attr_pch_mac.attr);
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if (retval)
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goto err_sysfs_create;
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retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
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if (retval)
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goto exit_bin_attr;
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/* set the prefech value
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* Device2(USB OHCI #0,1,2,3/ USB EHCI #0):a
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* Device4(SDIO #0,1):f
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* Device6(SATA 2):f
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*/
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iowrite32(0x0000ffa0, chip->pch_phub_base_address + 0x14);
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/* set the interrupt delay value */
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iowrite32(0x25, chip->pch_phub_base_address + 0x140);
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chip->pch_opt_rom_start_address =\
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PCH_PHUB_ROM_START_ADDR_ML7223;
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chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
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}
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chip->ioh_type = id->driver_data;
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pci_set_drvdata(pdev, chip);
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return 0;
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@ -733,6 +836,8 @@ static int pch_phub_resume(struct pci_dev *pdev)
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static struct pci_device_id pch_phub_pcidev_id[] = {
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH1_PHUB), 1, },
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{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7213_PHUB), 2, },
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{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_mPHUB), 3, },
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{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_nPHUB), 4, },
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{ }
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};
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MODULE_DEVICE_TABLE(pci, pch_phub_pcidev_id);
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@ -759,5 +864,5 @@ static void __exit pch_phub_pci_exit(void)
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module_init(pch_phub_pci_init);
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module_exit(pch_phub_pci_exit);
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MODULE_DESCRIPTION("PCH Packet Hub PCI Driver");
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MODULE_DESCRIPTION("Intel EG20T PCH/OKI SEMICONDUCTOR IOH(ML7213/ML7223) PHUB");
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MODULE_LICENSE("GPL");
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