pwm: Imagination Technologies PWM DAC driver
The Pistachio SOC from Imagination Technologies includes a Pulse Width Modulation DAC which produces 1 to 4 digital bit-outputs which represent digital waveforms. These PWM outputs are primarily in charge of controlling backlight LED devices. Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Naidu Tellapati <Naidu.Tellapati@imgtec.com> Signed-off-by: Sai Masarapu <Sai.Masarapu@imgtec.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Reviewed-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> [thierry.reding: fixup license header as discussed on list] Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
This commit is contained in:
Naidu Tellapati
Thierry Reding
Родитель
cd264b6a65
Коммит
277bb6a29e
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@ -131,6 +131,19 @@ config PWM_FSL_FTM
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To compile this driver as a module, choose M here: the module
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will be called pwm-fsl-ftm.
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config PWM_IMG
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tristate "Imagination Technologies PWM driver"
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depends on HAS_IOMEM
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depends on MFD_SYSCON
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depends on COMMON_CLK
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depends on MIPS || COMPILE_TEST
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help
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Generic PWM framework driver for Imagination Technologies
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PWM block which supports 4 channels.
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To compile this driver as a module, choose M here: the module
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will be called pwm-img
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config PWM_IMX
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tristate "i.MX PWM support"
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depends on ARCH_MXC
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@ -10,6 +10,7 @@ obj-$(CONFIG_PWM_BFIN) += pwm-bfin.o
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obj-$(CONFIG_PWM_CLPS711X) += pwm-clps711x.o
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obj-$(CONFIG_PWM_EP93XX) += pwm-ep93xx.o
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obj-$(CONFIG_PWM_FSL_FTM) += pwm-fsl-ftm.o
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obj-$(CONFIG_PWM_IMG) += pwm-img.o
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obj-$(CONFIG_PWM_IMX) += pwm-imx.o
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obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o
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obj-$(CONFIG_PWM_LP3943) += pwm-lp3943.o
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@ -0,0 +1,249 @@
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/*
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* Imagination Technologies Pulse Width Modulator driver
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*
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* Copyright (c) 2014-2015, Imagination Technologies
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*
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* Based on drivers/pwm/pwm-tegra.c, Copyright (c) 2010, NVIDIA Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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/* PWM registers */
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#define PWM_CTRL_CFG 0x0000
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#define PWM_CTRL_CFG_NO_SUB_DIV 0
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#define PWM_CTRL_CFG_SUB_DIV0 1
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#define PWM_CTRL_CFG_SUB_DIV1 2
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#define PWM_CTRL_CFG_SUB_DIV0_DIV1 3
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#define PWM_CTRL_CFG_DIV_SHIFT(ch) ((ch) * 2 + 4)
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#define PWM_CTRL_CFG_DIV_MASK 0x3
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#define PWM_CH_CFG(ch) (0x4 + (ch) * 4)
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#define PWM_CH_CFG_TMBASE_SHIFT 0
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#define PWM_CH_CFG_DUTY_SHIFT 16
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#define PERIP_PWM_PDM_CONTROL 0x0140
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#define PERIP_PWM_PDM_CONTROL_CH_MASK 0x1
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#define PERIP_PWM_PDM_CONTROL_CH_SHIFT(ch) ((ch) * 4)
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#define MAX_TMBASE_STEPS 65536
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struct img_pwm_chip {
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struct device *dev;
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struct pwm_chip chip;
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struct clk *pwm_clk;
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struct clk *sys_clk;
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void __iomem *base;
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struct regmap *periph_regs;
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};
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static inline struct img_pwm_chip *to_img_pwm_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct img_pwm_chip, chip);
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}
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static inline void img_pwm_writel(struct img_pwm_chip *chip,
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u32 reg, u32 val)
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{
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writel(val, chip->base + reg);
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}
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static inline u32 img_pwm_readl(struct img_pwm_chip *chip,
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u32 reg)
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{
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return readl(chip->base + reg);
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}
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static int img_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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u32 val, div, duty, timebase;
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unsigned long mul, output_clk_hz, input_clk_hz;
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struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip);
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input_clk_hz = clk_get_rate(pwm_chip->pwm_clk);
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output_clk_hz = DIV_ROUND_UP(NSEC_PER_SEC, period_ns);
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mul = DIV_ROUND_UP(input_clk_hz, output_clk_hz);
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if (mul <= MAX_TMBASE_STEPS) {
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div = PWM_CTRL_CFG_NO_SUB_DIV;
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timebase = DIV_ROUND_UP(mul, 1);
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} else if (mul <= MAX_TMBASE_STEPS * 8) {
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div = PWM_CTRL_CFG_SUB_DIV0;
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timebase = DIV_ROUND_UP(mul, 8);
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} else if (mul <= MAX_TMBASE_STEPS * 64) {
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div = PWM_CTRL_CFG_SUB_DIV1;
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timebase = DIV_ROUND_UP(mul, 64);
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} else if (mul <= MAX_TMBASE_STEPS * 512) {
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div = PWM_CTRL_CFG_SUB_DIV0_DIV1;
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timebase = DIV_ROUND_UP(mul, 512);
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} else if (mul > MAX_TMBASE_STEPS * 512) {
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dev_err(chip->dev,
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"failed to configure timebase steps/divider value\n");
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return -EINVAL;
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}
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duty = DIV_ROUND_UP(timebase * duty_ns, period_ns);
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val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
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val &= ~(PWM_CTRL_CFG_DIV_MASK << PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm));
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val |= (div & PWM_CTRL_CFG_DIV_MASK) <<
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PWM_CTRL_CFG_DIV_SHIFT(pwm->hwpwm);
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img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
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val = (duty << PWM_CH_CFG_DUTY_SHIFT) |
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(timebase << PWM_CH_CFG_TMBASE_SHIFT);
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img_pwm_writel(pwm_chip, PWM_CH_CFG(pwm->hwpwm), val);
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return 0;
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}
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static int img_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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u32 val;
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struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip);
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val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
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val |= BIT(pwm->hwpwm);
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img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
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regmap_update_bits(pwm_chip->periph_regs, PERIP_PWM_PDM_CONTROL,
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PERIP_PWM_PDM_CONTROL_CH_MASK <<
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PERIP_PWM_PDM_CONTROL_CH_SHIFT(pwm->hwpwm), 0);
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return 0;
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}
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static void img_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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u32 val;
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struct img_pwm_chip *pwm_chip = to_img_pwm_chip(chip);
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val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
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val &= ~BIT(pwm->hwpwm);
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img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
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}
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static const struct pwm_ops img_pwm_ops = {
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.config = img_pwm_config,
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.enable = img_pwm_enable,
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.disable = img_pwm_disable,
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.owner = THIS_MODULE,
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};
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static int img_pwm_probe(struct platform_device *pdev)
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{
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int ret;
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struct resource *res;
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struct img_pwm_chip *pwm;
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pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
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if (!pwm)
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return -ENOMEM;
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pwm->dev = &pdev->dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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pwm->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(pwm->base))
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return PTR_ERR(pwm->base);
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pwm->periph_regs = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
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"img,cr-periph");
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if (IS_ERR(pwm->periph_regs))
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return PTR_ERR(pwm->periph_regs);
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pwm->sys_clk = devm_clk_get(&pdev->dev, "sys");
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if (IS_ERR(pwm->sys_clk)) {
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dev_err(&pdev->dev, "failed to get system clock\n");
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return PTR_ERR(pwm->sys_clk);
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}
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pwm->pwm_clk = devm_clk_get(&pdev->dev, "pwm");
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if (IS_ERR(pwm->pwm_clk)) {
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dev_err(&pdev->dev, "failed to get pwm clock\n");
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return PTR_ERR(pwm->pwm_clk);
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}
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ret = clk_prepare_enable(pwm->sys_clk);
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if (ret < 0) {
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dev_err(&pdev->dev, "could not prepare or enable sys clock\n");
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return ret;
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}
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ret = clk_prepare_enable(pwm->pwm_clk);
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if (ret < 0) {
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dev_err(&pdev->dev, "could not prepare or enable pwm clock\n");
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goto disable_sysclk;
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}
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pwm->chip.dev = &pdev->dev;
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pwm->chip.ops = &img_pwm_ops;
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pwm->chip.base = -1;
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pwm->chip.npwm = 4;
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ret = pwmchip_add(&pwm->chip);
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if (ret < 0) {
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dev_err(&pdev->dev, "pwmchip_add failed: %d\n", ret);
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goto disable_pwmclk;
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}
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platform_set_drvdata(pdev, pwm);
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return 0;
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disable_pwmclk:
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clk_disable_unprepare(pwm->pwm_clk);
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disable_sysclk:
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clk_disable_unprepare(pwm->sys_clk);
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return ret;
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}
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static int img_pwm_remove(struct platform_device *pdev)
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{
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struct img_pwm_chip *pwm_chip = platform_get_drvdata(pdev);
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u32 val;
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unsigned int i;
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for (i = 0; i < pwm_chip->chip.npwm; i++) {
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val = img_pwm_readl(pwm_chip, PWM_CTRL_CFG);
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val &= ~BIT(i);
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img_pwm_writel(pwm_chip, PWM_CTRL_CFG, val);
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}
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clk_disable_unprepare(pwm_chip->pwm_clk);
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clk_disable_unprepare(pwm_chip->sys_clk);
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return pwmchip_remove(&pwm_chip->chip);
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}
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static const struct of_device_id img_pwm_of_match[] = {
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{ .compatible = "img,pistachio-pwm", },
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{ }
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};
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MODULE_DEVICE_TABLE(of, img_pwm_of_match);
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static struct platform_driver img_pwm_driver = {
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.driver = {
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.name = "img-pwm",
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.of_match_table = img_pwm_of_match,
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},
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.probe = img_pwm_probe,
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.remove = img_pwm_remove,
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};
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module_platform_driver(img_pwm_driver);
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MODULE_AUTHOR("Sai Masarapu <Sai.Masarapu@imgtec.com>");
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MODULE_DESCRIPTION("Imagination Technologies PWM DAC driver");
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MODULE_LICENSE("GPL v2");
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