Merge branch 'drm-next-3.14' of git://people.freedesktop.org/~agd5f/linux into drm-next
more radeon fixes * 'drm-next-3.14' of git://people.freedesktop.org/~agd5f/linux: drm/radeon/dce8: workaround for atom BlankCrtc table drm/radeon/DCE4+: clear bios scratch dpms bit (v2) drm/radeon: set si_notify_smc_display_change properly drm/radeon: fix DAC interrupt handling on DCE5+ drm/radeon: clean up active vram sizing drm/radeon: skip async dma init on r6xx drm/radeon/runpm: don't runtime suspend non-PX cards drm/radeon: add ring to fence trace functions drm/radeon: add missing trace point drm/radeon: fix VMID use tracking
This commit is contained in:
Коммит
279b9e0cc3
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@ -209,6 +209,16 @@ static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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}
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static const u32 vga_control_regs[6] =
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{
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AVIVO_D1VGA_CONTROL,
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AVIVO_D2VGA_CONTROL,
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EVERGREEN_D3VGA_CONTROL,
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EVERGREEN_D4VGA_CONTROL,
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EVERGREEN_D5VGA_CONTROL,
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EVERGREEN_D6VGA_CONTROL,
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};
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static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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@ -216,13 +226,23 @@ static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
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struct radeon_device *rdev = dev->dev_private;
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int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
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BLANK_CRTC_PS_ALLOCATION args;
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u32 vga_control = 0;
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memset(&args, 0, sizeof(args));
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if (ASIC_IS_DCE8(rdev)) {
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vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);
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WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);
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}
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args.ucCRTC = radeon_crtc->crtc_id;
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args.ucBlanking = state;
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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if (ASIC_IS_DCE8(rdev)) {
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WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);
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}
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}
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static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
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@ -3840,6 +3840,8 @@ static void cik_cp_gfx_enable(struct radeon_device *rdev, bool enable)
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if (enable)
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WREG32(CP_ME_CNTL, 0);
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else {
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if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
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rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
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}
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@ -4038,6 +4040,10 @@ static int cik_cp_gfx_resume(struct radeon_device *rdev)
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rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
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return r;
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}
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if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
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return 0;
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}
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@ -250,6 +250,8 @@ static void cik_sdma_gfx_stop(struct radeon_device *rdev)
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u32 rb_cntl, reg_offset;
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int i;
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if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
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(rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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for (i = 0; i < 2; i++) {
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@ -381,6 +383,8 @@ static int cik_sdma_gfx_resume(struct radeon_device *rdev)
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}
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}
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if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
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(rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
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return 0;
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@ -4348,8 +4348,8 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev)
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WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
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}
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/* only one DAC on DCE6 */
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if (!ASIC_IS_DCE6(rdev))
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/* only one DAC on DCE5 */
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if (!ASIC_IS_DCE5(rdev))
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WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
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WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
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@ -1390,6 +1390,7 @@ static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
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if (enable)
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WREG32(CP_ME_CNTL, 0);
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else {
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if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
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WREG32(SCRATCH_UMSK, 0);
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@ -1663,6 +1664,9 @@ static int cayman_cp_resume(struct radeon_device *rdev)
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return r;
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}
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if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
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return 0;
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}
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@ -157,6 +157,8 @@ void cayman_dma_stop(struct radeon_device *rdev)
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{
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u32 rb_cntl;
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if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
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(rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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/* dma0 */
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@ -259,6 +261,8 @@ int cayman_dma_resume(struct radeon_device *rdev)
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}
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}
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if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
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(rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
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return 0;
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@ -2254,6 +2254,7 @@ void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
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*/
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void r600_cp_stop(struct radeon_device *rdev)
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{
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if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
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WREG32(SCRATCH_UMSK, 0);
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@ -2612,6 +2613,10 @@ int r600_cp_resume(struct radeon_device *rdev)
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ring->ready = false;
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return r;
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}
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if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
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return 0;
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}
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@ -2895,12 +2900,6 @@ static int r600_startup(struct radeon_device *rdev)
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return r;
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}
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r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
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if (r) {
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dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
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return r;
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}
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/* Enable IRQ */
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if (!rdev->irq.installed) {
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r = radeon_irq_kms_init(rdev);
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@ -2922,12 +2921,6 @@ static int r600_startup(struct radeon_device *rdev)
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if (r)
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return r;
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ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
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r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
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DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
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if (r)
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return r;
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r = r600_cp_load_microcode(rdev);
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if (r)
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return r;
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@ -2935,10 +2928,6 @@ static int r600_startup(struct radeon_device *rdev)
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if (r)
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return r;
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r = r600_dma_resume(rdev);
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if (r)
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return r;
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r = radeon_ib_pool_init(rdev);
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if (r) {
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dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
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@ -2997,7 +2986,6 @@ int r600_suspend(struct radeon_device *rdev)
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radeon_pm_suspend(rdev);
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r600_audio_fini(rdev);
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r600_cp_stop(rdev);
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r600_dma_stop(rdev);
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r600_irq_suspend(rdev);
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radeon_wb_disable(rdev);
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r600_pcie_gart_disable(rdev);
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@ -3077,9 +3065,6 @@ int r600_init(struct radeon_device *rdev)
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rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
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r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
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rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
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r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
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rdev->ih.ring_obj = NULL;
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r600_ih_ring_init(rdev, 64 * 1024);
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@ -3092,7 +3077,6 @@ int r600_init(struct radeon_device *rdev)
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if (r) {
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dev_err(rdev->dev, "disabling GPU acceleration\n");
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r600_cp_fini(rdev);
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r600_dma_fini(rdev);
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r600_irq_fini(rdev);
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radeon_wb_fini(rdev);
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radeon_ib_pool_fini(rdev);
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@ -3109,7 +3093,6 @@ void r600_fini(struct radeon_device *rdev)
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radeon_pm_fini(rdev);
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r600_audio_fini(rdev);
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r600_cp_fini(rdev);
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r600_dma_fini(rdev);
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r600_irq_fini(rdev);
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radeon_wb_fini(rdev);
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radeon_ib_pool_fini(rdev);
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@ -100,6 +100,7 @@ void r600_dma_stop(struct radeon_device *rdev)
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{
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u32 rb_cntl = RREG32(DMA_RB_CNTL);
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if (rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX)
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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rb_cntl &= ~DMA_RB_ENABLE;
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@ -187,6 +188,7 @@ int r600_dma_resume(struct radeon_device *rdev)
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return r;
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}
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if (rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX)
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
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return 0;
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@ -867,6 +867,8 @@ struct radeon_vm {
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struct radeon_fence *fence;
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/* last flush or NULL if we still need to flush */
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struct radeon_fence *last_flush;
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/* last use of vmid */
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struct radeon_fence *last_id_use;
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};
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struct radeon_vm_manager {
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@ -3938,6 +3938,10 @@ void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
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/* tell the bios not to handle mode switching */
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bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
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/* clear the vbios dpms state */
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if (ASIC_IS_DCE4(rdev))
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bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
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if (rdev->family >= CHIP_R600) {
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WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
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WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
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@ -138,7 +138,7 @@ static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority
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p->ring = R600_RING_TYPE_DMA_INDEX;
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else
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p->ring = CAYMAN_RING_TYPE_DMA1_INDEX;
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} else if (p->rdev->family >= CHIP_R600) {
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} else if (p->rdev->family >= CHIP_RV770) {
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p->ring = R600_RING_TYPE_DMA_INDEX;
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} else {
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return -EINVAL;
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@ -405,6 +405,9 @@ static int radeon_pmops_runtime_suspend(struct device *dev)
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if (radeon_runtime_pm == 0)
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return -EINVAL;
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if (radeon_runtime_pm == -1 && !radeon_is_px())
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return -EINVAL;
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drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
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drm_kms_helper_poll_disable(drm_dev);
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vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
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@ -427,6 +430,9 @@ static int radeon_pmops_runtime_resume(struct device *dev)
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if (radeon_runtime_pm == 0)
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return -EINVAL;
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if (radeon_runtime_pm == -1 && !radeon_is_px())
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return -EINVAL;
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drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
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pci_set_power_state(pdev, PCI_D0);
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@ -121,7 +121,7 @@ int radeon_fence_emit(struct radeon_device *rdev,
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(*fence)->seq = ++rdev->fence_drv[ring].sync_seq[ring];
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(*fence)->ring = ring;
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radeon_fence_ring_emit(rdev, ring, *fence);
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trace_radeon_fence_emit(rdev->ddev, (*fence)->seq);
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trace_radeon_fence_emit(rdev->ddev, ring, (*fence)->seq);
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return 0;
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}
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@ -313,7 +313,7 @@ static int radeon_fence_wait_seq(struct radeon_device *rdev, u64 *target_seq,
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continue;
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last_seq[i] = atomic64_read(&rdev->fence_drv[i].last_seq);
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trace_radeon_fence_wait_begin(rdev->ddev, target_seq[i]);
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trace_radeon_fence_wait_begin(rdev->ddev, i, target_seq[i]);
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radeon_irq_kms_sw_irq_get(rdev, i);
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}
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@ -332,7 +332,7 @@ static int radeon_fence_wait_seq(struct radeon_device *rdev, u64 *target_seq,
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continue;
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radeon_irq_kms_sw_irq_put(rdev, i);
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trace_radeon_fence_wait_end(rdev->ddev, target_seq[i]);
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trace_radeon_fence_wait_end(rdev->ddev, i, target_seq[i]);
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}
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if (unlikely(r < 0))
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|
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@ -713,7 +713,7 @@ struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
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unsigned i;
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/* check if the id is still valid */
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if (vm->fence && vm->fence == rdev->vm_manager.active[vm->id])
|
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if (vm->last_id_use && vm->last_id_use == rdev->vm_manager.active[vm->id])
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return NULL;
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/* we definately need to flush */
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|
@ -726,6 +726,7 @@ struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
|
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if (fence == NULL) {
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/* found a free one */
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vm->id = i;
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trace_radeon_vm_grab_id(vm->id, ring);
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return NULL;
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}
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@ -769,6 +770,9 @@ void radeon_vm_fence(struct radeon_device *rdev,
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radeon_fence_unref(&vm->fence);
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vm->fence = radeon_fence_ref(fence);
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radeon_fence_unref(&vm->last_id_use);
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vm->last_id_use = radeon_fence_ref(fence);
|
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}
|
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||||
/**
|
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|
@ -1303,6 +1307,8 @@ void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm)
|
|||
{
|
||||
vm->id = 0;
|
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vm->fence = NULL;
|
||||
vm->last_flush = NULL;
|
||||
vm->last_id_use = NULL;
|
||||
mutex_init(&vm->mutex);
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||||
INIT_LIST_HEAD(&vm->list);
|
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INIT_LIST_HEAD(&vm->va);
|
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|
@ -1341,5 +1347,6 @@ void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm)
|
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}
|
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radeon_fence_unref(&vm->fence);
|
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radeon_fence_unref(&vm->last_flush);
|
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radeon_fence_unref(&vm->last_id_use);
|
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mutex_unlock(&vm->mutex);
|
||||
}
|
||||
|
|
|
@ -106,42 +106,45 @@ TRACE_EVENT(radeon_vm_set_page,
|
|||
|
||||
DECLARE_EVENT_CLASS(radeon_fence_request,
|
||||
|
||||
TP_PROTO(struct drm_device *dev, u32 seqno),
|
||||
TP_PROTO(struct drm_device *dev, int ring, u32 seqno),
|
||||
|
||||
TP_ARGS(dev, seqno),
|
||||
TP_ARGS(dev, ring, seqno),
|
||||
|
||||
TP_STRUCT__entry(
|
||||
__field(u32, dev)
|
||||
__field(int, ring)
|
||||
__field(u32, seqno)
|
||||
),
|
||||
|
||||
TP_fast_assign(
|
||||
__entry->dev = dev->primary->index;
|
||||
__entry->ring = ring;
|
||||
__entry->seqno = seqno;
|
||||
),
|
||||
|
||||
TP_printk("dev=%u, seqno=%u", __entry->dev, __entry->seqno)
|
||||
TP_printk("dev=%u, ring=%d, seqno=%u",
|
||||
__entry->dev, __entry->ring, __entry->seqno)
|
||||
);
|
||||
|
||||
DEFINE_EVENT(radeon_fence_request, radeon_fence_emit,
|
||||
|
||||
TP_PROTO(struct drm_device *dev, u32 seqno),
|
||||
TP_PROTO(struct drm_device *dev, int ring, u32 seqno),
|
||||
|
||||
TP_ARGS(dev, seqno)
|
||||
TP_ARGS(dev, ring, seqno)
|
||||
);
|
||||
|
||||
DEFINE_EVENT(radeon_fence_request, radeon_fence_wait_begin,
|
||||
|
||||
TP_PROTO(struct drm_device *dev, u32 seqno),
|
||||
TP_PROTO(struct drm_device *dev, int ring, u32 seqno),
|
||||
|
||||
TP_ARGS(dev, seqno)
|
||||
TP_ARGS(dev, ring, seqno)
|
||||
);
|
||||
|
||||
DEFINE_EVENT(radeon_fence_request, radeon_fence_wait_end,
|
||||
|
||||
TP_PROTO(struct drm_device *dev, u32 seqno),
|
||||
TP_PROTO(struct drm_device *dev, int ring, u32 seqno),
|
||||
|
||||
TP_ARGS(dev, seqno)
|
||||
TP_ARGS(dev, ring, seqno)
|
||||
);
|
||||
|
||||
DECLARE_EVENT_CLASS(radeon_semaphore_request,
|
||||
|
|
|
@ -1071,6 +1071,7 @@ static void rv770_mc_program(struct radeon_device *rdev)
|
|||
*/
|
||||
void r700_cp_stop(struct radeon_device *rdev)
|
||||
{
|
||||
if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
|
||||
radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
|
||||
WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
|
||||
WREG32(SCRATCH_UMSK, 0);
|
||||
|
|
|
@ -3249,6 +3249,7 @@ static void si_cp_enable(struct radeon_device *rdev, bool enable)
|
|||
if (enable)
|
||||
WREG32(CP_ME_CNTL, 0);
|
||||
else {
|
||||
if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
|
||||
radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
|
||||
WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
|
||||
WREG32(SCRATCH_UMSK, 0);
|
||||
|
@ -3510,6 +3511,9 @@ static int si_cp_resume(struct radeon_device *rdev)
|
|||
|
||||
si_enable_gui_idle_interrupt(rdev, true);
|
||||
|
||||
if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
|
||||
radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -5678,7 +5682,7 @@ static void si_disable_interrupt_state(struct radeon_device *rdev)
|
|||
}
|
||||
|
||||
if (!ASIC_IS_NODCE(rdev)) {
|
||||
WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
|
||||
WREG32(DAC_AUTODETECT_INT_CONTROL, 0);
|
||||
|
||||
tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
|
||||
WREG32(DC_HPD1_INT_CONTROL, tmp);
|
||||
|
|
|
@ -3590,10 +3590,9 @@ static void si_program_display_gap(struct radeon_device *rdev)
|
|||
|
||||
/* Setting this to false forces the performance state to low if the crtcs are disabled.
|
||||
* This can be a problem on PowerXpress systems or if you want to use the card
|
||||
* for offscreen rendering or compute if there are no crtcs enabled. Set it to
|
||||
* true for now so that performance scales even if the displays are off.
|
||||
* for offscreen rendering or compute if there are no crtcs enabled.
|
||||
*/
|
||||
si_notify_smc_display_change(rdev, true /*rdev->pm.dpm.new_active_crtc_count > 0*/);
|
||||
si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
|
||||
}
|
||||
|
||||
static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
|
||||
|
|
|
@ -822,7 +822,7 @@
|
|||
# define GRPH_PFLIP_INT_MASK (1 << 0)
|
||||
# define GRPH_PFLIP_INT_TYPE (1 << 8)
|
||||
|
||||
#define DACA_AUTODETECT_INT_CONTROL 0x66c8
|
||||
#define DAC_AUTODETECT_INT_CONTROL 0x67c8
|
||||
|
||||
#define DC_HPD1_INT_STATUS 0x601c
|
||||
#define DC_HPD2_INT_STATUS 0x6028
|
||||
|
|
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