staging: rtl8192e: Copy comments from r819XE_phyreg.h to r8192E_phyreg.h
Both files have the same contents (with the exception of comments). One of them will not survive future commits. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Mateusz Kulikowski
Greg Kroah-Hartman
Родитель
7b7b0c9bbc
Коммит
27a3071c6d
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@ -53,10 +53,10 @@
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#define MCS_TXAGC 0x340
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#define CCK_TXAGC 0x348
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/*---------------------0x400~0x4ff----------------------*/
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/* Mac block on/off control register */
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#define MacBlkCtrl 0x403
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#define rFPGA0_RFMOD 0x800
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#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */
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#define rFPGA0_TxInfo 0x804
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#define rFPGA0_PSDFunction 0x808
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#define rFPGA0_TxGainStage 0x80c
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@ -98,6 +98,7 @@
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#define rFPGA0_XAB_RFInterfaceRB 0x8e0
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#define rFPGA0_XCD_RFInterfaceRB 0x8e4
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/* Page 9 - RF mode & OFDM TxSC */
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#define rFPGA1_RFMOD 0x900
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#define rFPGA1_TxBlock 0x904
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#define rFPGA1_DebugSelect 0x908
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@ -106,14 +107,16 @@
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#define rCCK0_System 0xa00
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#define rCCK0_AFESetting 0xa04
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#define rCCK0_CCA 0xa08
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/* AGC default value, saturation level */
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#define rCCK0_RxAGC1 0xa0c
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#define rCCK0_RxAGC2 0xa10
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#define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */
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#define rCCK0_RxHP 0xa14
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/* Timing recovery & channel estimation threshold */
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#define rCCK0_DSPParameter1 0xa18
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#define rCCK0_DSPParameter2 0xa1c
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#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */
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#define rCCK0_TxFilter1 0xa20
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#define rCCK0_TxFilter2 0xa24
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#define rCCK0_DebugPort 0xa28
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#define rCCK0_DebugPort 0xa28 /* Debug port and TX filter 3 */
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#define rCCK0_FalseAlarmReport 0xa2c
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#define rCCK0_TRSSIReport 0xa50
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#define rCCK0_RxReport 0xa54
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@ -124,22 +127,24 @@
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#define rOFDM0_TRxPathEnable 0xc04
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#define rOFDM0_TRMuxPar 0xc08
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#define rOFDM0_TRSWIsolation 0xc0c
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/* RxIQ DC offset, Rx digital filter, DC notch filter */
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#define rOFDM0_XARxAFE 0xc10
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#define rOFDM0_XARxIQImbalance 0xc14
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#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imbalance matrix */
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#define rOFDM0_XBRxAFE 0xc18
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#define rOFDM0_XBRxIQImbalance 0xc1c
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#define rOFDM0_XCRxAFE 0xc20
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#define rOFDM0_XCRxIQImbalance 0xc24
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#define rOFDM0_XDRxAFE 0xc28
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#define rOFDM0_XDRxIQImbalance 0xc2c
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#define rOFDM0_RxDetector1 0xc30
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#define rOFDM0_RxDetector2 0xc34
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#define rOFDM0_RxDetector3 0xc38
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#define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */
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#define rOFDM0_RxDetector2 0xc34 /* SBD */
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#define rOFDM0_RxDetector3 0xc38 /* Frame Sync */
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/* PD, SBD, Frame Sync & Short-GI */
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#define rOFDM0_RxDetector4 0xc3c
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#define rOFDM0_RxDSP 0xc40
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#define rOFDM0_CFOandDAGC 0xc44
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#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */
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#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */
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#define rOFDM0_CCADropThreshold 0xc48
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#define rOFDM0_ECCAThreshold 0xc4c
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#define rOFDM0_ECCAThreshold 0xc4c /* Energy CCA */
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#define rOFDM0_XAAGCCore1 0xc50
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#define rOFDM0_XAAGCCore2 0xc54
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#define rOFDM0_XBAGCCore1 0xc58
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@ -184,9 +189,9 @@
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#define rOFDM1_PseudoNoiseStateAB 0xd50
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#define rOFDM1_PseudoNoiseStateCD 0xd54
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#define rOFDM1_RxPseudoNoiseWgt 0xd58
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#define rOFDM_PHYCounter1 0xda0
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#define rOFDM_PHYCounter2 0xda4
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#define rOFDM_PHYCounter3 0xda8
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#define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */
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#define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */
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#define rOFDM_PHYCounter3 0xda8 /* MCS not supported */
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#define rOFDM_ShortCFOAB 0xdac
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#define rOFDM_ShortCFOCD 0xdb0
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#define rOFDM_LongCFOAB 0xdb4
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@ -221,14 +226,17 @@
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#define rZebra1_RxLPF 0xb
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#define rZebra1_RxHPFCorner 0xc
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/* Zebra 4 */
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#define rGlobalCtrl 0
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#define rRTL8256_TxLPF 19
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#define rRTL8256_RxLPF 11
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/* RTL8258 */
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#define rRTL8258_TxLPF 0x11
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#define rRTL8258_RxLPF 0x13
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#define rRTL8258_RSSILPF 0xa
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/* Bit Mask - Page 1*/
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#define bBBResetB 0x100
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#define bGlobalResetB 0x200
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#define bOFDMTxStart 0x4
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@ -273,7 +281,7 @@
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#define bCCKTxCRC16 0xffff
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#define bCCKTxStatus 0x1
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#define bOFDMTxStatus 0x2
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/* Bit Mask - Page 8 */
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#define bRFMOD 0x1
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#define bJapanMode 0x2
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#define bCCKTxSC 0x30
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@ -290,13 +298,16 @@
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#define bRFStart 0x0000f000
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#define bBBStart 0x000000f0
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#define bBBCCKStart 0x0000000f
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/* Bit Mask - rFPGA0_RFTiming2 */
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#define bPAEnd 0xf
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#define bTREnd 0x0f000000
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#define bRFEnd 0x000f0000
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/* T2R */
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#define bCCAMask 0x000000f0
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#define bR2RCCAMask 0x00000f00
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#define bHSSI_R2TDelay 0xf8000000
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#define bHSSI_T2RDelay 0xf80000
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/* Channel gain at continue TX. */
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#define bContTxHSSI 0x400
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#define bIGFromCCK 0x200
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#define bAGCAddress 0x3f
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@ -308,6 +319,7 @@
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#define b3WireDataLength 0x800
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#define b3WireAddressLength 0x400
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#define b3WireRFPowerDown 0x1
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/*#define bHWSISelect 0x8 */
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#define b5GPAPEPolarity 0x40000000
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#define b2GPAPEPolarity 0x80000000
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#define bRFSW_TxDefaultAnt 0x3
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@ -318,6 +330,7 @@
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#define bRFSI_3WireClock 0x2
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#define bRFSI_3WireLoad 0x4
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#define bRFSI_3WireRW 0x8
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/* 3-wire total control */
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#define bRFSI_3Wire 0xf
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#define bRFSI_RFENV 0x10
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#define bRFSI_TRSW 0x20
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@ -343,11 +356,11 @@
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#define bLSIG_Length 0x1fffe
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#define bLSIG_Parity 0x20
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#define bCCKRxPhase 0x4
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#define bLSSIReadAddress 0x3f000000
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#define bLSSIReadEdge 0x80000000
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#define bLSSIReadAddress 0x3f000000 /* LSSI "read" address */
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#define bLSSIReadEdge 0x80000000 /* LSSI "read" edge signal */
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#define bLSSIReadBackData 0xfff
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#define bLSSIReadOKFlag 0x1000
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#define bCCKSampleRate 0x8
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#define bCCKSampleRate 0x8 /* 0: 44 MHz, 1: 88MHz */
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#define bRegulator0Standby 0x1
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#define bRegulatorPLLStandby 0x2
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@ -404,10 +417,13 @@
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#define bPSDSineToneScale 0x7f000000
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#define bPSDReport 0xffff
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/* Page 8 */
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#define bOFDMTxSC 0x30000000
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#define bCCKTxOn 0x1
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#define bOFDMTxOn 0x2
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/* Reset debug page and also HWord, LWord */
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#define bDebugPage 0xfff
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/* Reset debug page and LWord */
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#define bDebugItem 0xff
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#define bAntL 0x10
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#define bAntNonHT 0x100
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@ -416,6 +432,7 @@
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#define bAntHT1S1 0x100000
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#define bAntNonHTS1 0x1000000
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/* Page a */
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#define bCCKBBMode 0x3
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#define bCCKTxPowerSaving 0x80
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#define bCCKRxPowerSaving 0x40
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@ -436,7 +453,7 @@
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#define bCCKBistMode 0x80000000
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#define bCCKCCAMask 0x40000000
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#define bCCKTxDACPhase 0x4
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#define bCCKRxADCPhase 0x20000000
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#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */
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#define bCCKr_cp_mode0 0x0100
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#define bCCKTxDCOffset 0xf0
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#define bCCKRxDCOffset 0xf
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@ -450,11 +467,14 @@
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#define bCCKRxIG 0x7f00
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#define bCCKLNAPolarity 0x800000
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#define bCCKRx1stGain 0x7f0000
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/* CCK Rx Initial gain polarity */
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#define bCCKRFExtend 0x20000000
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#define bCCKRxAGCSatLevel 0x1f000000
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#define bCCKRxAGCSatCount 0xe0
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/* AGCSAmp_dly */
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#define bCCKRxRFSettle 0x1f
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#define bCCKFixedRxAGC 0x8000
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/*#define bCCKRxAGCFormat 0x4000 remove to HSSI register 0x824 */
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#define bCCKAntennaPolarity 0x2000
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#define bCCKTxFilterType 0x0c00
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#define bCCKRxAGCReportType 0x0300
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@ -495,6 +515,7 @@
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#define bCCKDefaultRxPath 0xc000000
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#define bCCKOptionRxPath 0x3000000
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/* Page c */
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#define bNumOfSTF 0x3
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#define bShift_L 0xc0
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#define bGI_TH 0xc
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@ -596,7 +617,9 @@
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#define bRxHP_BBP1 0x7000
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#define bRxHP_BBP2 0x70000
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#define bRxHP_BBP3 0x700000
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/* The threshold for high power */
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#define bRSSI_H 0x7f0000
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/* The threshold for ant diversity */
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#define bRSSI_Gen 0x7f000000
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#define bRxSettle_TRSW 0x7
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#define bRxSettle_LNA 0x38
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@ -631,6 +654,7 @@
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#define bRxPD_Delay_TH1 0x38
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#define bRxPD_Delay_TH2 0x1c0
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#define bRxPD_DC_COUNT_MAX 0x600
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/*#define bRxMF_Hold 0x3800*/
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#define bRxPD_Delay_TH 0x8000
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#define bRxProcess_Delay 0xf0000
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#define bRxSearchrange_GI2_Early 0x700000
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@ -656,6 +680,7 @@
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#define bExtLNAGain 0x7c00
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/* Page d */
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#define bSTBCEn 0x4
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#define bAntennaMapping 0x10
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#define bNss 0x20
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@ -665,6 +690,13 @@
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#define bOFDMContinueTx 0x10000000
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#define bOFDMSingleCarrier 0x20000000
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#define bOFDMSingleTone 0x40000000
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/* #define bRxPath1 0x01
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* #define bRxPath2 0x02
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* #define bRxPath3 0x04
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* #define bRxPath4 0x08
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* #define bTxPath1 0x10
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* #define bTxPath2 0x20
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*/
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#define bHTDetect 0x100
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#define bCFOEn 0x10000
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#define bCFOValue 0xfff00000
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@ -677,8 +709,8 @@
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#define bCounter_MCSNoSupport 0xffff
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#define bCounter_FastSync 0xffff
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#define bShortCFO 0xfff
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#define bShortCFOTLength 12
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#define bShortCFOFLength 11
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#define bShortCFOTLength 12 /* total */
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#define bShortCFOFLength 11 /* fraction */
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#define bLongCFO 0x7ff
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#define bLongCFOTLength 11
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#define bLongCFOFLength 11
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@ -755,6 +787,7 @@
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#define bUChCfg 0x7000000
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#define bUpdEqz 0x8000000
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/* Page e */
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#define bTxAGCRate18_06 0x7f7f7f7f
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#define bTxAGCRate54_24 0x7f7f7f7f
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#define bTxAGCRateMCS32 0x7f
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@ -764,8 +797,7 @@
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#define bTxAGCRateMCS11_MCS8 0x7f7f7f7f
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#define bTxAGCRateMCS15_MCS12 0x7f7f7f7f
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#define bRxPesudoNoiseOn 0x20000000
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#define bRxPesudoNoiseOn 0x20000000 /* Rx Pseduo noise */
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#define bRxPesudoNoise_A 0xff
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#define bRxPesudoNoise_B 0xff00
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#define bRxPesudoNoise_C 0xff0000
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@ -775,6 +807,7 @@
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#define bPesudoNoiseState_C 0xffff
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#define bPesudoNoiseState_D 0xffff0000
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/* RF Zebra 1 */
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#define bZebra1_HSSIEnable 0x8
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#define bZebra1_TRxControl 0xc00
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#define bZebra1_TRxGainSetting 0x07f
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@ -785,15 +818,18 @@
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#define bZebra1_TxLPFBW 0x400
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#define bZebra1_RxLPFBW 0x600
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/* Zebra4 */
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#define bRTL8256RegModeCtrl1 0x100
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#define bRTL8256RegModeCtrl0 0x40
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#define bRTL8256_TxLPFBW 0x18
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#define bRTL8256_RxLPFBW 0x600
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/* RTL8258 */
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#define bRTL8258_TxLPFBW 0xc
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#define bRTL8258_RxLPFBW 0xc00
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#define bRTL8258_RSSILPFBW 0xc0
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/* byte enable for sb_write */
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#define bByte0 0x1
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#define bByte1 0x2
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#define bByte2 0x4
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@ -802,6 +838,7 @@
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#define bWord1 0xc
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#define bDWord 0xf
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/* for PutRegsetting & GetRegSetting BitMask */
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#define bMaskByte0 0xff
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#define bMaskByte1 0xff00
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#define bMaskByte2 0xff0000
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@ -810,6 +847,7 @@
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#define bMaskLWord 0x0000ffff
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#define bMaskDWord 0xffffffff
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/* for PutRFRegsetting & GetRFRegSetting BitMask */
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#define bMask12Bits 0xfff
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#define bEnable 0x1
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@ -818,14 +856,14 @@
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#define LeftAntenna 0x0
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#define RightAntenna 0x1
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#define tCheckTxStatus 500
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#define tUpdateRxCounter 100
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#define tCheckTxStatus 500 /* 500 ms */
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#define tUpdateRxCounter 100 /* 100 ms */
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#define rateCCK 0
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#define rateOFDM 1
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#define rateHT 2
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#define bPMAC_End 0x1ff
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#define bPMAC_End 0x1ff /* define Register-End */
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#define bFPGAPHY0_End 0x8ff
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#define bFPGAPHY1_End 0x9ff
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#define bCCKPHY0_End 0xaff
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