Merge branch 'phy-meson-gxl-clean-up-and-improvements'
Jerome Brunet says: ==================== net: phy: meson-gxl: clean-up and improvements This patchset adds defines for the control registers and helpers to access the banked registers. The goal being to make it easier to understand what the driver actually does. Then CONFIG_A6 settings is removed since this statement was without effect Finally interrupt support is added, speeding things up a little This series has been tested on the libretech-cc and khadas VIM Changes since v2 [0]: Drop LPA corruption fix which has been merged through net. Apart from this, series remains the same. [0]: https://lkml.kernel.org/r/20171207142715.32578-1-jbrunet@baylibre.com ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
Коммит
27e9f4b3e5
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@ -24,31 +24,129 @@
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#include <linux/netdevice.h>
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#include <linux/bitfield.h>
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#define TSTCNTL 20
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#define TSTCNTL_READ BIT(15)
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#define TSTCNTL_WRITE BIT(14)
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#define TSTCNTL_REG_BANK_SEL GENMASK(12, 11)
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#define TSTCNTL_TEST_MODE BIT(10)
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#define TSTCNTL_READ_ADDRESS GENMASK(9, 5)
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#define TSTCNTL_WRITE_ADDRESS GENMASK(4, 0)
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#define TSTREAD1 21
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#define TSTWRITE 23
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#define INTSRC_FLAG 29
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#define INTSRC_ANEG_PR BIT(1)
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#define INTSRC_PARALLEL_FAULT BIT(2)
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#define INTSRC_ANEG_LP_ACK BIT(3)
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#define INTSRC_LINK_DOWN BIT(4)
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#define INTSRC_REMOTE_FAULT BIT(5)
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#define INTSRC_ANEG_COMPLETE BIT(6)
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#define INTSRC_MASK 30
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#define BANK_ANALOG_DSP 0
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#define BANK_WOL 1
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#define BANK_BIST 3
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/* WOL Registers */
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#define LPI_STATUS 0xc
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#define LPI_STATUS_RSV12 BIT(12)
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/* BIST Registers */
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#define FR_PLL_CONTROL 0x1b
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#define FR_PLL_DIV0 0x1c
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#define FR_PLL_DIV1 0x1d
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static int meson_gxl_open_banks(struct phy_device *phydev)
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{
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int ret;
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/* Enable Analog and DSP register Bank access by
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* toggling TSTCNTL_TEST_MODE bit in the TSTCNTL register
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*/
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ret = phy_write(phydev, TSTCNTL, 0);
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if (ret)
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return ret;
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ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE);
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if (ret)
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return ret;
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ret = phy_write(phydev, TSTCNTL, 0);
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if (ret)
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return ret;
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return phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE);
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}
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static void meson_gxl_close_banks(struct phy_device *phydev)
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{
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phy_write(phydev, TSTCNTL, 0);
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}
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static int meson_gxl_read_reg(struct phy_device *phydev,
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unsigned int bank, unsigned int reg)
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{
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int ret;
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ret = meson_gxl_open_banks(phydev);
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if (ret)
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goto out;
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ret = phy_write(phydev, TSTCNTL, TSTCNTL_READ |
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FIELD_PREP(TSTCNTL_REG_BANK_SEL, bank) |
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TSTCNTL_TEST_MODE |
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FIELD_PREP(TSTCNTL_READ_ADDRESS, reg));
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if (ret)
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goto out;
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ret = phy_read(phydev, TSTREAD1);
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out:
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/* Close the bank access on our way out */
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meson_gxl_close_banks(phydev);
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return ret;
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}
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static int meson_gxl_write_reg(struct phy_device *phydev,
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unsigned int bank, unsigned int reg,
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uint16_t value)
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{
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int ret;
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ret = meson_gxl_open_banks(phydev);
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if (ret)
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goto out;
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ret = phy_write(phydev, TSTWRITE, value);
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if (ret)
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goto out;
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ret = phy_write(phydev, TSTCNTL, TSTCNTL_WRITE |
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FIELD_PREP(TSTCNTL_REG_BANK_SEL, bank) |
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TSTCNTL_TEST_MODE |
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FIELD_PREP(TSTCNTL_WRITE_ADDRESS, reg));
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out:
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/* Close the bank access on our way out */
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meson_gxl_close_banks(phydev);
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return ret;
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}
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static int meson_gxl_config_init(struct phy_device *phydev)
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{
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/* Enable Analog and DSP register Bank access by */
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phy_write(phydev, 0x14, 0x0000);
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phy_write(phydev, 0x14, 0x0400);
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phy_write(phydev, 0x14, 0x0000);
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phy_write(phydev, 0x14, 0x0400);
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/* Write Analog register 23 */
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phy_write(phydev, 0x17, 0x8E0D);
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phy_write(phydev, 0x14, 0x4417);
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int ret;
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/* Enable fractional PLL */
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phy_write(phydev, 0x17, 0x0005);
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phy_write(phydev, 0x14, 0x5C1B);
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ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_CONTROL, 0x5);
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if (ret)
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return ret;
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/* Program fraction FR_PLL_DIV1 */
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phy_write(phydev, 0x17, 0x029A);
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phy_write(phydev, 0x14, 0x5C1D);
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ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_DIV1, 0x029a);
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if (ret)
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return ret;
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/* Program fraction FR_PLL_DIV1 */
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phy_write(phydev, 0x17, 0xAAAA);
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phy_write(phydev, 0x14, 0x5C1C);
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ret = meson_gxl_write_reg(phydev, BANK_BIST, FR_PLL_DIV0, 0xaaaa);
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if (ret)
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return ret;
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return 0;
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return genphy_config_init(phydev);
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}
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/* This function is provided to cope with the possible failures of this phy
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@ -78,27 +176,8 @@ static int meson_gxl_read_status(struct phy_device *phydev)
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else if (!ret)
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goto read_status_continue;
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/* Need to access WOL bank, make sure the access is open */
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ret = phy_write(phydev, 0x14, 0x0000);
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if (ret)
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return ret;
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ret = phy_write(phydev, 0x14, 0x0400);
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if (ret)
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return ret;
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ret = phy_write(phydev, 0x14, 0x0000);
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if (ret)
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return ret;
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ret = phy_write(phydev, 0x14, 0x0400);
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if (ret)
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return ret;
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/* Request LPI_STATUS WOL register */
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ret = phy_write(phydev, 0x14, 0x8D80);
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if (ret)
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return ret;
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/* Read LPI_STATUS value */
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wol = phy_read(phydev, 0x15);
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/* Aneg is done, let's check everything is fine */
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wol = meson_gxl_read_reg(phydev, BANK_WOL, LPI_STATUS);
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if (wol < 0)
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return wol;
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@ -110,7 +189,7 @@ static int meson_gxl_read_status(struct phy_device *phydev)
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if (exp < 0)
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return exp;
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if (!(wol & BIT(12)) ||
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if (!(wol & LPI_STATUS_RSV12) ||
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((exp & EXPANSION_NWAY) && !(lpa & LPA_LPACK))) {
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/* Looks like aneg failed after all */
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phydev_dbg(phydev, "LPA corruption - aneg restart\n");
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@ -122,16 +201,43 @@ read_status_continue:
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return genphy_read_status(phydev);
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}
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static int meson_gxl_ack_interrupt(struct phy_device *phydev)
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{
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int ret = phy_read(phydev, INTSRC_FLAG);
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return ret < 0 ? ret : 0;
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}
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static int meson_gxl_config_intr(struct phy_device *phydev)
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{
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u16 val;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
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val = INTSRC_ANEG_PR
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| INTSRC_PARALLEL_FAULT
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| INTSRC_ANEG_LP_ACK
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| INTSRC_LINK_DOWN
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| INTSRC_REMOTE_FAULT
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| INTSRC_ANEG_COMPLETE;
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} else {
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val = 0;
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}
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return phy_write(phydev, INTSRC_MASK, val);
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}
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static struct phy_driver meson_gxl_phy[] = {
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{
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.phy_id = 0x01814400,
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.phy_id_mask = 0xfffffff0,
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.name = "Meson GXL Internal PHY",
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.features = PHY_BASIC_FEATURES,
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.flags = PHY_IS_INTERNAL,
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.flags = PHY_IS_INTERNAL | PHY_HAS_INTERRUPT,
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.config_init = meson_gxl_config_init,
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.aneg_done = genphy_aneg_done,
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.read_status = meson_gxl_read_status,
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.ack_interrupt = meson_gxl_ack_interrupt,
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.config_intr = meson_gxl_config_intr,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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},
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@ -149,4 +255,5 @@ MODULE_DEVICE_TABLE(mdio, meson_gxl_tbl);
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MODULE_DESCRIPTION("Amlogic Meson GXL Internal PHY driver");
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MODULE_AUTHOR("Baoqi wang");
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MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
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MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
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MODULE_LICENSE("GPL");
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