KVM: x86: Add emulation for MSR_IA32_MCx_CTL2 MSRs.
This patch adds the emulation of IA32_MCi_CTL2 registers to KVM. A separate mci_ctl2_banks array is used to keep the existing mce_banks register layout intact. In Machine Check Architecture, in addition to MCG_CMCI_P, bit 30 of the per-bank register IA32_MCi_CTL2 controls whether Corrected Machine Check error reporting is enabled. Signed-off-by: Jue Wang <juew@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20220610171134.772566-7-juew@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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087acc4e18
Коммит
281b52780b
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@ -826,6 +826,7 @@ struct kvm_vcpu_arch {
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u64 mcg_ctl;
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u64 mcg_ext_ctl;
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u64 *mce_banks;
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u64 *mci_ctl2_banks;
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/* Cache MMIO info */
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u64 mmio_gva;
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@ -3191,6 +3191,16 @@ static void kvmclock_sync_fn(struct work_struct *work)
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KVMCLOCK_SYNC_PERIOD);
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}
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/* These helpers are safe iff @msr is known to be an MCx bank MSR. */
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static bool is_mci_control_msr(u32 msr)
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{
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return (msr & 3) == 0;
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}
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static bool is_mci_status_msr(u32 msr)
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{
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return (msr & 3) == 1;
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}
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/*
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* On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
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*/
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@ -3209,6 +3219,7 @@ static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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unsigned bank_num = mcg_cap & 0xff;
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u32 msr = msr_info->index;
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u64 data = msr_info->data;
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u32 offset, last_msr;
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switch (msr) {
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case MSR_IA32_MCG_STATUS:
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@ -3222,35 +3233,53 @@ static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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return 1;
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vcpu->arch.mcg_ctl = data;
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break;
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default:
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if (msr >= MSR_IA32_MC0_CTL &&
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msr < MSR_IA32_MCx_CTL(bank_num)) {
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u32 offset = array_index_nospec(
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msr - MSR_IA32_MC0_CTL,
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MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
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case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
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last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
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if (msr > last_msr)
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return 1;
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/* only 0 or all 1s can be written to IA32_MCi_CTL
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* some Linux kernels though clear bit 10 in bank 4 to
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* workaround a BIOS/GART TBL issue on AMD K8s, ignore
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* this to avoid an uncatched #GP in the guest.
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if (!(mcg_cap & MCG_CMCI_P) && (data || !msr_info->host_initiated))
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return 1;
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/* An attempt to write a 1 to a reserved bit raises #GP */
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if (data & ~(MCI_CTL2_CMCI_EN | MCI_CTL2_CMCI_THRESHOLD_MASK))
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return 1;
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offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
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last_msr + 1 - MSR_IA32_MC0_CTL2);
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vcpu->arch.mci_ctl2_banks[offset] = data;
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break;
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case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
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last_msr = MSR_IA32_MCx_CTL(bank_num) - 1;
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if (msr > last_msr)
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return 1;
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/*
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* Only 0 or all 1s can be written to IA32_MCi_CTL, all other
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* values are architecturally undefined. But, some Linux
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* kernels clear bit 10 in bank 4 to workaround a BIOS/GART TLB
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* issue on AMD K8s, allow bit 10 to be clear when setting all
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* other bits in order to avoid an uncaught #GP in the guest.
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*
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* UNIXWARE clears bit 0 of MC1_CTL to ignore
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* correctable, single-bit ECC data errors.
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*/
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if ((offset & 0x3) == 0 &&
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data != 0 && (data | (1 << 10) | 1) != ~(u64)0)
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return -1;
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*/
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if (is_mci_control_msr(msr) &&
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data != 0 && (data | (1 << 10) | 1) != ~(u64)0)
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return 1;
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/* MCi_STATUS */
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if (!msr_info->host_initiated &&
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(offset & 0x3) == 1 && data != 0) {
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if (!can_set_mci_status(vcpu))
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return -1;
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}
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/*
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* All CPUs allow writing 0 to MCi_STATUS MSRs to clear the MSR.
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* AMD-based CPUs allow non-zero values, but if and only if
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* HWCR[McStatusWrEn] is set.
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*/
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if (!msr_info->host_initiated && is_mci_status_msr(msr) &&
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data != 0 && !can_set_mci_status(vcpu))
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return 1;
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vcpu->arch.mce_banks[offset] = data;
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break;
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}
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offset = array_index_nospec(msr - MSR_IA32_MC0_CTL,
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last_msr + 1 - MSR_IA32_MC0_CTL);
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vcpu->arch.mce_banks[offset] = data;
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break;
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default:
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return 1;
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}
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return 0;
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@ -3534,7 +3563,8 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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return 1;
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}
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break;
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case 0x200 ... 0x2ff:
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case 0x200 ... MSR_IA32_MC0_CTL2 - 1:
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case MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) ... 0x2ff:
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return kvm_mtrr_set_msr(vcpu, msr, data);
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case MSR_IA32_APICBASE:
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return kvm_set_apic_base(vcpu, msr_info);
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@ -3704,6 +3734,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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case MSR_IA32_MCG_CTL:
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case MSR_IA32_MCG_STATUS:
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case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
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case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
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return set_msr_mce(vcpu, msr_info);
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case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
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@ -3819,6 +3850,7 @@ static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
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u64 data;
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u64 mcg_cap = vcpu->arch.mcg_cap;
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unsigned bank_num = mcg_cap & 0xff;
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u32 offset, last_msr;
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switch (msr) {
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case MSR_IA32_P5_MC_ADDR:
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@ -3836,16 +3868,27 @@ static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
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case MSR_IA32_MCG_STATUS:
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data = vcpu->arch.mcg_status;
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break;
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default:
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if (msr >= MSR_IA32_MC0_CTL &&
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msr < MSR_IA32_MCx_CTL(bank_num)) {
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u32 offset = array_index_nospec(
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msr - MSR_IA32_MC0_CTL,
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MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
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case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
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last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
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if (msr > last_msr)
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return 1;
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data = vcpu->arch.mce_banks[offset];
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break;
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}
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if (!(mcg_cap & MCG_CMCI_P) && !host)
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return 1;
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offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
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last_msr + 1 - MSR_IA32_MC0_CTL2);
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data = vcpu->arch.mci_ctl2_banks[offset];
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break;
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case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
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last_msr = MSR_IA32_MCx_CTL(bank_num) - 1;
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if (msr > last_msr)
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return 1;
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offset = array_index_nospec(msr - MSR_IA32_MC0_CTL,
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last_msr + 1 - MSR_IA32_MC0_CTL);
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data = vcpu->arch.mce_banks[offset];
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break;
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default:
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return 1;
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}
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*pdata = data;
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@ -3949,7 +3992,8 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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break;
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}
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case MSR_MTRRcap:
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case 0x200 ... 0x2ff:
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case 0x200 ... MSR_IA32_MC0_CTL2 - 1:
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case MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) ... 0x2ff:
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return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
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case 0xcd: /* fsb frequency */
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msr_info->data = 3;
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@ -4065,6 +4109,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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case MSR_IA32_MCG_CTL:
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case MSR_IA32_MCG_STATUS:
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case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
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case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
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return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
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msr_info->host_initiated);
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case MSR_IA32_XSS:
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@ -4842,9 +4887,12 @@ static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
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/* Init IA32_MCG_CTL to all 1s */
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if (mcg_cap & MCG_CTL_P)
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vcpu->arch.mcg_ctl = ~(u64)0;
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/* Init IA32_MCi_CTL to all 1s */
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for (bank = 0; bank < bank_num; bank++)
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/* Init IA32_MCi_CTL to all 1s, IA32_MCi_CTL2 to all 0s */
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for (bank = 0; bank < bank_num; bank++) {
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vcpu->arch.mce_banks[bank*4] = ~(u64)0;
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if (mcg_cap & MCG_CMCI_P)
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vcpu->arch.mci_ctl2_banks[bank] = 0;
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}
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vcpu->arch.apic->nr_lvt_entries =
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KVM_APIC_MAX_NR_LVT_ENTRIES - !(mcg_cap & MCG_CMCI_P);
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@ -11449,7 +11497,9 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
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vcpu->arch.mce_banks = kcalloc(KVM_MAX_MCE_BANKS * 4, sizeof(u64),
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GFP_KERNEL_ACCOUNT);
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if (!vcpu->arch.mce_banks)
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vcpu->arch.mci_ctl2_banks = kcalloc(KVM_MAX_MCE_BANKS, sizeof(u64),
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GFP_KERNEL_ACCOUNT);
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if (!vcpu->arch.mce_banks || !vcpu->arch.mci_ctl2_banks)
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goto fail_free_pio_data;
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vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
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@ -11503,6 +11553,7 @@ free_wbinvd_dirty_mask:
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free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
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fail_free_mce_banks:
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kfree(vcpu->arch.mce_banks);
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kfree(vcpu->arch.mci_ctl2_banks);
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fail_free_pio_data:
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free_page((unsigned long)vcpu->arch.pio_data);
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fail_free_lapic:
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@ -11548,6 +11599,7 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
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kvm_hv_vcpu_uninit(vcpu);
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kvm_pmu_destroy(vcpu);
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kfree(vcpu->arch.mce_banks);
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kfree(vcpu->arch.mci_ctl2_banks);
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kvm_free_lapic(vcpu);
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idx = srcu_read_lock(&vcpu->kvm->srcu);
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kvm_mmu_destroy(vcpu);
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