ARM: EXYNOS: Add clock support for G-Scaler
Add required clock support for G-Scaler for exynos5 Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com> Signed-off-by: Prathyush K <prathyush.k@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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4cbe5a555f
Коммит
2822d3187b
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@ -552,6 +552,68 @@ static struct clksrc_clk exynos5_clk_aclk_66 = {
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.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
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};
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static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
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.clk = {
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.name = "mout_aclk_300_gscl_mid",
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},
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.sources = &exynos5_clkset_aclk,
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.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
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};
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static struct clk *exynos5_clkset_aclk_300_mid1_list[] = {
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[0] = &exynos5_clk_sclk_vpll.clk,
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[1] = &exynos5_clk_mout_cpll.clk,
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};
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static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = {
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.sources = exynos5_clkset_aclk_300_mid1_list,
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.nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_mid1_list),
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};
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static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
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.clk = {
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.name = "mout_aclk_300_gscl_mid1",
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},
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.sources = &exynos5_clkset_aclk_300_gscl_mid1,
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.reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
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};
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static struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
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[0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
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[1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk,
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};
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static struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
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.sources = exynos5_clkset_aclk_300_gscl_list,
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.nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
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};
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static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
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.clk = {
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.name = "mout_aclk_300_gscl",
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},
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.sources = &exynos5_clkset_aclk_300_gscl,
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.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
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};
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static struct clk *exynos5_clk_src_gscl_300_list[] = {
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[0] = &clk_ext_xtal_mux,
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[1] = &exynos5_clk_mout_aclk_300_gscl.clk,
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};
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static struct clksrc_sources exynos5_clk_src_gscl_300 = {
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.sources = exynos5_clk_src_gscl_300_list,
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.nr_sources = ARRAY_SIZE(exynos5_clk_src_gscl_300_list),
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};
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static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
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.clk = {
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.name = "aclk_300_gscl",
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},
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.sources = &exynos5_clk_src_gscl_300,
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.reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
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};
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static struct clk exynos5_init_clocks_off[] = {
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{
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.name = "timers",
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@ -763,6 +825,26 @@ static struct clk exynos5_init_clocks_off[] = {
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.parent = &exynos5_clk_aclk_66.clk,
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.enable = exynos5_clk_ip_peric_ctrl,
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.ctrlbit = (1 << 18),
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}, {
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.name = "gscl",
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.devname = "exynos-gsc.0",
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.enable = exynos5_clk_ip_gscl_ctrl,
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.ctrlbit = (1 << 0),
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}, {
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.name = "gscl",
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.devname = "exynos-gsc.1",
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.enable = exynos5_clk_ip_gscl_ctrl,
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.ctrlbit = (1 << 1),
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}, {
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.name = "gscl",
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.devname = "exynos-gsc.2",
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.enable = exynos5_clk_ip_gscl_ctrl,
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.ctrlbit = (1 << 2),
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}, {
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.name = "gscl",
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.devname = "exynos-gsc.3",
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.enable = exynos5_clk_ip_gscl_ctrl,
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.ctrlbit = (1 << 3),
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
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@ -1225,6 +1307,10 @@ static struct clksrc_clk *exynos5_sysclks[] = {
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&exynos5_clk_aclk_266,
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&exynos5_clk_aclk_200,
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&exynos5_clk_aclk_166,
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&exynos5_clk_aclk_300_gscl,
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&exynos5_clk_mout_aclk_300_gscl,
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&exynos5_clk_mout_aclk_300_gscl_mid,
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&exynos5_clk_mout_aclk_300_gscl_mid1,
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&exynos5_clk_aclk_66_pre,
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&exynos5_clk_aclk_66,
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&exynos5_clk_dout_mmc0,
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