drm: add savage driver
Add driver for savage chipsets. From: Felix Kuehling Signed-off-by: Dave Airlie <airlied@linux.ie>
This commit is contained in:
Dave Airlie
Dave Airlie
Родитель
d27c9b548a
Коммит
282a16749b
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@ -96,3 +96,10 @@ config DRM_VIA
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Choose this option if you have a Via unichrome or compatible video
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chipset. If M is selected the module will be called via.
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config DRM_SAVAGE
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tristate "Savage video cards"
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depends on DRM
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help
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Choose this option if you have a Savage3D/4/SuperSavage/Pro/Twister
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chipset. If M is selected the module will be called savage.
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@ -17,6 +17,7 @@ i915-objs := i915_drv.o i915_dma.o i915_irq.o i915_mem.o
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radeon-objs := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o radeon_irq.o
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ffb-objs := ffb_drv.o ffb_context.o
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sis-objs := sis_drv.o sis_ds.o sis_mm.o
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savage-objs := savage_drv.o savage_bci.o savage_state.o
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via-objs := via_irq.o via_drv.o via_ds.o via_map.o via_mm.o via_dma.o via_verifier.o via_video.o
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ifeq ($(CONFIG_COMPAT),y)
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@ -37,5 +38,7 @@ obj-$(CONFIG_DRM_I830) += i830.o
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obj-$(CONFIG_DRM_I915) += i915.o
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obj-$(CONFIG_DRM_FFB) += ffb.o
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obj-$(CONFIG_DRM_SIS) += sis.o
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obj-$(CONFIG_DRM_SAVAGE)+= savage.o
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obj-$(CONFIG_DRM_VIA) +=via.o
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Разница между файлами не показана из-за своего большого размера
Загрузить разницу
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@ -0,0 +1,209 @@
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/* savage_drm.h -- Public header for the savage driver
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*
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* Copyright 2004 Felix Kuehling
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sub license,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
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* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __SAVAGE_DRM_H__
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#define __SAVAGE_DRM_H__
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#ifndef __SAVAGE_SAREA_DEFINES__
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#define __SAVAGE_SAREA_DEFINES__
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/* 2 heaps (1 for card, 1 for agp), each divided into upto 128
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* regions, subject to a minimum region size of (1<<16) == 64k.
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*
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* Clients may subdivide regions internally, but when sharing between
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* clients, the region size is the minimum granularity.
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*/
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#define SAVAGE_CARD_HEAP 0
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#define SAVAGE_AGP_HEAP 1
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#define SAVAGE_NR_TEX_HEAPS 2
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#define SAVAGE_NR_TEX_REGIONS 16
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#define SAVAGE_LOG_MIN_TEX_REGION_SIZE 16
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#endif /* __SAVAGE_SAREA_DEFINES__ */
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typedef struct _drm_savage_sarea {
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/* LRU lists for texture memory in agp space and on the card.
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*/
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drm_tex_region_t texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS+1];
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unsigned int texAge[SAVAGE_NR_TEX_HEAPS];
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/* Mechanism to validate card state.
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*/
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int ctxOwner;
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} drm_savage_sarea_t, *drm_savage_sarea_ptr;
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/* Savage-specific ioctls
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*/
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#define DRM_SAVAGE_BCI_INIT 0x00
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#define DRM_SAVAGE_BCI_CMDBUF 0x01
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#define DRM_SAVAGE_BCI_EVENT_EMIT 0x02
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#define DRM_SAVAGE_BCI_EVENT_WAIT 0x03
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#define DRM_IOCTL_SAVAGE_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_INIT, drm_savage_init_t)
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#define DRM_IOCTL_SAVAGE_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_CMDBUF, drm_savage_cmdbuf_t)
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#define DRM_IOCTL_SAVAGE_EVENT_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_EMIT, drm_savage_event_emit_t)
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#define DRM_IOCTL_SAVAGE_EVENT_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_WAIT, drm_savage_event_wait_t)
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#define SAVAGE_DMA_PCI 1
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#define SAVAGE_DMA_AGP 3
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typedef struct drm_savage_init {
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enum {
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SAVAGE_INIT_BCI = 1,
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SAVAGE_CLEANUP_BCI = 2
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} func;
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unsigned int sarea_priv_offset;
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/* some parameters */
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unsigned int cob_size;
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unsigned int bci_threshold_lo, bci_threshold_hi;
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unsigned int dma_type;
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/* frame buffer layout */
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unsigned int fb_bpp;
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unsigned int front_offset, front_pitch;
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unsigned int back_offset, back_pitch;
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unsigned int depth_bpp;
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unsigned int depth_offset, depth_pitch;
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/* local textures */
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unsigned int texture_offset;
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unsigned int texture_size;
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/* physical locations of non-permanent maps */
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unsigned long status_offset;
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unsigned long buffers_offset;
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unsigned long agp_textures_offset;
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unsigned long cmd_dma_offset;
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} drm_savage_init_t;
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typedef union drm_savage_cmd_header drm_savage_cmd_header_t;
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typedef struct drm_savage_cmdbuf {
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/* command buffer in client's address space */
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drm_savage_cmd_header_t __user *cmd_addr;
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unsigned int size; /* size of the command buffer in 64bit units */
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unsigned int dma_idx; /* DMA buffer index to use */
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int discard; /* discard DMA buffer when done */
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/* vertex buffer in client's address space */
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unsigned int __user *vb_addr;
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unsigned int vb_size; /* size of client vertex buffer in bytes */
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unsigned int vb_stride; /* stride of vertices in 32bit words */
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/* boxes in client's address space */
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drm_clip_rect_t __user *box_addr;
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unsigned int nbox; /* number of clipping boxes */
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} drm_savage_cmdbuf_t;
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#define SAVAGE_WAIT_2D 0x1 /* wait for 2D idle before updating event tag */
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#define SAVAGE_WAIT_3D 0x2 /* wait for 3D idle before updating event tag */
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#define SAVAGE_WAIT_IRQ 0x4 /* emit or wait for IRQ, not implemented yet */
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typedef struct drm_savage_event {
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unsigned int count;
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unsigned int flags;
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} drm_savage_event_emit_t, drm_savage_event_wait_t;
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/* Commands for the cmdbuf ioctl
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*/
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#define SAVAGE_CMD_STATE 0 /* a range of state registers */
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#define SAVAGE_CMD_DMA_PRIM 1 /* vertices from DMA buffer */
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#define SAVAGE_CMD_VB_PRIM 2 /* vertices from client vertex buffer */
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#define SAVAGE_CMD_DMA_IDX 3 /* indexed vertices from DMA buffer */
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#define SAVAGE_CMD_VB_IDX 4 /* indexed vertices client vertex buffer */
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#define SAVAGE_CMD_CLEAR 5 /* clear buffers */
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#define SAVAGE_CMD_SWAP 6 /* swap buffers */
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/* Primitive types
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*/
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#define SAVAGE_PRIM_TRILIST 0 /* triangle list */
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#define SAVAGE_PRIM_TRISTRIP 1 /* triangle strip */
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#define SAVAGE_PRIM_TRIFAN 2 /* triangle fan */
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#define SAVAGE_PRIM_TRILIST_201 3 /* reorder verts for correct flat
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* shading on s3d */
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/* Skip flags (vertex format)
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*/
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#define SAVAGE_SKIP_Z 0x01
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#define SAVAGE_SKIP_W 0x02
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#define SAVAGE_SKIP_C0 0x04
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#define SAVAGE_SKIP_C1 0x08
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#define SAVAGE_SKIP_S0 0x10
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#define SAVAGE_SKIP_T0 0x20
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#define SAVAGE_SKIP_ST0 0x30
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#define SAVAGE_SKIP_S1 0x40
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#define SAVAGE_SKIP_T1 0x80
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#define SAVAGE_SKIP_ST1 0xc0
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#define SAVAGE_SKIP_ALL_S3D 0x3f
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#define SAVAGE_SKIP_ALL_S4 0xff
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/* Buffer names for clear command
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*/
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#define SAVAGE_FRONT 0x1
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#define SAVAGE_BACK 0x2
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#define SAVAGE_DEPTH 0x4
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/* 64-bit command header
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*/
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union drm_savage_cmd_header {
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struct {
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unsigned char cmd; /* command */
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unsigned char pad0;
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unsigned short pad1;
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unsigned short pad2;
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unsigned short pad3;
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} cmd; /* generic */
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struct {
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unsigned char cmd;
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unsigned char global; /* need idle engine? */
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unsigned short count; /* number of consecutive registers */
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unsigned short start; /* first register */
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unsigned short pad3;
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} state; /* SAVAGE_CMD_STATE */
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struct {
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unsigned char cmd;
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unsigned char prim; /* primitive type */
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unsigned short skip; /* vertex format (skip flags) */
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unsigned short count; /* number of vertices */
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unsigned short start; /* first vertex in DMA/vertex buffer */
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} prim; /* SAVAGE_CMD_DMA_PRIM, SAVAGE_CMD_VB_PRIM */
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struct {
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unsigned char cmd;
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unsigned char prim;
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unsigned short skip;
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unsigned short count; /* number of indices that follow */
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unsigned short pad3;
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} idx; /* SAVAGE_CMD_DMA_IDX, SAVAGE_CMD_VB_IDX */
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struct {
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unsigned char cmd;
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unsigned char pad0;
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unsigned short pad1;
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unsigned int flags;
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} clear0; /* SAVAGE_CMD_CLEAR */
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struct {
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unsigned int mask;
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unsigned int value;
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} clear1; /* SAVAGE_CMD_CLEAR data */
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};
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#endif
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@ -0,0 +1,112 @@
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/* savage_drv.c -- Savage driver for Linux
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*
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* Copyright 2004 Felix Kuehling
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sub license,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
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* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <linux/config.h>
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#include "drmP.h"
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#include "savage_drm.h"
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#include "savage_drv.h"
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#include "drm_pciids.h"
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static int postinit( struct drm_device *dev, unsigned long flags )
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{
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DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n",
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DRIVER_NAME,
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DRIVER_MAJOR,
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DRIVER_MINOR,
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DRIVER_PATCHLEVEL,
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DRIVER_DATE,
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dev->primary.minor,
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pci_pretty_name(dev->pdev)
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);
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return 0;
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}
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static int version( drm_version_t *version )
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{
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int len;
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version->version_major = DRIVER_MAJOR;
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version->version_minor = DRIVER_MINOR;
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version->version_patchlevel = DRIVER_PATCHLEVEL;
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DRM_COPY( version->name, DRIVER_NAME );
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DRM_COPY( version->date, DRIVER_DATE );
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DRM_COPY( version->desc, DRIVER_DESC );
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return 0;
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}
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static struct pci_device_id pciidlist[] = {
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savage_PCI_IDS
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};
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extern drm_ioctl_desc_t savage_ioctls[];
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extern int savage_max_ioctl;
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static struct drm_driver driver = {
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.driver_features =
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DRIVER_USE_AGP | DRIVER_USE_MTRR |
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DRIVER_HAVE_DMA | DRIVER_PCI_DMA,
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.dev_priv_size = sizeof(drm_savage_buf_priv_t),
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.preinit = savage_preinit,
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.postinit = postinit,
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.postcleanup = savage_postcleanup,
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.reclaim_buffers = savage_reclaim_buffers,
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.get_map_ofs = drm_core_get_map_ofs,
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.get_reg_ofs = drm_core_get_reg_ofs,
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.version = version,
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.ioctls = savage_ioctls,
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.dma_ioctl = savage_bci_buffers,
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.fops = {
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.owner = THIS_MODULE,
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.open = drm_open,
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.release = drm_release,
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.ioctl = drm_ioctl,
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.mmap = drm_mmap,
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.poll = drm_poll,
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.fasync = drm_fasync,
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},
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.pci_driver = {
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.name = DRIVER_NAME,
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.id_table = pciidlist,
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}
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};
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static int __init savage_init(void)
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{
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driver.num_ioctls = savage_max_ioctl;
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return drm_init(&driver);
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}
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static void __exit savage_exit(void)
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{
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drm_exit(&driver);
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}
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module_init(savage_init);
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module_exit(savage_exit);
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MODULE_AUTHOR( DRIVER_AUTHOR );
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MODULE_DESCRIPTION( DRIVER_DESC );
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MODULE_LICENSE("GPL and additional rights");
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@ -0,0 +1,579 @@
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/* savage_drv.h -- Private header for the savage driver
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*
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* Copyright 2004 Felix Kuehling
|
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* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sub license,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the
|
||||
* next paragraph) shall be included in all copies or substantial portions
|
||||
* of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
|
||||
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
|
||||
* CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
|
||||
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
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#ifndef __SAVAGE_DRV_H__
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#define __SAVAGE_DRV_H__
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#define DRIVER_AUTHOR "Felix Kuehling"
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#define DRIVER_NAME "savage"
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#define DRIVER_DESC "Savage3D/MX/IX, Savage4, SuperSavage, Twister, ProSavage[DDR]"
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#define DRIVER_DATE "20050313"
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#define DRIVER_MAJOR 2
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#define DRIVER_MINOR 4
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#define DRIVER_PATCHLEVEL 1
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/* Interface history:
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*
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* 1.x The DRM driver from the VIA/S3 code drop, basically a dummy
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* 2.0 The first real DRM
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* 2.1 Scissors registers managed by the DRM, 3D operations clipped by
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* cliprects of the cmdbuf ioctl
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* 2.2 Implemented SAVAGE_CMD_DMA_IDX and SAVAGE_CMD_VB_IDX
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* 2.3 Event counters used by BCI_EVENT_EMIT/WAIT ioctls are now 32 bits
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* wide and thus very long lived (unlikely to ever wrap). The size
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* in the struct was 32 bits before, but only 16 bits were used
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* 2.4 Implemented command DMA. Now drm_savage_init_t.cmd_dma_offset is
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* actually used
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*/
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typedef struct drm_savage_age {
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uint16_t event;
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unsigned int wrap;
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} drm_savage_age_t;
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typedef struct drm_savage_buf_priv {
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struct drm_savage_buf_priv *next;
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struct drm_savage_buf_priv *prev;
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drm_savage_age_t age;
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drm_buf_t *buf;
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} drm_savage_buf_priv_t;
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typedef struct drm_savage_dma_page {
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drm_savage_age_t age;
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unsigned int used, flushed;
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} drm_savage_dma_page_t;
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#define SAVAGE_DMA_PAGE_SIZE 1024 /* in dwords */
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/* Fake DMA buffer size in bytes. 4 pages. Allows a maximum command
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* size of 16kbytes or 4k entries. Minimum requirement would be
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* 10kbytes for 255 40-byte vertices in one drawing command. */
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#define SAVAGE_FAKE_DMA_SIZE (SAVAGE_DMA_PAGE_SIZE*4*4)
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/* interesting bits of hardware state that are saved in dev_priv */
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typedef union {
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struct drm_savage_common_state {
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uint32_t vbaddr;
|
||||
} common;
|
||||
struct {
|
||||
unsigned char pad[sizeof(struct drm_savage_common_state)];
|
||||
uint32_t texctrl, texaddr;
|
||||
uint32_t scstart, new_scstart;
|
||||
uint32_t scend, new_scend;
|
||||
} s3d;
|
||||
struct {
|
||||
unsigned char pad[sizeof(struct drm_savage_common_state)];
|
||||
uint32_t texdescr, texaddr0, texaddr1;
|
||||
uint32_t drawctrl0, new_drawctrl0;
|
||||
uint32_t drawctrl1, new_drawctrl1;
|
||||
} s4;
|
||||
} drm_savage_state_t;
|
||||
|
||||
/* these chip tags should match the ones in the 2D driver in savage_regs.h. */
|
||||
enum savage_family {
|
||||
S3_UNKNOWN = 0,
|
||||
S3_SAVAGE3D,
|
||||
S3_SAVAGE_MX,
|
||||
S3_SAVAGE4,
|
||||
S3_PROSAVAGE,
|
||||
S3_TWISTER,
|
||||
S3_PROSAVAGEDDR,
|
||||
S3_SUPERSAVAGE,
|
||||
S3_SAVAGE2000,
|
||||
S3_LAST
|
||||
};
|
||||
|
||||
#define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX))
|
||||
|
||||
#define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) \
|
||||
|| (chip==S3_PROSAVAGE) \
|
||||
|| (chip==S3_TWISTER) \
|
||||
|| (chip==S3_PROSAVAGEDDR))
|
||||
|
||||
#define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE))
|
||||
|
||||
#define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000))
|
||||
|
||||
#define S3_MOBILE_TWISTER_SERIES(chip) ((chip==S3_TWISTER) \
|
||||
||(chip==S3_PROSAVAGEDDR))
|
||||
|
||||
/* flags */
|
||||
#define SAVAGE_IS_AGP 1
|
||||
|
||||
typedef struct drm_savage_private {
|
||||
drm_savage_sarea_t *sarea_priv;
|
||||
|
||||
drm_savage_buf_priv_t head, tail;
|
||||
|
||||
/* who am I? */
|
||||
enum savage_family chipset;
|
||||
|
||||
unsigned int cob_size;
|
||||
unsigned int bci_threshold_lo, bci_threshold_hi;
|
||||
unsigned int dma_type;
|
||||
|
||||
/* frame buffer layout */
|
||||
unsigned int fb_bpp;
|
||||
unsigned int front_offset, front_pitch;
|
||||
unsigned int back_offset, back_pitch;
|
||||
unsigned int depth_bpp;
|
||||
unsigned int depth_offset, depth_pitch;
|
||||
|
||||
/* bitmap descriptors for swap and clear */
|
||||
unsigned int front_bd, back_bd, depth_bd;
|
||||
|
||||
/* local textures */
|
||||
unsigned int texture_offset;
|
||||
unsigned int texture_size;
|
||||
|
||||
/* memory regions in physical memory */
|
||||
drm_local_map_t *sarea;
|
||||
drm_local_map_t *mmio;
|
||||
drm_local_map_t *fb;
|
||||
drm_local_map_t *aperture;
|
||||
drm_local_map_t *status;
|
||||
drm_local_map_t *agp_textures;
|
||||
drm_local_map_t *cmd_dma;
|
||||
drm_local_map_t fake_dma;
|
||||
|
||||
struct {
|
||||
int handle;
|
||||
unsigned long base, size;
|
||||
} mtrr[3];
|
||||
|
||||
/* BCI and status-related stuff */
|
||||
volatile uint32_t *status_ptr, *bci_ptr;
|
||||
uint32_t status_used_mask;
|
||||
uint16_t event_counter;
|
||||
unsigned int event_wrap;
|
||||
|
||||
/* Savage4 command DMA */
|
||||
drm_savage_dma_page_t *dma_pages;
|
||||
unsigned int nr_dma_pages, first_dma_page, current_dma_page;
|
||||
drm_savage_age_t last_dma_age;
|
||||
|
||||
/* saved hw state for global/local check on S3D */
|
||||
uint32_t hw_draw_ctrl, hw_zbuf_ctrl;
|
||||
/* and for scissors (global, so don't emit if not changed) */
|
||||
uint32_t hw_scissors_start, hw_scissors_end;
|
||||
|
||||
drm_savage_state_t state;
|
||||
|
||||
/* after emitting a wait cmd Savage3D needs 63 nops before next DMA */
|
||||
unsigned int waiting;
|
||||
|
||||
/* config/hardware-dependent function pointers */
|
||||
int (*wait_fifo)(struct drm_savage_private *dev_priv, unsigned int n);
|
||||
int (*wait_evnt)(struct drm_savage_private *dev_priv, uint16_t e);
|
||||
/* Err, there is a macro wait_event in include/linux/wait.h.
|
||||
* Avoid unwanted macro expansion. */
|
||||
void (*emit_clip_rect)(struct drm_savage_private *dev_priv,
|
||||
drm_clip_rect_t *pbox);
|
||||
void (*dma_flush)(struct drm_savage_private *dev_priv);
|
||||
} drm_savage_private_t;
|
||||
|
||||
/* ioctls */
|
||||
extern int savage_bci_cmdbuf(DRM_IOCTL_ARGS);
|
||||
extern int savage_bci_buffers(DRM_IOCTL_ARGS);
|
||||
|
||||
/* BCI functions */
|
||||
extern uint16_t savage_bci_emit_event(drm_savage_private_t *dev_priv,
|
||||
unsigned int flags);
|
||||
extern void savage_freelist_put(drm_device_t *dev, drm_buf_t *buf);
|
||||
extern void savage_dma_reset(drm_savage_private_t *dev_priv);
|
||||
extern void savage_dma_wait(drm_savage_private_t *dev_priv, unsigned int page);
|
||||
extern uint32_t *savage_dma_alloc(drm_savage_private_t *dev_priv,
|
||||
unsigned int n);
|
||||
extern int savage_preinit(drm_device_t *dev, unsigned long chipset);
|
||||
extern int savage_postcleanup(drm_device_t *dev);
|
||||
extern int savage_do_cleanup_bci(drm_device_t *dev);
|
||||
extern void savage_reclaim_buffers(drm_device_t *dev, DRMFILE filp);
|
||||
|
||||
/* state functions */
|
||||
extern void savage_emit_clip_rect_s3d(drm_savage_private_t *dev_priv,
|
||||
drm_clip_rect_t *pbox);
|
||||
extern void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv,
|
||||
drm_clip_rect_t *pbox);
|
||||
|
||||
#define SAVAGE_FB_SIZE_S3 0x01000000 /* 16MB */
|
||||
#define SAVAGE_FB_SIZE_S4 0x02000000 /* 32MB */
|
||||
#define SAVAGE_MMIO_SIZE 0x00080000 /* 512kB */
|
||||
#define SAVAGE_APERTURE_OFFSET 0x02000000 /* 32MB */
|
||||
#define SAVAGE_APERTURE_SIZE 0x05000000 /* 5 tiled surfaces, 16MB each */
|
||||
|
||||
#define SAVAGE_BCI_OFFSET 0x00010000 /* offset of the BCI region
|
||||
* inside the MMIO region */
|
||||
#define SAVAGE_BCI_FIFO_SIZE 32 /* number of entries in on-chip
|
||||
* BCI FIFO */
|
||||
|
||||
/*
|
||||
* MMIO registers
|
||||
*/
|
||||
#define SAVAGE_STATUS_WORD0 0x48C00
|
||||
#define SAVAGE_STATUS_WORD1 0x48C04
|
||||
#define SAVAGE_ALT_STATUS_WORD0 0x48C60
|
||||
|
||||
#define SAVAGE_FIFO_USED_MASK_S3D 0x0001ffff
|
||||
#define SAVAGE_FIFO_USED_MASK_S4 0x001fffff
|
||||
|
||||
/* Copied from savage_bci.h in the 2D driver with some renaming. */
|
||||
|
||||
/* Bitmap descriptors */
|
||||
#define SAVAGE_BD_STRIDE_SHIFT 0
|
||||
#define SAVAGE_BD_BPP_SHIFT 16
|
||||
#define SAVAGE_BD_TILE_SHIFT 24
|
||||
#define SAVAGE_BD_BW_DISABLE (1<<28)
|
||||
/* common: */
|
||||
#define SAVAGE_BD_TILE_LINEAR 0
|
||||
/* savage4, MX, IX, 3D */
|
||||
#define SAVAGE_BD_TILE_16BPP 2
|
||||
#define SAVAGE_BD_TILE_32BPP 3
|
||||
/* twister, prosavage, DDR, supersavage, 2000 */
|
||||
#define SAVAGE_BD_TILE_DEST 1
|
||||
#define SAVAGE_BD_TILE_TEXTURE 2
|
||||
/* GBD - BCI enable */
|
||||
/* savage4, MX, IX, 3D */
|
||||
#define SAVAGE_GBD_BCI_ENABLE 8
|
||||
/* twister, prosavage, DDR, supersavage, 2000 */
|
||||
#define SAVAGE_GBD_BCI_ENABLE_TWISTER 0
|
||||
|
||||
#define SAVAGE_GBD_BIG_ENDIAN 4
|
||||
#define SAVAGE_GBD_LITTLE_ENDIAN 0
|
||||
#define SAVAGE_GBD_64 1
|
||||
|
||||
/* Global Bitmap Descriptor */
|
||||
#define SAVAGE_BCI_GLB_BD_LOW 0x8168
|
||||
#define SAVAGE_BCI_GLB_BD_HIGH 0x816C
|
||||
|
||||
/*
|
||||
* BCI registers
|
||||
*/
|
||||
/* Savage4/Twister/ProSavage 3D registers */
|
||||
#define SAVAGE_DRAWLOCALCTRL_S4 0x1e
|
||||
#define SAVAGE_TEXPALADDR_S4 0x1f
|
||||
#define SAVAGE_TEXCTRL0_S4 0x20
|
||||
#define SAVAGE_TEXCTRL1_S4 0x21
|
||||
#define SAVAGE_TEXADDR0_S4 0x22
|
||||
#define SAVAGE_TEXADDR1_S4 0x23
|
||||
#define SAVAGE_TEXBLEND0_S4 0x24
|
||||
#define SAVAGE_TEXBLEND1_S4 0x25
|
||||
#define SAVAGE_TEXXPRCLR_S4 0x26 /* never used */
|
||||
#define SAVAGE_TEXDESCR_S4 0x27
|
||||
#define SAVAGE_FOGTABLE_S4 0x28
|
||||
#define SAVAGE_FOGCTRL_S4 0x30
|
||||
#define SAVAGE_STENCILCTRL_S4 0x31
|
||||
#define SAVAGE_ZBUFCTRL_S4 0x32
|
||||
#define SAVAGE_ZBUFOFF_S4 0x33
|
||||
#define SAVAGE_DESTCTRL_S4 0x34
|
||||
#define SAVAGE_DRAWCTRL0_S4 0x35
|
||||
#define SAVAGE_DRAWCTRL1_S4 0x36
|
||||
#define SAVAGE_ZWATERMARK_S4 0x37
|
||||
#define SAVAGE_DESTTEXRWWATERMARK_S4 0x38
|
||||
#define SAVAGE_TEXBLENDCOLOR_S4 0x39
|
||||
/* Savage3D/MX/IX 3D registers */
|
||||
#define SAVAGE_TEXPALADDR_S3D 0x18
|
||||
#define SAVAGE_TEXXPRCLR_S3D 0x19 /* never used */
|
||||
#define SAVAGE_TEXADDR_S3D 0x1A
|
||||
#define SAVAGE_TEXDESCR_S3D 0x1B
|
||||
#define SAVAGE_TEXCTRL_S3D 0x1C
|
||||
#define SAVAGE_FOGTABLE_S3D 0x20
|
||||
#define SAVAGE_FOGCTRL_S3D 0x30
|
||||
#define SAVAGE_DRAWCTRL_S3D 0x31
|
||||
#define SAVAGE_ZBUFCTRL_S3D 0x32
|
||||
#define SAVAGE_ZBUFOFF_S3D 0x33
|
||||
#define SAVAGE_DESTCTRL_S3D 0x34
|
||||
#define SAVAGE_SCSTART_S3D 0x35
|
||||
#define SAVAGE_SCEND_S3D 0x36
|
||||
#define SAVAGE_ZWATERMARK_S3D 0x37
|
||||
#define SAVAGE_DESTTEXRWWATERMARK_S3D 0x38
|
||||
/* common stuff */
|
||||
#define SAVAGE_VERTBUFADDR 0x3e
|
||||
#define SAVAGE_BITPLANEWTMASK 0xd7
|
||||
#define SAVAGE_DMABUFADDR 0x51
|
||||
|
||||
/* texture enable bits (needed for tex addr checking) */
|
||||
#define SAVAGE_TEXCTRL_TEXEN_MASK 0x00010000 /* S3D */
|
||||
#define SAVAGE_TEXDESCR_TEX0EN_MASK 0x02000000 /* S4 */
|
||||
#define SAVAGE_TEXDESCR_TEX1EN_MASK 0x04000000 /* S4 */
|
||||
|
||||
/* Global fields in Savage4/Twister/ProSavage 3D registers:
|
||||
*
|
||||
* All texture registers and DrawLocalCtrl are local. All other
|
||||
* registers are global. */
|
||||
|
||||
/* Global fields in Savage3D/MX/IX 3D registers:
|
||||
*
|
||||
* All texture registers are local. DrawCtrl and ZBufCtrl are
|
||||
* partially local. All other registers are global.
|
||||
*
|
||||
* DrawCtrl global fields: cullMode, alphaTestCmpFunc, alphaTestEn, alphaRefVal
|
||||
* ZBufCtrl global fields: zCmpFunc, zBufEn
|
||||
*/
|
||||
#define SAVAGE_DRAWCTRL_S3D_GLOBAL 0x03f3c00c
|
||||
#define SAVAGE_ZBUFCTRL_S3D_GLOBAL 0x00000027
|
||||
|
||||
/* Masks for scissor bits (drawCtrl[01] on s4, scissorStart/End on s3d)
|
||||
*/
|
||||
#define SAVAGE_SCISSOR_MASK_S4 0x00fff7ff
|
||||
#define SAVAGE_SCISSOR_MASK_S3D 0x07ff07ff
|
||||
|
||||
/*
|
||||
* BCI commands
|
||||
*/
|
||||
#define BCI_CMD_NOP 0x40000000
|
||||
#define BCI_CMD_RECT 0x48000000
|
||||
#define BCI_CMD_RECT_XP 0x01000000
|
||||
#define BCI_CMD_RECT_YP 0x02000000
|
||||
#define BCI_CMD_SCANLINE 0x50000000
|
||||
#define BCI_CMD_LINE 0x5C000000
|
||||
#define BCI_CMD_LINE_LAST_PIXEL 0x58000000
|
||||
#define BCI_CMD_BYTE_TEXT 0x63000000
|
||||
#define BCI_CMD_NT_BYTE_TEXT 0x67000000
|
||||
#define BCI_CMD_BIT_TEXT 0x6C000000
|
||||
#define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF)
|
||||
#define BCI_CMD_SET_ROP(cmd, rop) ((cmd) |= ((rop & 0xFF) << 16))
|
||||
#define BCI_CMD_SEND_COLOR 0x00008000
|
||||
|
||||
#define BCI_CMD_CLIP_NONE 0x00000000
|
||||
#define BCI_CMD_CLIP_CURRENT 0x00002000
|
||||
#define BCI_CMD_CLIP_LR 0x00004000
|
||||
#define BCI_CMD_CLIP_NEW 0x00006000
|
||||
|
||||
#define BCI_CMD_DEST_GBD 0x00000000
|
||||
#define BCI_CMD_DEST_PBD 0x00000800
|
||||
#define BCI_CMD_DEST_PBD_NEW 0x00000C00
|
||||
#define BCI_CMD_DEST_SBD 0x00001000
|
||||
#define BCI_CMD_DEST_SBD_NEW 0x00001400
|
||||
|
||||
#define BCI_CMD_SRC_TRANSPARENT 0x00000200
|
||||
#define BCI_CMD_SRC_SOLID 0x00000000
|
||||
#define BCI_CMD_SRC_GBD 0x00000020
|
||||
#define BCI_CMD_SRC_COLOR 0x00000040
|
||||
#define BCI_CMD_SRC_MONO 0x00000060
|
||||
#define BCI_CMD_SRC_PBD_COLOR 0x00000080
|
||||
#define BCI_CMD_SRC_PBD_MONO 0x000000A0
|
||||
#define BCI_CMD_SRC_PBD_COLOR_NEW 0x000000C0
|
||||
#define BCI_CMD_SRC_PBD_MONO_NEW 0x000000E0
|
||||
#define BCI_CMD_SRC_SBD_COLOR 0x00000100
|
||||
#define BCI_CMD_SRC_SBD_MONO 0x00000120
|
||||
#define BCI_CMD_SRC_SBD_COLOR_NEW 0x00000140
|
||||
#define BCI_CMD_SRC_SBD_MONO_NEW 0x00000160
|
||||
|
||||
#define BCI_CMD_PAT_TRANSPARENT 0x00000010
|
||||
#define BCI_CMD_PAT_NONE 0x00000000
|
||||
#define BCI_CMD_PAT_COLOR 0x00000002
|
||||
#define BCI_CMD_PAT_MONO 0x00000003
|
||||
#define BCI_CMD_PAT_PBD_COLOR 0x00000004
|
||||
#define BCI_CMD_PAT_PBD_MONO 0x00000005
|
||||
#define BCI_CMD_PAT_PBD_COLOR_NEW 0x00000006
|
||||
#define BCI_CMD_PAT_PBD_MONO_NEW 0x00000007
|
||||
#define BCI_CMD_PAT_SBD_COLOR 0x00000008
|
||||
#define BCI_CMD_PAT_SBD_MONO 0x00000009
|
||||
#define BCI_CMD_PAT_SBD_COLOR_NEW 0x0000000A
|
||||
#define BCI_CMD_PAT_SBD_MONO_NEW 0x0000000B
|
||||
|
||||
#define BCI_BD_BW_DISABLE 0x10000000
|
||||
#define BCI_BD_TILE_MASK 0x03000000
|
||||
#define BCI_BD_TILE_NONE 0x00000000
|
||||
#define BCI_BD_TILE_16 0x02000000
|
||||
#define BCI_BD_TILE_32 0x03000000
|
||||
#define BCI_BD_GET_BPP(bd) (((bd) >> 16) & 0xFF)
|
||||
#define BCI_BD_SET_BPP(bd, bpp) ((bd) |= (((bpp) & 0xFF) << 16))
|
||||
#define BCI_BD_GET_STRIDE(bd) ((bd) & 0xFFFF)
|
||||
#define BCI_BD_SET_STRIDE(bd, st) ((bd) |= ((st) & 0xFFFF))
|
||||
|
||||
#define BCI_CMD_SET_REGISTER 0x96000000
|
||||
|
||||
#define BCI_CMD_WAIT 0xC0000000
|
||||
#define BCI_CMD_WAIT_3D 0x00010000
|
||||
#define BCI_CMD_WAIT_2D 0x00020000
|
||||
|
||||
#define BCI_CMD_UPDATE_EVENT_TAG 0x98000000
|
||||
|
||||
#define BCI_CMD_DRAW_PRIM 0x80000000
|
||||
#define BCI_CMD_DRAW_INDEXED_PRIM 0x88000000
|
||||
#define BCI_CMD_DRAW_CONT 0x01000000
|
||||
#define BCI_CMD_DRAW_TRILIST 0x00000000
|
||||
#define BCI_CMD_DRAW_TRISTRIP 0x02000000
|
||||
#define BCI_CMD_DRAW_TRIFAN 0x04000000
|
||||
#define BCI_CMD_DRAW_SKIPFLAGS 0x000000ff
|
||||
#define BCI_CMD_DRAW_NO_Z 0x00000001
|
||||
#define BCI_CMD_DRAW_NO_W 0x00000002
|
||||
#define BCI_CMD_DRAW_NO_CD 0x00000004
|
||||
#define BCI_CMD_DRAW_NO_CS 0x00000008
|
||||
#define BCI_CMD_DRAW_NO_U0 0x00000010
|
||||
#define BCI_CMD_DRAW_NO_V0 0x00000020
|
||||
#define BCI_CMD_DRAW_NO_UV0 0x00000030
|
||||
#define BCI_CMD_DRAW_NO_U1 0x00000040
|
||||
#define BCI_CMD_DRAW_NO_V1 0x00000080
|
||||
#define BCI_CMD_DRAW_NO_UV1 0x000000c0
|
||||
|
||||
#define BCI_CMD_DMA 0xa8000000
|
||||
|
||||
#define BCI_W_H(w, h) ((((h) << 16) | (w)) & 0x0FFF0FFF)
|
||||
#define BCI_X_Y(x, y) ((((y) << 16) | (x)) & 0x0FFF0FFF)
|
||||
#define BCI_X_W(x, y) ((((w) << 16) | (x)) & 0x0FFF0FFF)
|
||||
#define BCI_CLIP_LR(l, r) ((((r) << 16) | (l)) & 0x0FFF0FFF)
|
||||
#define BCI_CLIP_TL(t, l) ((((t) << 16) | (l)) & 0x0FFF0FFF)
|
||||
#define BCI_CLIP_BR(b, r) ((((b) << 16) | (r)) & 0x0FFF0FFF)
|
||||
|
||||
#define BCI_LINE_X_Y(x, y) (((y) << 16) | ((x) & 0xFFFF))
|
||||
#define BCI_LINE_STEPS(diag, axi) (((axi) << 16) | ((diag) & 0xFFFF))
|
||||
#define BCI_LINE_MISC(maj, ym, xp, yp, err) \
|
||||
(((maj) & 0x1FFF) | \
|
||||
((ym) ? 1<<13 : 0) | \
|
||||
((xp) ? 1<<14 : 0) | \
|
||||
((yp) ? 1<<15 : 0) | \
|
||||
((err) << 16))
|
||||
|
||||
/*
|
||||
* common commands
|
||||
*/
|
||||
#define BCI_SET_REGISTERS( first, n ) \
|
||||
BCI_WRITE(BCI_CMD_SET_REGISTER | \
|
||||
((uint32_t)(n) & 0xff) << 16 | \
|
||||
((uint32_t)(first) & 0xffff))
|
||||
#define DMA_SET_REGISTERS( first, n ) \
|
||||
DMA_WRITE(BCI_CMD_SET_REGISTER | \
|
||||
((uint32_t)(n) & 0xff) << 16 | \
|
||||
((uint32_t)(first) & 0xffff))
|
||||
|
||||
#define BCI_DRAW_PRIMITIVE(n, type, skip) \
|
||||
BCI_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \
|
||||
((n) << 16))
|
||||
#define DMA_DRAW_PRIMITIVE(n, type, skip) \
|
||||
DMA_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \
|
||||
((n) << 16))
|
||||
|
||||
#define BCI_DRAW_INDICES_S3D(n, type, i0) \
|
||||
BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) | \
|
||||
((n) << 16) | (i0))
|
||||
|
||||
#define BCI_DRAW_INDICES_S4(n, type, skip) \
|
||||
BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) | \
|
||||
(skip) | ((n) << 16))
|
||||
|
||||
#define BCI_DMA(n) \
|
||||
BCI_WRITE(BCI_CMD_DMA | (((n) >> 1) - 1))
|
||||
|
||||
/*
|
||||
* access to MMIO
|
||||
*/
|
||||
#define SAVAGE_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
|
||||
#define SAVAGE_WRITE(reg) DRM_WRITE32( dev_priv->mmio, (reg) )
|
||||
|
||||
/*
|
||||
* access to the burst command interface (BCI)
|
||||
*/
|
||||
#define SAVAGE_BCI_DEBUG 1
|
||||
|
||||
#define BCI_LOCALS volatile uint32_t *bci_ptr;
|
||||
|
||||
#define BEGIN_BCI( n ) do { \
|
||||
dev_priv->wait_fifo(dev_priv, (n)); \
|
||||
bci_ptr = dev_priv->bci_ptr; \
|
||||
} while(0)
|
||||
|
||||
#define BCI_WRITE( val ) *bci_ptr++ = (uint32_t)(val)
|
||||
|
||||
#define BCI_COPY_FROM_USER(src,n) do { \
|
||||
unsigned int i; \
|
||||
for (i = 0; i < n; ++i) { \
|
||||
uint32_t val; \
|
||||
DRM_GET_USER_UNCHECKED(val, &((uint32_t*)(src))[i]); \
|
||||
BCI_WRITE(val); \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
/*
|
||||
* command DMA support
|
||||
*/
|
||||
#define SAVAGE_DMA_DEBUG 1
|
||||
|
||||
#define DMA_LOCALS uint32_t *dma_ptr;
|
||||
|
||||
#define BEGIN_DMA( n ) do { \
|
||||
unsigned int cur = dev_priv->current_dma_page; \
|
||||
unsigned int rest = SAVAGE_DMA_PAGE_SIZE - \
|
||||
dev_priv->dma_pages[cur].used; \
|
||||
if ((n) > rest) { \
|
||||
dma_ptr = savage_dma_alloc(dev_priv, (n)); \
|
||||
} else { /* fast path for small allocations */ \
|
||||
dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle + \
|
||||
cur * SAVAGE_DMA_PAGE_SIZE + \
|
||||
dev_priv->dma_pages[cur].used; \
|
||||
if (dev_priv->dma_pages[cur].used == 0) \
|
||||
savage_dma_wait(dev_priv, cur); \
|
||||
dev_priv->dma_pages[cur].used += (n); \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
#define DMA_WRITE( val ) *dma_ptr++ = (uint32_t)(val)
|
||||
|
||||
#define DMA_COPY_FROM_USER(src,n) do { \
|
||||
DRM_COPY_FROM_USER_UNCHECKED(dma_ptr, (src), (n)*4); \
|
||||
dma_ptr += n; \
|
||||
} while(0)
|
||||
|
||||
#if SAVAGE_DMA_DEBUG
|
||||
#define DMA_COMMIT() do { \
|
||||
unsigned int cur = dev_priv->current_dma_page; \
|
||||
uint32_t *expected = (uint32_t *)dev_priv->cmd_dma->handle + \
|
||||
cur * SAVAGE_DMA_PAGE_SIZE + \
|
||||
dev_priv->dma_pages[cur].used; \
|
||||
if (dma_ptr != expected) { \
|
||||
DRM_ERROR("DMA allocation and use don't match: " \
|
||||
"%p != %p\n", expected, dma_ptr); \
|
||||
savage_dma_reset(dev_priv); \
|
||||
} \
|
||||
} while(0)
|
||||
#else
|
||||
#define DMA_COMMIT() do {/* nothing */} while(0)
|
||||
#endif
|
||||
|
||||
#define DMA_FLUSH() dev_priv->dma_flush(dev_priv)
|
||||
|
||||
/* Buffer aging via event tag
|
||||
*/
|
||||
|
||||
#define UPDATE_EVENT_COUNTER( ) do { \
|
||||
if (dev_priv->status_ptr) { \
|
||||
uint16_t count; \
|
||||
/* coordinate with Xserver */ \
|
||||
count = dev_priv->status_ptr[1023]; \
|
||||
if (count < dev_priv->event_counter) \
|
||||
dev_priv->event_wrap++; \
|
||||
dev_priv->event_counter = count; \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
#define SET_AGE( age, e, w ) do { \
|
||||
(age)->event = e; \
|
||||
(age)->wrap = w; \
|
||||
} while(0)
|
||||
|
||||
#define TEST_AGE( age, e, w ) \
|
||||
( (age)->wrap < (w) || ( (age)->wrap == (w) && (age)->event <= (e) ) )
|
||||
|
||||
#endif /* __SAVAGE_DRV_H__ */
|
||||
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