bnx2x: Utilize FW 7.12.30
This moves bnx2x into using 7.12.30 FW. Said firmware fixes the following: - Packets from a VF with pvid configured which were sent with a different vlan were transmitted instead of being discarded. - FCoE traffic might not recover after a failue while there's traffic to another function. In addition, this FW opens the door for the driver to implement several new features; Specifically, this enhances the device's support for encapsulated packets and will allow vxlan/geneve offloads to be added in the future, as well as vlan filtering offload. Signed-off-by: Yuval Mintz <Yuval.Mintz@qlogic.com> Signed-off-by: Ariel Elior <Ariel.Elior@qlogic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yuval Mintz
David S. Miller
Родитель
b56ea2985d
Коммит
28311f8e7c
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@ -2103,9 +2103,14 @@ int bnx2x_rss(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
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if (rss_obj->udp_rss_v6)
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__set_bit(BNX2X_RSS_IPV6_UDP, ¶ms.rss_flags);
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if (!CHIP_IS_E1x(bp))
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if (!CHIP_IS_E1x(bp)) {
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/* valid only for TUNN_MODE_VXLAN tunnel mode */
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__set_bit(BNX2X_RSS_IPV4_VXLAN, ¶ms.rss_flags);
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__set_bit(BNX2X_RSS_IPV6_VXLAN, ¶ms.rss_flags);
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/* valid only for TUNN_MODE_GRE tunnel mode */
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__set_bit(BNX2X_RSS_GRE_INNER_HDRS, ¶ms.rss_flags);
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__set_bit(BNX2X_RSS_TUNN_INNER_HDRS, ¶ms.rss_flags);
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}
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} else {
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__set_bit(BNX2X_RSS_MODE_DISABLED, ¶ms.rss_flags);
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}
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@ -3677,7 +3682,7 @@ static void bnx2x_update_pbds_gso_enc(struct sk_buff *skb,
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pbd2->fw_ip_hdr_to_payload_w =
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hlen_w - ((sizeof(struct ipv6hdr)) >> 1);
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pbd_e2->data.tunnel_data.flags |=
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ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER;
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ETH_TUNNEL_DATA_IPV6_OUTER;
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}
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pbd2->tcp_send_seq = bswab32(inner_tcp_hdr(skb)->seq);
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@ -936,9 +936,7 @@ static inline int bnx2x_func_start(struct bnx2x *bp)
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else /* CHIP_IS_E1X */
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start_params->network_cos_mode = FW_WRR;
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start_params->tunnel_mode = TUNN_MODE_GRE;
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start_params->gre_tunnel_type = IPGRE_TUNNEL;
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start_params->inner_gre_rss_en = 1;
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start_params->inner_rss = 1;
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if (IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
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start_params->class_fail_ethtype = ETH_P_FIP;
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@ -1850,6 +1850,8 @@ static void bnx2x_dcbx_fw_struct(struct bnx2x *bp,
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if (bp->dcbx_port_params.ets.cos_params[cos].
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pri_bitmask & pri_bit)
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tt2cos[pri].cos = cos;
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pfc_fw_cfg->dcb_outer_pri[pri] = ttp[pri];
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}
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/* we never want the FW to add a 0 vlan tag */
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@ -372,7 +372,7 @@
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#define MAX_COS_NUMBER 4
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#define MAX_TRAFFIC_TYPES 8
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#define MAX_PFC_PRIORITIES 8
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#define MAX_VLAN_PRIORITIES 8
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/* used by array traffic_type_to_priority[] to mark traffic type \
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that is not mapped to priority*/
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#define LLFC_TRAFFIC_TYPE_TO_PRIORITY_UNMAPPED 0xFF
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@ -2898,8 +2898,8 @@ struct afex_stats {
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};
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#define BCM_5710_FW_MAJOR_VERSION 7
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#define BCM_5710_FW_MINOR_VERSION 10
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#define BCM_5710_FW_REVISION_VERSION 51
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#define BCM_5710_FW_MINOR_VERSION 12
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#define BCM_5710_FW_REVISION_VERSION 30
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#define BCM_5710_FW_ENGINEERING_VERSION 0
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#define BCM_5710_FW_COMPILE_FLAGS 1
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@ -3901,7 +3901,11 @@ struct eth_fast_path_rx_cqe {
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__le16 len_on_bd;
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struct parsing_flags pars_flags;
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union eth_sgl_or_raw_data sgl_or_raw_data;
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__le32 reserved1[7];
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u8 tunn_type;
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u8 tunn_inner_hdrs_offset;
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__le16 reserved1;
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__le32 tunn_tenant_id;
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__le32 padding[5];
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u32 marker;
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};
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@ -4012,8 +4016,8 @@ struct eth_tunnel_data {
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__le16 pseudo_csum;
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u8 ip_hdr_start_inner_w;
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u8 flags;
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#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0)
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#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0
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#define ETH_TUNNEL_DATA_IPV6_OUTER (0x1<<0)
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#define ETH_TUNNEL_DATA_IPV6_OUTER_SHIFT 0
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#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1)
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#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1
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};
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@ -4120,16 +4124,12 @@ struct eth_rss_update_ramrod_data {
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#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 6
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#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY (0x1<<7)
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#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY_SHIFT 7
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#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<8)
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#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 8
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#define ETH_RSS_UPDATE_RAMROD_DATA_NVGRE_KEY_ENTROPY_CAPABILITY (0x1<<9)
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#define ETH_RSS_UPDATE_RAMROD_DATA_NVGRE_KEY_ENTROPY_CAPABILITY_SHIFT 9
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#define ETH_RSS_UPDATE_RAMROD_DATA_GRE_INNER_HDRS_CAPABILITY (0x1<<10)
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#define ETH_RSS_UPDATE_RAMROD_DATA_GRE_INNER_HDRS_CAPABILITY_SHIFT 10
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#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<11)
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#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 11
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#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED (0xF<<12)
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#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED_SHIFT 12
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#define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY (0x1<<8)
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#define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY_SHIFT 8
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#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<9)
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#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 9
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#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED (0x3F<<10)
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#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED_SHIFT 10
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u8 rss_result_mask;
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u8 reserved3;
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__le16 reserved4;
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@ -4314,6 +4314,18 @@ enum eth_tunnel_non_lso_csum_location {
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MAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION
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};
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enum eth_tunn_type {
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TUNN_TYPE_NONE,
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TUNN_TYPE_VXLAN,
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TUNN_TYPE_L2_GRE,
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TUNN_TYPE_IPV4_GRE,
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TUNN_TYPE_IPV6_GRE,
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TUNN_TYPE_L2_GENEVE,
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TUNN_TYPE_IPV4_GENEVE,
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TUNN_TYPE_IPV6_GENEVE,
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MAX_ETH_TUNN_TYPE
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};
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/*
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* Tx regular BD structure
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*/
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@ -4758,6 +4770,9 @@ struct afex_vif_list_ramrod_data {
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__le16 reserved1;
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};
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struct c2s_pri_trans_table_entry {
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u8 val[MAX_VLAN_PRIORITIES];
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};
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/*
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* cfc delete event data
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@ -5246,6 +5261,7 @@ struct flow_control_configuration {
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u8 dont_add_pri_0_en;
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u8 reserved1;
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__le32 reserved2;
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u8 dcb_outer_pri[MAX_TRAFFIC_TYPES];
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};
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@ -5260,18 +5276,25 @@ struct function_start_data {
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u8 path_id;
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u8 network_cos_mode;
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u8 dmae_cmd_id;
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u8 tunnel_mode;
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u8 gre_tunnel_type;
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u8 tunn_clss_en;
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u8 inner_gre_rss_en;
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u8 sd_accept_mf_clss_fail;
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u8 no_added_tags;
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__le16 reserved0;
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__le32 reserved1;
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u8 inner_clss_vxlan;
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u8 inner_clss_l2gre;
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u8 inner_clss_l2geneve;
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u8 inner_rss;
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__le16 vxlan_dst_port;
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__le16 geneve_dst_port;
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u8 sd_accept_mf_clss_fail;
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u8 sd_accept_mf_clss_fail_match_ethtype;
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__le16 sd_accept_mf_clss_fail_ethtype;
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__le16 sd_vlan_eth_type;
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u8 sd_vlan_force_pri_flg;
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u8 sd_vlan_force_pri_val;
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u8 sd_accept_mf_clss_fail_match_ethtype;
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u8 no_added_tags;
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u8 c2s_pri_tt_valid;
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u8 c2s_pri_default;
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u8 reserved2[6];
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struct c2s_pri_trans_table_entry c2s_pri_trans_table;
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};
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struct function_update_data {
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@ -5289,11 +5312,12 @@ struct function_update_data {
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u8 tx_switch_suspend;
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u8 echo;
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u8 update_tunn_cfg_flg;
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u8 tunnel_mode;
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u8 gre_tunnel_type;
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u8 tunn_clss_en;
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u8 inner_gre_rss_en;
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u8 inner_clss_vxlan;
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u8 inner_clss_l2gre;
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u8 inner_clss_l2geneve;
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u8 inner_rss;
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__le16 vxlan_dst_port;
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__le16 geneve_dst_port;
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u8 sd_vlan_force_pri_change_flg;
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u8 sd_vlan_force_pri_flg;
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u8 sd_vlan_force_pri_val;
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@ -5302,6 +5326,8 @@ struct function_update_data {
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u8 reserved1;
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__le16 sd_vlan_tag;
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__le16 sd_vlan_eth_type;
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__le16 reserved0;
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__le32 reserved2;
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};
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/*
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@ -5330,15 +5356,6 @@ struct fw_version {
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#define __FW_VERSION_RESERVED_SHIFT 4
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};
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/* GRE Tunnel Mode */
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enum gre_tunnel_type {
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NVGRE_TUNNEL,
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L2GRE_TUNNEL,
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IPGRE_TUNNEL,
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MAX_GRE_TUNNEL_TYPE
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};
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/*
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* Dynamic Host-Coalescing - Driver(host) counters
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*/
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@ -5568,6 +5568,8 @@ static void bnx2x_eq_int(struct bnx2x *bp)
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BNX2X_STATE_OPEN):
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case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
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BNX2X_STATE_OPENING_WAIT4_PORT):
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case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
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BNX2X_STATE_CLOSING_WAIT4_HALT):
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cid = elem->message.data.eth_event.echo &
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BNX2X_SWCID_MASK;
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DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
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@ -4060,8 +4060,14 @@ static int bnx2x_setup_rss(struct bnx2x *bp,
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if (test_bit(BNX2X_RSS_IPV6_UDP, &p->rss_flags))
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caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY;
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if (test_bit(BNX2X_RSS_GRE_INNER_HDRS, &p->rss_flags))
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caps |= ETH_RSS_UPDATE_RAMROD_DATA_GRE_INNER_HDRS_CAPABILITY;
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if (test_bit(BNX2X_RSS_IPV4_VXLAN, &p->rss_flags))
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caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY;
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if (test_bit(BNX2X_RSS_IPV6_VXLAN, &p->rss_flags))
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caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY;
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if (test_bit(BNX2X_RSS_TUNN_INNER_HDRS, &p->rss_flags))
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caps |= ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY;
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/* RSS keys */
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if (test_bit(BNX2X_RSS_SET_SRCH, &p->rss_flags)) {
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@ -5669,10 +5675,14 @@ static inline int bnx2x_func_send_start(struct bnx2x *bp,
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rdata->sd_vlan_tag = cpu_to_le16(start_params->sd_vlan_tag);
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rdata->path_id = BP_PATH(bp);
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rdata->network_cos_mode = start_params->network_cos_mode;
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rdata->tunnel_mode = start_params->tunnel_mode;
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rdata->gre_tunnel_type = start_params->gre_tunnel_type;
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rdata->inner_gre_rss_en = start_params->inner_gre_rss_en;
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rdata->vxlan_dst_port = cpu_to_le16(4789);
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rdata->vxlan_dst_port = cpu_to_le16(start_params->vxlan_dst_port);
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rdata->geneve_dst_port = cpu_to_le16(start_params->geneve_dst_port);
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rdata->inner_clss_l2gre = start_params->inner_clss_l2gre;
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rdata->inner_clss_l2geneve = start_params->inner_clss_l2geneve;
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rdata->inner_clss_vxlan = start_params->inner_clss_vxlan;
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rdata->inner_rss = start_params->inner_rss;
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rdata->sd_accept_mf_clss_fail = start_params->class_fail;
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if (start_params->class_fail_ethtype) {
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rdata->sd_accept_mf_clss_fail_match_ethtype = 1;
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@ -5690,6 +5700,14 @@ static inline int bnx2x_func_send_start(struct bnx2x *bp,
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cpu_to_le16(0x8100);
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rdata->no_added_tags = start_params->no_added_tags;
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rdata->c2s_pri_tt_valid = start_params->c2s_pri_valid;
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if (rdata->c2s_pri_tt_valid) {
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memcpy(rdata->c2s_pri_trans_table.val,
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start_params->c2s_pri,
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MAX_VLAN_PRIORITIES);
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rdata->c2s_pri_default = start_params->c2s_pri_default;
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}
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/* No need for an explicit memory barrier here as long we would
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* need to ensure the ordering of writing to the SPQ element
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* and updating of the SPQ producer which involves a memory
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@ -5750,15 +5768,22 @@ static inline int bnx2x_func_send_switch_update(struct bnx2x *bp,
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if (test_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
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&switch_update_params->changes)) {
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rdata->update_tunn_cfg_flg = 1;
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if (test_bit(BNX2X_F_UPDATE_TUNNEL_CLSS_EN,
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if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GRE,
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&switch_update_params->changes))
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rdata->tunn_clss_en = 1;
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if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_GRE_RSS_EN,
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rdata->inner_clss_l2gre = 1;
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if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN,
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&switch_update_params->changes))
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rdata->inner_gre_rss_en = 1;
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rdata->tunnel_mode = switch_update_params->tunnel_mode;
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rdata->gre_tunnel_type = switch_update_params->gre_tunnel_type;
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rdata->vxlan_dst_port = cpu_to_le16(4789);
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rdata->inner_clss_vxlan = 1;
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if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GENEVE,
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&switch_update_params->changes))
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rdata->inner_clss_l2geneve = 1;
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if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_RSS,
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&switch_update_params->changes))
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rdata->inner_rss = 1;
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rdata->vxlan_dst_port =
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cpu_to_le16(switch_update_params->vxlan_dst_port);
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rdata->geneve_dst_port =
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cpu_to_le16(switch_update_params->geneve_dst_port);
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}
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rdata->echo = SWITCH_UPDATE;
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@ -5885,6 +5910,8 @@ static inline int bnx2x_func_send_tx_start(struct bnx2x *bp,
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rdata->traffic_type_to_priority_cos[i] =
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tx_start_params->traffic_type_to_priority_cos[i];
|
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|
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for (i = 0; i < MAX_TRAFFIC_TYPES; i++)
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rdata->dcb_outer_pri[i] = tx_start_params->dcb_outer_pri[i];
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/* No need for an explicit memory barrier here as long as we
|
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* ensure the ordering of writing to the SPQ element
|
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* and updating of the SPQ producer which involves a memory
|
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@ -711,7 +711,10 @@ enum {
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BNX2X_RSS_IPV6,
|
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BNX2X_RSS_IPV6_TCP,
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BNX2X_RSS_IPV6_UDP,
|
||||
BNX2X_RSS_GRE_INNER_HDRS,
|
||||
|
||||
BNX2X_RSS_IPV4_VXLAN,
|
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BNX2X_RSS_IPV6_VXLAN,
|
||||
BNX2X_RSS_TUNN_INNER_HDRS,
|
||||
};
|
||||
|
||||
struct bnx2x_config_rss_params {
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||||
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@ -1105,8 +1108,10 @@ enum {
|
|||
BNX2X_F_UPDATE_VLAN_FORCE_PRIO_CHNG,
|
||||
BNX2X_F_UPDATE_VLAN_FORCE_PRIO_FLAG,
|
||||
BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
|
||||
BNX2X_F_UPDATE_TUNNEL_CLSS_EN,
|
||||
BNX2X_F_UPDATE_TUNNEL_INNER_GRE_RSS_EN,
|
||||
BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GRE,
|
||||
BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN,
|
||||
BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GENEVE,
|
||||
BNX2X_F_UPDATE_TUNNEL_INNER_RSS,
|
||||
};
|
||||
|
||||
/* Allowed Function states */
|
||||
|
|
@ -1171,19 +1176,23 @@ struct bnx2x_func_start_params {
|
|||
/* Function cos mode */
|
||||
u8 network_cos_mode;
|
||||
|
||||
/* TUNN_MODE_NONE/TUNN_MODE_VXLAN/TUNN_MODE_GRE */
|
||||
u8 tunnel_mode;
|
||||
/* UDP dest port for VXLAN */
|
||||
u16 vxlan_dst_port;
|
||||
|
||||
/* tunneling classification enablement */
|
||||
u8 tunn_clss_en;
|
||||
/* UDP dest port for Geneve */
|
||||
u16 geneve_dst_port;
|
||||
|
||||
/* NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */
|
||||
u8 gre_tunnel_type;
|
||||
/* Enable inner Rx classifications for L2GRE packets */
|
||||
u8 inner_clss_l2gre;
|
||||
|
||||
/* Enables Inner GRE RSS on the function, depends on the client RSS
|
||||
* capailities
|
||||
*/
|
||||
u8 inner_gre_rss_en;
|
||||
/* Enable inner Rx classifications for L2-Geneve packets */
|
||||
u8 inner_clss_l2geneve;
|
||||
|
||||
/* Enable inner Rx classification for vxlan packets */
|
||||
u8 inner_clss_vxlan;
|
||||
|
||||
/* Enable RSS according to inner header */
|
||||
u8 inner_rss;
|
||||
|
||||
/* Allows accepting of packets failing MF classification, possibly
|
||||
* only matching a given ethertype
|
||||
|
|
@ -1200,6 +1209,11 @@ struct bnx2x_func_start_params {
|
|||
|
||||
/* Prevent inner vlans from being added by FW */
|
||||
u8 no_added_tags;
|
||||
|
||||
/* Inner-to-Outer vlan priority mapping */
|
||||
u8 c2s_pri[MAX_VLAN_PRIORITIES];
|
||||
u8 c2s_pri_default;
|
||||
u8 c2s_pri_valid;
|
||||
};
|
||||
|
||||
struct bnx2x_func_switch_update_params {
|
||||
|
|
@ -1207,8 +1221,8 @@ struct bnx2x_func_switch_update_params {
|
|||
u16 vlan;
|
||||
u16 vlan_eth_type;
|
||||
u8 vlan_force_prio;
|
||||
u8 tunnel_mode;
|
||||
u8 gre_tunnel_type;
|
||||
u16 vxlan_dst_port;
|
||||
u16 geneve_dst_port;
|
||||
};
|
||||
|
||||
struct bnx2x_func_afex_update_params {
|
||||
|
|
@ -1229,6 +1243,7 @@ struct bnx2x_func_tx_start_params {
|
|||
u8 dcb_enabled;
|
||||
u8 dcb_version;
|
||||
u8 dont_add_pri_0_en;
|
||||
u8 dcb_outer_pri[MAX_TRAFFIC_TYPES];
|
||||
};
|
||||
|
||||
struct bnx2x_func_set_timesync_params {
|
||||
|
|
|
|||
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