Support for "split lock" detection:
- Atomic operations (lock prefixed instructions) which span two cache
lines have to acquire the global bus lock. This is at least 1k cycles
slower than an atomic operation within a cache line and disrupts
performance on other cores. Aside of performance disruption this is
a unpriviledged form of DoS.
Some newer CPUs have the capability to raise an #AC trap when such an
operation is attempted. The detection is by default enabled in warning
mode which will warn once when a user space application is caught. A
command line option allows to disable the detection or to select fatal
mode which will terminate offending applications with SIGBUS.
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Merge tag 'x86-splitlock-2020-03-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 splitlock updates from Thomas Gleixner:
"Support for 'split lock' detection:
Atomic operations (lock prefixed instructions) which span two cache
lines have to acquire the global bus lock. This is at least 1k cycles
slower than an atomic operation within a cache line and disrupts
performance on other cores. Aside of performance disruption this is a
unpriviledged form of DoS.
Some newer CPUs have the capability to raise an #AC trap when such an
operation is attempted. The detection is by default enabled in warning
mode which will warn once when a user space application is caught. A
command line option allows to disable the detection or to select fatal
mode which will terminate offending applications with SIGBUS"
* tag 'x86-splitlock-2020-03-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/split_lock: Avoid runtime reads of the TEST_CTRL MSR
x86/split_lock: Rework the initialization flow of split lock detection
x86/split_lock: Enable split lock detection by kernel
This commit is contained in:
Linus Torvalds
Коммит
2853d5fafb
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|
@ -4711,6 +4711,28 @@
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spia_pedr=
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spia_peddr=
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split_lock_detect=
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[X86] Enable split lock detection
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When enabled (and if hardware support is present), atomic
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instructions that access data across cache line
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boundaries will result in an alignment check exception.
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off - not enabled
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warn - the kernel will emit rate limited warnings
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about applications triggering the #AC
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exception. This mode is the default on CPUs
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that supports split lock detection.
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fatal - the kernel will send SIGBUS to applications
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that trigger the #AC exception.
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If an #AC exception is hit in the kernel or in
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firmware (i.e. not while executing in user mode)
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the kernel will oops in either "warn" or "fatal"
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mode.
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srcutree.counter_wrap_check [KNL]
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Specifies how frequently to check for
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grace-period sequence counter wrap for the
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@ -40,4 +40,16 @@ int mwait_usable(const struct cpuinfo_x86 *);
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unsigned int x86_family(unsigned int sig);
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unsigned int x86_model(unsigned int sig);
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unsigned int x86_stepping(unsigned int sig);
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#ifdef CONFIG_CPU_SUP_INTEL
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extern void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c);
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extern void switch_to_sld(unsigned long tifn);
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extern bool handle_user_split_lock(struct pt_regs *regs, long error_code);
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#else
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static inline void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c) {}
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static inline void switch_to_sld(unsigned long tifn) {}
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static inline bool handle_user_split_lock(struct pt_regs *regs, long error_code)
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{
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return false;
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}
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#endif
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#endif /* _ASM_X86_CPU_H */
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@ -285,6 +285,7 @@
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#define X86_FEATURE_CQM_MBM_LOCAL (11*32+ 3) /* LLC Local MBM monitoring */
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#define X86_FEATURE_FENCE_SWAPGS_USER (11*32+ 4) /* "" LFENCE in user entry SWAPGS path */
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#define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */
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#define X86_FEATURE_SPLIT_LOCK_DETECT (11*32+ 6) /* #AC for split lock */
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/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
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#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
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@ -368,6 +369,7 @@
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#define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */
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#define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */
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#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
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#define X86_FEATURE_CORE_CAPABILITIES (18*32+30) /* "" IA32_CORE_CAPABILITIES MSR */
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#define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypass Disable */
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/*
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@ -41,6 +41,10 @@
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/* Intel MSRs. Some also available on other CPUs */
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#define MSR_TEST_CTRL 0x00000033
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#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29
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#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT)
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#define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */
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#define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */
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#define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */
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@ -70,6 +74,11 @@
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*/
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#define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U)
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/* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */
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#define MSR_IA32_CORE_CAPS 0x000000cf
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#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5
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#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT)
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#define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
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#define NHM_C3_AUTO_DEMOTE (1UL << 25)
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#define NHM_C1_AUTO_DEMOTE (1UL << 26)
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|
|
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|
@ -92,6 +92,7 @@ struct thread_info {
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#define TIF_NOCPUID 15 /* CPUID is not accessible in userland */
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#define TIF_NOTSC 16 /* TSC is not accessible in userland */
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#define TIF_IA32 17 /* IA32 compatibility process */
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#define TIF_SLD 18 /* Restore split lock detection on context switch */
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#define TIF_MEMDIE 20 /* is terminating due to OOM killer */
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#define TIF_POLLING_NRFLAG 21 /* idle is polling for TIF_NEED_RESCHED */
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#define TIF_IO_BITMAP 22 /* uses I/O bitmap */
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@ -121,6 +122,7 @@ struct thread_info {
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#define _TIF_NOCPUID (1 << TIF_NOCPUID)
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#define _TIF_NOTSC (1 << TIF_NOTSC)
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#define _TIF_IA32 (1 << TIF_IA32)
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#define _TIF_SLD (1 << TIF_SLD)
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#define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG)
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#define _TIF_IO_BITMAP (1 << TIF_IO_BITMAP)
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#define _TIF_FORCED_TF (1 << TIF_FORCED_TF)
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@ -139,7 +141,7 @@ struct thread_info {
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/* flags to check in __switch_to() */
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#define _TIF_WORK_CTXSW_BASE \
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(_TIF_NOCPUID | _TIF_NOTSC | _TIF_BLOCKSTEP | \
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_TIF_SSBD | _TIF_SPEC_FORCE_UPDATE)
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_TIF_SSBD | _TIF_SPEC_FORCE_UPDATE | _TIF_SLD)
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/*
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* Avoid calls to __switch_to_xtra() on UP as STIBP is not evaluated.
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|
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@ -1224,6 +1224,8 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c)
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cpu_set_bug_bits(c);
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cpu_set_core_cap_bits(c);
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fpu__init_system(c);
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#ifdef CONFIG_X86_32
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|
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@ -19,6 +19,8 @@
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#include <asm/microcode_intel.h>
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#include <asm/hwcap2.h>
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#include <asm/elf.h>
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#include <asm/cpu_device_id.h>
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#include <asm/cmdline.h>
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#ifdef CONFIG_X86_64
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#include <linux/topology.h>
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@ -31,6 +33,20 @@
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#include <asm/apic.h>
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#endif
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enum split_lock_detect_state {
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sld_off = 0,
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sld_warn,
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sld_fatal,
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};
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/*
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* Default to sld_off because most systems do not support split lock detection
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* split_lock_setup() will switch this to sld_warn on systems that support
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* split lock detect, unless there is a command line override.
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*/
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static enum split_lock_detect_state sld_state __ro_after_init = sld_off;
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static u64 msr_test_ctrl_cache __ro_after_init;
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/*
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* Processors which have self-snooping capability can handle conflicting
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* memory type across CPUs by snooping its own cache. However, there exists
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@ -570,6 +586,8 @@ static void init_intel_misc_features(struct cpuinfo_x86 *c)
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wrmsrl(MSR_MISC_FEATURES_ENABLES, msr);
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}
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static void split_lock_init(void);
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static void init_intel(struct cpuinfo_x86 *c)
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{
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early_init_intel(c);
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@ -684,6 +702,8 @@ static void init_intel(struct cpuinfo_x86 *c)
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tsx_enable();
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if (tsx_ctrl_state == TSX_CTRL_DISABLE)
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tsx_disable();
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split_lock_init();
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}
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#ifdef CONFIG_X86_32
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@ -945,3 +965,166 @@ static const struct cpu_dev intel_cpu_dev = {
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};
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cpu_dev_register(intel_cpu_dev);
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#undef pr_fmt
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#define pr_fmt(fmt) "x86/split lock detection: " fmt
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static const struct {
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const char *option;
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enum split_lock_detect_state state;
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} sld_options[] __initconst = {
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{ "off", sld_off },
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{ "warn", sld_warn },
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{ "fatal", sld_fatal },
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};
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static inline bool match_option(const char *arg, int arglen, const char *opt)
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{
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int len = strlen(opt);
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return len == arglen && !strncmp(arg, opt, len);
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}
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static bool split_lock_verify_msr(bool on)
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{
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u64 ctrl, tmp;
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if (rdmsrl_safe(MSR_TEST_CTRL, &ctrl))
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return false;
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if (on)
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ctrl |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
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else
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ctrl &= ~MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
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if (wrmsrl_safe(MSR_TEST_CTRL, ctrl))
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return false;
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rdmsrl(MSR_TEST_CTRL, tmp);
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return ctrl == tmp;
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}
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static void __init split_lock_setup(void)
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{
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enum split_lock_detect_state state = sld_warn;
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char arg[20];
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int i, ret;
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if (!split_lock_verify_msr(false)) {
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pr_info("MSR access failed: Disabled\n");
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return;
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}
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ret = cmdline_find_option(boot_command_line, "split_lock_detect",
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arg, sizeof(arg));
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if (ret >= 0) {
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for (i = 0; i < ARRAY_SIZE(sld_options); i++) {
|
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if (match_option(arg, ret, sld_options[i].option)) {
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state = sld_options[i].state;
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break;
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}
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}
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}
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switch (state) {
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case sld_off:
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pr_info("disabled\n");
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return;
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case sld_warn:
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pr_info("warning about user-space split_locks\n");
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break;
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case sld_fatal:
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pr_info("sending SIGBUS on user-space split_locks\n");
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break;
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}
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rdmsrl(MSR_TEST_CTRL, msr_test_ctrl_cache);
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if (!split_lock_verify_msr(true)) {
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pr_info("MSR access failed: Disabled\n");
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return;
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}
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|
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sld_state = state;
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setup_force_cpu_cap(X86_FEATURE_SPLIT_LOCK_DETECT);
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}
|
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|
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/*
|
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* MSR_TEST_CTRL is per core, but we treat it like a per CPU MSR. Locking
|
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* is not implemented as one thread could undo the setting of the other
|
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* thread immediately after dropping the lock anyway.
|
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*/
|
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static void sld_update_msr(bool on)
|
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{
|
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u64 test_ctrl_val = msr_test_ctrl_cache;
|
||||
|
||||
if (on)
|
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test_ctrl_val |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
|
||||
|
||||
wrmsrl(MSR_TEST_CTRL, test_ctrl_val);
|
||||
}
|
||||
|
||||
static void split_lock_init(void)
|
||||
{
|
||||
split_lock_verify_msr(sld_state != sld_off);
|
||||
}
|
||||
|
||||
bool handle_user_split_lock(struct pt_regs *regs, long error_code)
|
||||
{
|
||||
if ((regs->flags & X86_EFLAGS_AC) || sld_state == sld_fatal)
|
||||
return false;
|
||||
|
||||
pr_warn_ratelimited("#AC: %s/%d took a split_lock trap at address: 0x%lx\n",
|
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current->comm, current->pid, regs->ip);
|
||||
|
||||
/*
|
||||
* Disable the split lock detection for this task so it can make
|
||||
* progress and set TIF_SLD so the detection is re-enabled via
|
||||
* switch_to_sld() when the task is scheduled out.
|
||||
*/
|
||||
sld_update_msr(false);
|
||||
set_tsk_thread_flag(current, TIF_SLD);
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is called only when switching between tasks with
|
||||
* different split-lock detection modes. It sets the MSR for the
|
||||
* mode of the new task. This is right most of the time, but since
|
||||
* the MSR is shared by hyperthreads on a physical core there can
|
||||
* be glitches when the two threads need different modes.
|
||||
*/
|
||||
void switch_to_sld(unsigned long tifn)
|
||||
{
|
||||
sld_update_msr(!(tifn & _TIF_SLD));
|
||||
}
|
||||
|
||||
#define SPLIT_LOCK_CPU(model) {X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY}
|
||||
|
||||
/*
|
||||
* The following processors have the split lock detection feature. But
|
||||
* since they don't have the IA32_CORE_CAPABILITIES MSR, the feature cannot
|
||||
* be enumerated. Enable it by family and model matching on these
|
||||
* processors.
|
||||
*/
|
||||
static const struct x86_cpu_id split_lock_cpu_ids[] __initconst = {
|
||||
SPLIT_LOCK_CPU(INTEL_FAM6_ICELAKE_X),
|
||||
SPLIT_LOCK_CPU(INTEL_FAM6_ICELAKE_L),
|
||||
{}
|
||||
};
|
||||
|
||||
void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c)
|
||||
{
|
||||
u64 ia32_core_caps = 0;
|
||||
|
||||
if (c->x86_vendor != X86_VENDOR_INTEL)
|
||||
return;
|
||||
if (cpu_has(c, X86_FEATURE_CORE_CAPABILITIES)) {
|
||||
/* Enumerate features reported in IA32_CORE_CAPABILITIES MSR. */
|
||||
rdmsrl(MSR_IA32_CORE_CAPS, ia32_core_caps);
|
||||
} else if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
|
||||
/* Enumerate split lock detection by family and model. */
|
||||
if (x86_match_cpu(split_lock_cpu_ids))
|
||||
ia32_core_caps |= MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT;
|
||||
}
|
||||
|
||||
if (ia32_core_caps & MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT)
|
||||
split_lock_setup();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -649,6 +649,9 @@ void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p)
|
|||
/* Enforce MSR update to ensure consistent state */
|
||||
__speculation_ctrl_update(~tifn, tifn);
|
||||
}
|
||||
|
||||
if ((tifp ^ tifn) & _TIF_SLD)
|
||||
switch_to_sld(tifn);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -46,6 +46,7 @@
|
|||
#include <asm/traps.h>
|
||||
#include <asm/desc.h>
|
||||
#include <asm/fpu/internal.h>
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/cpu_entry_area.h>
|
||||
#include <asm/mce.h>
|
||||
#include <asm/fixmap.h>
|
||||
|
|
@ -242,7 +243,6 @@ do_trap(int trapnr, int signr, char *str, struct pt_regs *regs,
|
|||
{
|
||||
struct task_struct *tsk = current;
|
||||
|
||||
|
||||
if (!do_trap_no_signal(tsk, trapnr, str, regs, error_code))
|
||||
return;
|
||||
|
||||
|
|
@ -288,9 +288,29 @@ DO_ERROR(X86_TRAP_OLD_MF, SIGFPE, 0, NULL, "coprocessor segment overru
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DO_ERROR(X86_TRAP_TS, SIGSEGV, 0, NULL, "invalid TSS", invalid_TSS)
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DO_ERROR(X86_TRAP_NP, SIGBUS, 0, NULL, "segment not present", segment_not_present)
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DO_ERROR(X86_TRAP_SS, SIGBUS, 0, NULL, "stack segment", stack_segment)
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DO_ERROR(X86_TRAP_AC, SIGBUS, BUS_ADRALN, NULL, "alignment check", alignment_check)
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#undef IP
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dotraplinkage void do_alignment_check(struct pt_regs *regs, long error_code)
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{
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char *str = "alignment check";
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RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU");
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if (notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_AC, SIGBUS) == NOTIFY_STOP)
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return;
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if (!user_mode(regs))
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die("Split lock detected\n", regs, error_code);
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local_irq_enable();
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if (handle_user_split_lock(regs, error_code))
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return;
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do_trap(X86_TRAP_AC, SIGBUS, "alignment check", regs,
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error_code, BUS_ADRALN, NULL);
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}
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#ifdef CONFIG_VMAP_STACK
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__visible void __noreturn handle_stack_overflow(const char *message,
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struct pt_regs *regs,
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|
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