ARC: retire MMUv1 and MMUv2 support
There's no known/active customer using them with latest kernels anyways. Removal helps cleanup code and remove the hack for MMU_VER to MMU_V[3-4] conversion Signed-off-by: Vineet Gupta <vgupta@kernel.org>
This commit is contained in:
Vineet Gupta
Родитель
767a697e75
Коммит
288ff7de62
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@ -265,32 +265,17 @@ config ARC_DCCM_BASE
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choice
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prompt "MMU Version"
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default ARC_MMU_V3 if ARC_CPU_770
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default ARC_MMU_V4 if ARC_CPU_HS
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if ISA_ARCOMPACT
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config ARC_MMU_V1
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bool "MMU v1"
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help
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Orig ARC700 MMU
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config ARC_MMU_V2
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bool "MMU v2"
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help
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Fixed the deficiency of v1 - possible thrashing in memcpy scenario
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when 2 D-TLB and 1 I-TLB entries index into same 2way set.
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default ARC_MMU_V3 if ISA_ARCOMPACT
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default ARC_MMU_V4 if ISA_ARCV2
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config ARC_MMU_V3
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bool "MMU v3"
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depends on ARC_CPU_770
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depends on ISA_ARCOMPACT
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help
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Introduced with ARC700 4.10: New Features
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Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
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Shared Address Spaces (SASID)
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endif
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config ARC_MMU_V4
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bool "MMU v4"
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depends on ISA_ARCV2
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@ -309,7 +294,6 @@ config ARC_PAGE_SIZE_8K
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config ARC_PAGE_SIZE_16K
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bool "16KB"
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depends on ARC_MMU_V3 || ARC_MMU_V4
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config ARC_PAGE_SIZE_4K
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bool "4KB"
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@ -10,19 +10,10 @@
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#include <linux/threads.h> /* NR_CPUS */
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#endif
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#if defined(CONFIG_ARC_MMU_V1)
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#define CONFIG_ARC_MMU_VER 1
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#elif defined(CONFIG_ARC_MMU_V2)
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#define CONFIG_ARC_MMU_VER 2
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#elif defined(CONFIG_ARC_MMU_V3)
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#define CONFIG_ARC_MMU_VER 3
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#elif defined(CONFIG_ARC_MMU_V4)
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#define CONFIG_ARC_MMU_VER 4
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#endif
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/* MMU Management regs */
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#define ARC_REG_MMU_BCR 0x06f
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#if (CONFIG_ARC_MMU_VER < 4)
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#ifdef CONFIG_ARC_MMU_V3
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#define ARC_REG_TLBPD0 0x405
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#define ARC_REG_TLBPD1 0x406
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#define ARC_REG_TLBPD1HI 0 /* Dummy: allows code sharing with ARC700 */
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@ -52,7 +43,7 @@
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/* Error code if probe fails */
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#define TLB_LKUP_ERR 0x80000000
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#if (CONFIG_ARC_MMU_VER < 4)
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#ifdef CONFIG_ARC_MMU_V3
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#define TLB_DUP_ERR (TLB_LKUP_ERR | 0x00000001)
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#else
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#define TLB_DUP_ERR (TLB_LKUP_ERR | 0x40000000)
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@ -63,15 +54,10 @@
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#define TLBRead 0x2
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#define TLBGetIndex 0x3
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#define TLBProbe 0x4
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#if (CONFIG_ARC_MMU_VER >= 2)
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#define TLBWriteNI 0x5 /* write JTLB without inv uTLBs */
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#define TLBIVUTLB 0x6 /* explicitly inv uTLBs */
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#else
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#define TLBWriteNI TLBWrite /* Not present in hardware, fallback */
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#endif
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#if (CONFIG_ARC_MMU_VER >= 4)
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#ifdef CONFIG_ARC_MMU_V4
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#define TLBInsertEntry 0x7
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#define TLBDeleteEntry 0x8
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#endif
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@ -35,7 +35,7 @@
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#include <linux/bits.h>
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#include <asm-generic/pgtable-nopmd.h>
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#include <asm/page.h>
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#include <asm/mmu.h> /* to propagate CONFIG_ARC_MMU_VER <n> */
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#include <asm/mmu.h>
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/**************************************************************************
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* Page Table Flags
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@ -51,20 +51,6 @@
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* (saves some bit shift ops in TLB Miss hdlrs)
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*/
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#if (CONFIG_ARC_MMU_VER <= 2)
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#define _PAGE_ACCESSED (1<<1) /* Page is accessed (S) */
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#define _PAGE_CACHEABLE (1<<2) /* Page is cached (H) */
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#define _PAGE_EXECUTE (1<<3) /* Page has user execute perm (H) */
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#define _PAGE_WRITE (1<<4) /* Page has user write perm (H) */
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#define _PAGE_READ (1<<5) /* Page has user read perm (H) */
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#define _PAGE_DIRTY (1<<6) /* Page modified (dirty) (S) */
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#define _PAGE_SPECIAL (1<<7)
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#define _PAGE_GLOBAL (1<<8) /* Page is global (H) */
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#define _PAGE_PRESENT (1<<10) /* TLB entry is valid (H) */
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#else /* MMU v3 onwards */
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#define _PAGE_CACHEABLE (1<<0) /* Page is cached (H) */
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#define _PAGE_EXECUTE (1<<1) /* Page has user execute perm (H) */
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#define _PAGE_WRITE (1<<2) /* Page has user write perm (H) */
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@ -73,23 +59,15 @@
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#define _PAGE_DIRTY (1<<5) /* Page modified (dirty) (S) */
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#define _PAGE_SPECIAL (1<<6)
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#if (CONFIG_ARC_MMU_VER >= 4)
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#define _PAGE_WTHRU (1<<7) /* Page cache mode write-thru (H) */
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#endif
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#define _PAGE_GLOBAL (1<<8) /* Page is global (H) */
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#define _PAGE_PRESENT (1<<9) /* TLB entry is valid (H) */
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#if (CONFIG_ARC_MMU_VER >= 4)
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#ifdef CONFIG_ARC_MMU_V4
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#define _PAGE_HW_SZ (1<<10) /* Page Size indicator (H): 0 normal, 1 super */
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#endif
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#define _PAGE_SHARED_CODE (1<<11) /* Shared Code page with cmn vaddr
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usable for shared TLB entries (H) */
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#define _PAGE_UNUSED_BIT (1<<12)
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#endif
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/* vmalloc permissions */
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#define _K_PAGE_PERMS (_PAGE_EXECUTE | _PAGE_WRITE | _PAGE_READ | \
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_PAGE_GLOBAL | _PAGE_PRESENT)
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@ -1,101 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*/
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#ifndef __ASM_TLB_MMU_V1_H__
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#define __ASM_TLB_MMU_V1_H__
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#include <asm/mmu.h>
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#if defined(__ASSEMBLY__) && (CONFIG_ARC_MMU_VER == 1)
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.macro TLB_WRITE_HEURISTICS
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#define JH_HACK1
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#undef JH_HACK2
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#undef JH_HACK3
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#ifdef JH_HACK3
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; Calculate set index for 2-way MMU
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; -avoiding use of GetIndex from MMU
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; and its unpleasant LFSR pseudo-random sequence
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;
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; r1 = TLBPD0 from TLB_RELOAD above
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;
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; -- jh_ex_way_set not cleared on startup
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; didn't want to change setup.c
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; hence extra instruction to clean
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;
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; -- should be in cache since in same line
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; as r0/r1 saves above
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;
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ld r0,[jh_ex_way_sel] ; victim pointer
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and r0,r0,1 ; clean
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xor.f r0,r0,1 ; flip
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st r0,[jh_ex_way_sel] ; store back
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asr r0,r1,12 ; get set # <<1, note bit 12=R=0
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or.nz r0,r0,1 ; set way bit
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and r0,r0,0xff ; clean
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sr r0,[ARC_REG_TLBINDEX]
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#endif
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#ifdef JH_HACK2
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; JH hack #2
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; Faster than hack #1 in non-thrash case, but hard-coded for 2-way MMU
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; Slower in thrash case (where it matters) because more code is executed
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; Inefficient due to two-register paradigm of this miss handler
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;
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/* r1 = data TLBPD0 at this point */
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lr r0,[eret] /* instruction address */
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xor r0,r0,r1 /* compare set # */
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and.f r0,r0,0x000fe000 /* 2-way MMU mask */
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bne 88f /* not in same set - no need to probe */
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lr r0,[eret] /* instruction address */
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and r0,r0,PAGE_MASK /* VPN of instruction address */
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; lr r1,[ARC_REG_TLBPD0] /* Data VPN+ASID - already in r1 from TLB_RELOAD*/
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and r1,r1,0xff /* Data ASID */
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or r0,r0,r1 /* Instruction address + Data ASID */
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lr r1,[ARC_REG_TLBPD0] /* save TLBPD0 containing data TLB*/
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sr r0,[ARC_REG_TLBPD0] /* write instruction address to TLBPD0 */
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sr TLBProbe, [ARC_REG_TLBCOMMAND] /* Look for instruction */
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lr r0,[ARC_REG_TLBINDEX] /* r0 = index where instruction is, if at all */
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sr r1,[ARC_REG_TLBPD0] /* restore TLBPD0 */
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xor r0,r0,1 /* flip bottom bit of data index */
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b.d 89f
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sr r0,[ARC_REG_TLBINDEX] /* and put it back */
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88:
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sr TLBGetIndex, [ARC_REG_TLBCOMMAND]
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89:
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#endif
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#ifdef JH_HACK1
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;
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; Always checks whether instruction will be kicked out by dtlb miss
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;
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mov_s r3, r1 ; save PD0 prepared by TLB_RELOAD in r3
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lr r0,[eret] /* instruction address */
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and r0,r0,PAGE_MASK /* VPN of instruction address */
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bmsk r1,r3,7 /* Data ASID, bits 7-0 */
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or_s r0,r0,r1 /* Instruction address + Data ASID */
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sr r0,[ARC_REG_TLBPD0] /* write instruction address to TLBPD0 */
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sr TLBProbe, [ARC_REG_TLBCOMMAND] /* Look for instruction */
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lr r0,[ARC_REG_TLBINDEX] /* r0 = index where instruction is, if at all */
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sr r3,[ARC_REG_TLBPD0] /* restore TLBPD0 */
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sr TLBGetIndex, [ARC_REG_TLBCOMMAND]
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lr r1,[ARC_REG_TLBINDEX] /* r1 = index where MMU wants to put data */
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cmp r0,r1 /* if no match on indices, go around */
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xor.eq r1,r1,1 /* flip bottom bit of data index */
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sr r1,[ARC_REG_TLBINDEX] /* and put it back */
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#endif
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.endm
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#endif
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#endif
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@ -205,93 +205,24 @@ slc_chk:
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#define OP_INV_IC 0x4
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/*
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* I-Cache Aliasing in ARC700 VIPT caches (MMU v1-v3)
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* Cache Flush programming model
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*
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* ARC VIPT I-cache uses vaddr to index into cache and paddr to match the tag.
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* The orig Cache Management Module "CDU" only required paddr to invalidate a
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* certain line since it sufficed as index in Non-Aliasing VIPT cache-geometry.
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* Infact for distinct V1,V2,P: all of {V1-P},{V2-P},{P-P} would end up fetching
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* the exact same line.
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* ARC700 MMUv3 I$ and D$ are both VIPT and can potentially alias.
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* Programming model requires both paddr and vaddr irrespecive of aliasing
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* considerations:
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* - vaddr in {I,D}C_IV?L
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* - paddr in {I,D}C_PTAG
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*
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* However for larger Caches (way-size > page-size) - i.e. in Aliasing config,
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* paddr alone could not be used to correctly index the cache.
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* In HS38x (MMUv4), D$ is PIPT, I$ is VIPT and can still alias.
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* Programming model is different for aliasing vs. non-aliasing I$
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* - D$ / Non-aliasing I$: only paddr in {I,D}C_IV?L
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* - Aliasing I$: same as ARC700 above (so MMUv3 routine used for MMUv4 I$)
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*
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* ------------------
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* MMU v1/v2 (Fixed Page Size 8k)
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* ------------------
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* The solution was to provide CDU with these additonal vaddr bits. These
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* would be bits [x:13], x would depend on cache-geometry, 13 comes from
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* standard page size of 8k.
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* H/w folks chose [17:13] to be a future safe range, and moreso these 5 bits
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* of vaddr could easily be "stuffed" in the paddr as bits [4:0] since the
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* orig 5 bits of paddr were anyways ignored by CDU line ops, as they
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* represent the offset within cache-line. The adv of using this "clumsy"
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* interface for additional info was no new reg was needed in CDU programming
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* model.
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*
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* 17:13 represented the max num of bits passable, actual bits needed were
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* fewer, based on the num-of-aliases possible.
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* -for 2 alias possibility, only bit 13 needed (32K cache)
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* -for 4 alias possibility, bits 14:13 needed (64K cache)
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*
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* ------------------
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* MMU v3
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* ------------------
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* This ver of MMU supports variable page sizes (1k-16k): although Linux will
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* only support 8k (default), 16k and 4k.
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* However from hardware perspective, smaller page sizes aggravate aliasing
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* meaning more vaddr bits needed to disambiguate the cache-line-op ;
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* the existing scheme of piggybacking won't work for certain configurations.
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* Two new registers IC_PTAG and DC_PTAG inttoduced.
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* "tag" bits are provided in PTAG, index bits in existing IVIL/IVDL/FLDL regs
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* - If PAE40 is enabled, independent of aliasing considerations, the higher
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* bits needs to be written into PTAG_HI
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*/
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static inline
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void __cache_line_loop_v2(phys_addr_t paddr, unsigned long vaddr,
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unsigned long sz, const int op, const int full_page)
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{
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unsigned int aux_cmd;
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int num_lines;
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if (op == OP_INV_IC) {
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aux_cmd = ARC_REG_IC_IVIL;
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} else {
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/* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
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aux_cmd = op & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
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}
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/* Ensure we properly floor/ceil the non-line aligned/sized requests
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* and have @paddr - aligned to cache line and integral @num_lines.
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* This however can be avoided for page sized since:
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* -@paddr will be cache-line aligned already (being page aligned)
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* -@sz will be integral multiple of line size (being page sized).
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*/
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if (!full_page) {
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sz += paddr & ~CACHE_LINE_MASK;
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paddr &= CACHE_LINE_MASK;
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vaddr &= CACHE_LINE_MASK;
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}
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num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);
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/* MMUv2 and before: paddr contains stuffed vaddrs bits */
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paddr |= (vaddr >> PAGE_SHIFT) & 0x1F;
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while (num_lines-- > 0) {
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write_aux_reg(aux_cmd, paddr);
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paddr += L1_CACHE_BYTES;
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}
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}
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/*
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* For ARC700 MMUv3 I-cache and D-cache flushes
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* - ARC700 programming model requires paddr and vaddr be passed in seperate
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* AUX registers (*_IV*L and *_PTAG respectively) irrespective of whether the
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* caches actually alias or not.
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* - For HS38, only the aliasing I-cache configuration uses the PTAG reg
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* (non aliasing I-cache version doesn't; while D-cache can't possibly alias)
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*/
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static inline
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void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr,
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unsigned long sz, const int op, const int full_page)
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{
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@ -350,17 +281,6 @@ void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr,
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#ifndef USE_RGN_FLSH
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/*
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* In HS38x (MMU v4), I-cache is VIPT (can alias), D-cache is PIPT
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* Here's how cache ops are implemented
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*
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* - D-cache: only paddr needed (in DC_IVDL/DC_FLDL)
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* - I-cache Non Aliasing: Despite VIPT, only paddr needed (in IC_IVIL)
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* - I-cache Aliasing: Both vaddr and paddr needed (in IC_IVIL, IC_PTAG
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* respectively, similar to MMU v3 programming model, hence
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* __cache_line_loop_v3() is used)
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*
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* If PAE40 is enabled, independent of aliasing considerations, the higher bits
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* needs to be written into PTAG_HI
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*/
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static inline
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void __cache_line_loop_v4(phys_addr_t paddr, unsigned long vaddr,
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@ -460,11 +380,9 @@ void __cache_line_loop_v4(phys_addr_t paddr, unsigned long vaddr,
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#endif
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#if (CONFIG_ARC_MMU_VER < 3)
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#define __cache_line_loop __cache_line_loop_v2
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#elif (CONFIG_ARC_MMU_VER == 3)
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#ifdef CONFIG_ARC_MMU_V3
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#define __cache_line_loop __cache_line_loop_v3
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#elif (CONFIG_ARC_MMU_VER > 3)
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#else
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#define __cache_line_loop __cache_line_loop_v4
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#endif
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@ -1,51 +1,9 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* TLB Management (flush/create/diagnostics) for ARC700
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* TLB Management (flush/create/diagnostics) for MMUv3 and MMUv4
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*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* vineetg: Aug 2011
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* -Reintroduce duplicate PD fixup - some customer chips still have the issue
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*
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* vineetg: May 2011
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* -No need to flush_cache_page( ) for each call to update_mmu_cache()
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* some of the LMBench tests improved amazingly
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* = page-fault thrice as fast (75 usec to 28 usec)
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* = mmap twice as fast (9.6 msec to 4.6 msec),
|
||||
* = fork (5.3 msec to 3.7 msec)
|
||||
*
|
||||
* vineetg: April 2011 :
|
||||
* -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
|
||||
* helps avoid a shift when preparing PD0 from PTE
|
||||
*
|
||||
* vineetg: April 2011 : Preparing for MMU V3
|
||||
* -MMU v2/v3 BCRs decoded differently
|
||||
* -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512
|
||||
* -tlb_entry_erase( ) can be void
|
||||
* -local_flush_tlb_range( ):
|
||||
* = need not "ceil" @end
|
||||
* = walks MMU only if range spans < 32 entries, as opposed to 256
|
||||
*
|
||||
* Vineetg: Sept 10th 2008
|
||||
* -Changes related to MMU v2 (Rel 4.8)
|
||||
*
|
||||
* Vineetg: Aug 29th 2008
|
||||
* -In TLB Flush operations (Metal Fix MMU) there is a explicit command to
|
||||
* flush Micro-TLBS. If TLB Index Reg is invalid prior to TLBIVUTLB cmd,
|
||||
* it fails. Thus need to load it with ANY valid value before invoking
|
||||
* TLBIVUTLB cmd
|
||||
*
|
||||
* Vineetg: Aug 21th 2008:
|
||||
* -Reduced the duration of IRQ lockouts in TLB Flush routines
|
||||
* -Multiple copies of TLB erase code separated into a "single" function
|
||||
* -In TLB Flush routines, interrupt disabling moved UP to retrieve ASID
|
||||
* in interrupt-safe region.
|
||||
*
|
||||
* Vineetg: April 23rd Bug #93131
|
||||
* Problem: tlb_flush_kernel_range() doesn't do anything if the range to
|
||||
* flush is more than the size of TLB itself.
|
||||
*
|
||||
* Rahul Trivedi : Codito Technologies 2004
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
|
|
@ -57,47 +15,6 @@
|
|||
#include <asm/mmu_context.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
/* Need for ARC MMU v2
|
||||
*
|
||||
* ARC700 MMU-v1 had a Joint-TLB for Code and Data and is 2 way set-assoc.
|
||||
* For a memcpy operation with 3 players (src/dst/code) such that all 3 pages
|
||||
* map into same set, there would be contention for the 2 ways causing severe
|
||||
* Thrashing.
|
||||
*
|
||||
* Although J-TLB is 2 way set assoc, ARC700 caches J-TLB into uTLBS which has
|
||||
* much higher associativity. u-D-TLB is 8 ways, u-I-TLB is 4 ways.
|
||||
* Given this, the thrashing problem should never happen because once the 3
|
||||
* J-TLB entries are created (even though 3rd will knock out one of the prev
|
||||
* two), the u-D-TLB and u-I-TLB will have what is required to accomplish memcpy
|
||||
*
|
||||
* Yet we still see the Thrashing because a J-TLB Write cause flush of u-TLBs.
|
||||
* This is a simple design for keeping them in sync. So what do we do?
|
||||
* The solution which James came up was pretty neat. It utilised the assoc
|
||||
* of uTLBs by not invalidating always but only when absolutely necessary.
|
||||
*
|
||||
* - Existing TLB commands work as before
|
||||
* - New command (TLBWriteNI) for TLB write without clearing uTLBs
|
||||
* - New command (TLBIVUTLB) to invalidate uTLBs.
|
||||
*
|
||||
* The uTLBs need only be invalidated when pages are being removed from the
|
||||
* OS page table. If a 'victim' TLB entry is being overwritten in the main TLB
|
||||
* as a result of a miss, the removed entry is still allowed to exist in the
|
||||
* uTLBs as it is still valid and present in the OS page table. This allows the
|
||||
* full associativity of the uTLBs to hide the limited associativity of the main
|
||||
* TLB.
|
||||
*
|
||||
* During a miss handler, the new "TLBWriteNI" command is used to load
|
||||
* entries without clearing the uTLBs.
|
||||
*
|
||||
* When the OS page table is updated, TLB entries that may be associated with a
|
||||
* removed page are removed (flushed) from the TLB using TLBWrite. In this
|
||||
* circumstance, the uTLBs must also be cleared. This is done by using the
|
||||
* existing TLBWrite command. An explicit IVUTLB is also required for those
|
||||
* corner cases when TLBWrite was not executed at all because the corresp
|
||||
* J-TLB entry got evicted/replaced.
|
||||
*/
|
||||
|
||||
|
||||
/* A copy of the ASID from the PID reg is kept in asid_cache */
|
||||
DEFINE_PER_CPU(unsigned int, asid_cache) = MM_CTXT_FIRST_CYCLE;
|
||||
|
||||
|
|
@ -120,32 +37,10 @@ static inline void __tlb_entry_erase(void)
|
|||
|
||||
static void utlb_invalidate(void)
|
||||
{
|
||||
#if (CONFIG_ARC_MMU_VER >= 2)
|
||||
|
||||
#if (CONFIG_ARC_MMU_VER == 2)
|
||||
/* MMU v2 introduced the uTLB Flush command.
|
||||
* There was however an obscure hardware bug, where uTLB flush would
|
||||
* fail when a prior probe for J-TLB (both totally unrelated) would
|
||||
* return lkup err - because the entry didn't exist in MMU.
|
||||
* The Workaround was to set Index reg with some valid value, prior to
|
||||
* flush. This was fixed in MMU v3
|
||||
*/
|
||||
unsigned int idx;
|
||||
|
||||
/* make sure INDEX Reg is valid */
|
||||
idx = read_aux_reg(ARC_REG_TLBINDEX);
|
||||
|
||||
/* If not write some dummy val */
|
||||
if (unlikely(idx & TLB_LKUP_ERR))
|
||||
write_aux_reg(ARC_REG_TLBINDEX, 0xa);
|
||||
#endif
|
||||
|
||||
write_aux_reg(ARC_REG_TLBCOMMAND, TLBIVUTLB);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
#if (CONFIG_ARC_MMU_VER < 4)
|
||||
#ifdef CONFIG_ARC_MMU_V3
|
||||
|
||||
static inline unsigned int tlb_entry_lkup(unsigned long vaddr_n_asid)
|
||||
{
|
||||
|
|
@ -206,7 +101,7 @@ static void tlb_entry_insert(unsigned int pd0, pte_t pd1)
|
|||
write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
|
||||
}
|
||||
|
||||
#else /* CONFIG_ARC_MMU_VER >= 4) */
|
||||
#else /* MMUv4 */
|
||||
|
||||
static void tlb_entry_erase(unsigned int vaddr_n_asid)
|
||||
{
|
||||
|
|
@ -706,14 +601,6 @@ void read_decode_mmu_bcr(void)
|
|||
{
|
||||
struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
|
||||
unsigned int tmp;
|
||||
struct bcr_mmu_1_2 {
|
||||
#ifdef CONFIG_CPU_BIG_ENDIAN
|
||||
unsigned int ver:8, ways:4, sets:4, u_itlb:8, u_dtlb:8;
|
||||
#else
|
||||
unsigned int u_dtlb:8, u_itlb:8, sets:4, ways:4, ver:8;
|
||||
#endif
|
||||
} *mmu2;
|
||||
|
||||
struct bcr_mmu_3 {
|
||||
#ifdef CONFIG_CPU_BIG_ENDIAN
|
||||
unsigned int ver:8, ways:4, sets:4, res:3, sasid:1, pg_sz:4,
|
||||
|
|
@ -738,23 +625,14 @@ void read_decode_mmu_bcr(void)
|
|||
tmp = read_aux_reg(ARC_REG_MMU_BCR);
|
||||
mmu->ver = (tmp >> 24);
|
||||
|
||||
if (is_isa_arcompact()) {
|
||||
if (mmu->ver <= 2) {
|
||||
mmu2 = (struct bcr_mmu_1_2 *)&tmp;
|
||||
mmu->pg_sz_k = TO_KB(0x2000);
|
||||
mmu->sets = 1 << mmu2->sets;
|
||||
mmu->ways = 1 << mmu2->ways;
|
||||
mmu->u_dtlb = mmu2->u_dtlb;
|
||||
mmu->u_itlb = mmu2->u_itlb;
|
||||
} else {
|
||||
mmu3 = (struct bcr_mmu_3 *)&tmp;
|
||||
mmu->pg_sz_k = 1 << (mmu3->pg_sz - 1);
|
||||
mmu->sets = 1 << mmu3->sets;
|
||||
mmu->ways = 1 << mmu3->ways;
|
||||
mmu->u_dtlb = mmu3->u_dtlb;
|
||||
mmu->u_itlb = mmu3->u_itlb;
|
||||
mmu->sasid = mmu3->sasid;
|
||||
}
|
||||
if (is_isa_arcompact() && mmu->ver == 3) {
|
||||
mmu3 = (struct bcr_mmu_3 *)&tmp;
|
||||
mmu->pg_sz_k = 1 << (mmu3->pg_sz - 1);
|
||||
mmu->sets = 1 << mmu3->sets;
|
||||
mmu->ways = 1 << mmu3->ways;
|
||||
mmu->u_dtlb = mmu3->u_dtlb;
|
||||
mmu->u_itlb = mmu3->u_itlb;
|
||||
mmu->sasid = mmu3->sasid;
|
||||
} else {
|
||||
mmu4 = (struct bcr_mmu_4 *)&tmp;
|
||||
mmu->pg_sz_k = 1 << (mmu4->sz0 - 1);
|
||||
|
|
@ -815,22 +693,17 @@ void arc_mmu_init(void)
|
|||
|
||||
/*
|
||||
* Ensure that MMU features assumed by kernel exist in hardware.
|
||||
* For older ARC700 cpus, it has to be exact match, since the MMU
|
||||
* revisions were not backwards compatible (MMUv3 TLB layout changed
|
||||
* so even if kernel for v2 didn't use any new cmds of v3, it would
|
||||
* still not work.
|
||||
* For HS cpus, MMUv4 was baseline and v5 is backwards compatible
|
||||
* (will run older software).
|
||||
* - For older ARC700 cpus, only v3 supported
|
||||
* - For HS cpus, v4 was baseline and v5 is backwards compatible
|
||||
* (will run older software).
|
||||
*/
|
||||
if (is_isa_arcompact() && mmu->ver == CONFIG_ARC_MMU_VER)
|
||||
if (is_isa_arcompact() && mmu->ver == 3)
|
||||
compat = 1;
|
||||
else if (is_isa_arcv2() && mmu->ver >= CONFIG_ARC_MMU_VER)
|
||||
else if (is_isa_arcv2() && mmu->ver >= 4)
|
||||
compat = 1;
|
||||
|
||||
if (!compat) {
|
||||
panic("MMU ver %d doesn't match kernel built for %d...\n",
|
||||
mmu->ver, CONFIG_ARC_MMU_VER);
|
||||
}
|
||||
if (!compat)
|
||||
panic("MMU ver %d doesn't match kernel built for\n", mmu->ver);
|
||||
|
||||
if (mmu->pg_sz_k != TO_KB(PAGE_SIZE))
|
||||
panic("MMU pg size != PAGE_SIZE (%luk)\n", TO_KB(PAGE_SIZE));
|
||||
|
|
|
|||
|
|
@ -39,7 +39,6 @@
|
|||
#include <asm/arcregs.h>
|
||||
#include <asm/cache.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/tlb-mmu1.h>
|
||||
|
||||
#ifdef CONFIG_ISA_ARCOMPACT
|
||||
;-----------------------------------------------------------------
|
||||
|
|
@ -279,7 +278,7 @@ ex_saved_reg1:
|
|||
; Commit the TLB entry into MMU
|
||||
|
||||
.macro COMMIT_ENTRY_TO_MMU
|
||||
#if (CONFIG_ARC_MMU_VER < 4)
|
||||
#ifdef CONFIG_ARC_MMU_V3
|
||||
|
||||
/* Get free TLB slot: Set = computed from vaddr, way = random */
|
||||
sr TLBGetIndex, [ARC_REG_TLBCOMMAND]
|
||||
|
|
@ -375,13 +374,6 @@ ENTRY(EV_TLBMissD)
|
|||
|
||||
CONV_PTE_TO_TLB
|
||||
|
||||
#if (CONFIG_ARC_MMU_VER == 1)
|
||||
; MMU with 2 way set assoc J-TLB, needs some help in pathetic case of
|
||||
; memcpy where 3 parties contend for 2 ways, ensuing a livelock.
|
||||
; But only for old MMU or one with Metal Fix
|
||||
TLB_WRITE_HEURISTICS
|
||||
#endif
|
||||
|
||||
COMMIT_ENTRY_TO_MMU
|
||||
TLBMISS_RESTORE_REGS
|
||||
EV_TLBMissD_fast_ret: ; additional label for VDK OS-kit instrumentation
|
||||
|
|
|
|||
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