KVM/VMX: Emulate MSR_IA32_ARCH_CAPABILITIES
Intel processors use MSR_IA32_ARCH_CAPABILITIES MSR to indicate RDCL_NO (bit 0) and IBRS_ALL (bit 1). This is a read-only MSR. By default the contents will come directly from the hardware, but user-space can still override it. [dwmw2: The bit in kvm_cpuid_7_0_edx_x86_features can be unconditional] Signed-off-by: KarimAllah Ahmed <karahmed@amazon.de> Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Darren Kenny <darren.kenny@oracle.com> Reviewed-by: Jim Mattson <jmattson@google.com> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: Andrea Arcangeli <aarcange@redhat.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Jun Nakajima <jun.nakajima@intel.com> Cc: kvm@vger.kernel.org Cc: Dave Hansen <dave.hansen@intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Andy Lutomirski <luto@kernel.org> Cc: Asit Mallick <asit.k.mallick@intel.com> Cc: Arjan Van De Ven <arjan.van.de.ven@intel.com> Cc: Greg KH <gregkh@linuxfoundation.org> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Tim Chen <tim.c.chen@linux.intel.com> Cc: Ashok Raj <ashok.raj@intel.com> Link: https://lkml.kernel.org/r/1517522386-18410-4-git-send-email-karahmed@amazon.de
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@ -394,7 +394,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
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/* cpuid 7.0.edx*/
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const u32 kvm_cpuid_7_0_edx_x86_features =
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F(AVX512_4VNNIW) | F(AVX512_4FMAPS);
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F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(ARCH_CAPABILITIES);
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/* all calls to cpuid_count() should be made on the same cpu */
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get_cpu();
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@ -594,6 +594,8 @@ struct vcpu_vmx {
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u64 msr_guest_kernel_gs_base;
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#endif
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u64 arch_capabilities;
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u32 vm_entry_controls_shadow;
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u32 vm_exit_controls_shadow;
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u32 secondary_exec_control;
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@ -3260,6 +3262,12 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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case MSR_IA32_TSC:
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msr_info->data = guest_read_tsc(vcpu);
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break;
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case MSR_IA32_ARCH_CAPABILITIES:
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if (!msr_info->host_initiated &&
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!guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
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return 1;
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msr_info->data = to_vmx(vcpu)->arch_capabilities;
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break;
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case MSR_IA32_SYSENTER_CS:
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msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
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break;
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@ -3395,6 +3403,11 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
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MSR_TYPE_W);
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break;
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case MSR_IA32_ARCH_CAPABILITIES:
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if (!msr_info->host_initiated)
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return 1;
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vmx->arch_capabilities = data;
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break;
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case MSR_IA32_CR_PAT:
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if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
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if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
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@ -5657,6 +5670,8 @@ static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
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++vmx->nmsrs;
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}
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if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
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rdmsrl(MSR_IA32_ARCH_CAPABILITIES, vmx->arch_capabilities);
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vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
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@ -1009,6 +1009,7 @@ static u32 msrs_to_save[] = {
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#endif
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MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
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MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
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MSR_IA32_ARCH_CAPABILITIES
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};
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static unsigned num_msrs_to_save;
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