edac: AMD8131 driver source file
Introduce AMD8131 EDAC driver source file, which makes use of error detections on the PCI-X Bridge Controllers on the AMD8131 HyperTransport PCI-X Tunnel. Signed-off-by: Harry Ciao <qingtao.cao@windriver.com> Cc: Doug Thompson <norsk5@yahoo.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Harry Ciao
Linus Torvalds
Родитель
a35a281880
Коммит
28d16272b1
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/*
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* amd8131_edac.c, AMD8131 hypertransport chip EDAC kernel module
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*
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* Copyright (c) 2008 Wind River Systems, Inc.
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*
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* Authors: Cao Qingtao <qingtao.cao@windriver.com>
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* Benjamin Walsh <benjamin.walsh@windriver.com>
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* Hu Yongqi <yongqi.hu@windriver.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/bitops.h>
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#include <linux/edac.h>
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#include <linux/pci_ids.h>
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#include "edac_core.h"
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#include "edac_module.h"
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#include "amd8131_edac.h"
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#define AMD8131_EDAC_REVISION " Ver: 1.0.0 " __DATE__
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#define AMD8131_EDAC_MOD_STR "amd8131_edac"
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/* Wrapper functions for accessing PCI configuration space */
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static void edac_pci_read_dword(struct pci_dev *dev, int reg, u32 *val32)
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{
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int ret;
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ret = pci_read_config_dword(dev, reg, val32);
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if (ret != 0)
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printk(KERN_ERR AMD8131_EDAC_MOD_STR
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" PCI Access Read Error at 0x%x\n", reg);
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}
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static void edac_pci_write_dword(struct pci_dev *dev, int reg, u32 val32)
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{
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int ret;
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ret = pci_write_config_dword(dev, reg, val32);
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if (ret != 0)
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printk(KERN_ERR AMD8131_EDAC_MOD_STR
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" PCI Access Write Error at 0x%x\n", reg);
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}
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static char * const bridge_str[] = {
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[NORTH_A] = "NORTH A",
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[NORTH_B] = "NORTH B",
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[SOUTH_A] = "SOUTH A",
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[SOUTH_B] = "SOUTH B",
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[NO_BRIDGE] = "NO BRIDGE",
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};
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/* Support up to two AMD8131 chipsets on a platform */
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static struct amd8131_dev_info amd8131_devices[] = {
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{
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.inst = NORTH_A,
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.devfn = DEVFN_PCIX_BRIDGE_NORTH_A,
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.ctl_name = "AMD8131_PCIX_NORTH_A",
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},
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{
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.inst = NORTH_B,
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.devfn = DEVFN_PCIX_BRIDGE_NORTH_B,
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.ctl_name = "AMD8131_PCIX_NORTH_B",
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},
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{
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.inst = SOUTH_A,
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.devfn = DEVFN_PCIX_BRIDGE_SOUTH_A,
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.ctl_name = "AMD8131_PCIX_SOUTH_A",
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},
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{
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.inst = SOUTH_B,
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.devfn = DEVFN_PCIX_BRIDGE_SOUTH_B,
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.ctl_name = "AMD8131_PCIX_SOUTH_B",
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},
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{.inst = NO_BRIDGE,},
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};
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static void amd8131_pcix_init(struct amd8131_dev_info *dev_info)
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{
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u32 val32;
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struct pci_dev *dev = dev_info->dev;
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/* First clear error detection flags */
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edac_pci_read_dword(dev, REG_MEM_LIM, &val32);
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if (val32 & MEM_LIMIT_MASK)
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edac_pci_write_dword(dev, REG_MEM_LIM, val32);
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/* Clear Discard Timer Timedout flag */
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edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
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if (val32 & INT_CTLR_DTS)
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edac_pci_write_dword(dev, REG_INT_CTLR, val32);
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/* Clear CRC Error flag on link side A */
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edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
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if (val32 & LNK_CTRL_CRCERR_A)
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edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
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/* Clear CRC Error flag on link side B */
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edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
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if (val32 & LNK_CTRL_CRCERR_B)
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edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);
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/*
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* Then enable all error detections.
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*
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* Setup Discard Timer Sync Flood Enable,
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* System Error Enable and Parity Error Enable.
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*/
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edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
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val32 |= INT_CTLR_PERR | INT_CTLR_SERR | INT_CTLR_DTSE;
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edac_pci_write_dword(dev, REG_INT_CTLR, val32);
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/* Enable overall SERR Error detection */
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edac_pci_read_dword(dev, REG_STS_CMD, &val32);
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val32 |= STS_CMD_SERREN;
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edac_pci_write_dword(dev, REG_STS_CMD, val32);
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/* Setup CRC Flood Enable for link side A */
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edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
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val32 |= LNK_CTRL_CRCFEN;
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edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
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/* Setup CRC Flood Enable for link side B */
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edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
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val32 |= LNK_CTRL_CRCFEN;
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edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);
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}
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static void amd8131_pcix_exit(struct amd8131_dev_info *dev_info)
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{
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u32 val32;
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struct pci_dev *dev = dev_info->dev;
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/* Disable SERR, PERR and DTSE Error detection */
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edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
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val32 &= ~(INT_CTLR_PERR | INT_CTLR_SERR | INT_CTLR_DTSE);
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edac_pci_write_dword(dev, REG_INT_CTLR, val32);
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/* Disable overall System Error detection */
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edac_pci_read_dword(dev, REG_STS_CMD, &val32);
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val32 &= ~STS_CMD_SERREN;
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edac_pci_write_dword(dev, REG_STS_CMD, val32);
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/* Disable CRC Sync Flood on link side A */
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edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
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val32 &= ~LNK_CTRL_CRCFEN;
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edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
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/* Disable CRC Sync Flood on link side B */
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edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
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val32 &= ~LNK_CTRL_CRCFEN;
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edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);
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}
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static void amd8131_pcix_check(struct edac_pci_ctl_info *edac_dev)
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{
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struct amd8131_dev_info *dev_info = edac_dev->pvt_info;
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struct pci_dev *dev = dev_info->dev;
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u32 val32;
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/* Check PCI-X Bridge Memory Base-Limit Register for errors */
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edac_pci_read_dword(dev, REG_MEM_LIM, &val32);
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if (val32 & MEM_LIMIT_MASK) {
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printk(KERN_INFO "Error(s) in mem limit register "
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"on %s bridge\n", dev_info->ctl_name);
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printk(KERN_INFO "DPE: %d, RSE: %d, RMA: %d\n"
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"RTA: %d, STA: %d, MDPE: %d\n",
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val32 & MEM_LIMIT_DPE,
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val32 & MEM_LIMIT_RSE,
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val32 & MEM_LIMIT_RMA,
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val32 & MEM_LIMIT_RTA,
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val32 & MEM_LIMIT_STA,
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val32 & MEM_LIMIT_MDPE);
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val32 |= MEM_LIMIT_MASK;
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edac_pci_write_dword(dev, REG_MEM_LIM, val32);
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edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
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}
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/* Check if Discard Timer timed out */
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edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
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if (val32 & INT_CTLR_DTS) {
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printk(KERN_INFO "Error(s) in interrupt and control register "
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"on %s bridge\n", dev_info->ctl_name);
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printk(KERN_INFO "DTS: %d\n", val32 & INT_CTLR_DTS);
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val32 |= INT_CTLR_DTS;
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edac_pci_write_dword(dev, REG_INT_CTLR, val32);
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edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
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}
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/* Check if CRC error happens on link side A */
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edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
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if (val32 & LNK_CTRL_CRCERR_A) {
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printk(KERN_INFO "Error(s) in link conf and control register "
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"on %s bridge\n", dev_info->ctl_name);
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printk(KERN_INFO "CRCERR: %d\n", val32 & LNK_CTRL_CRCERR_A);
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val32 |= LNK_CTRL_CRCERR_A;
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edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
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edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
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}
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/* Check if CRC error happens on link side B */
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edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
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if (val32 & LNK_CTRL_CRCERR_B) {
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printk(KERN_INFO "Error(s) in link conf and control register "
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"on %s bridge\n", dev_info->ctl_name);
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printk(KERN_INFO "CRCERR: %d\n", val32 & LNK_CTRL_CRCERR_B);
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val32 |= LNK_CTRL_CRCERR_B;
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edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);
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edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
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}
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}
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static struct amd8131_info amd8131_chipset = {
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.err_dev = PCI_DEVICE_ID_AMD_8131_APIC,
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.devices = amd8131_devices,
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.init = amd8131_pcix_init,
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.exit = amd8131_pcix_exit,
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.check = amd8131_pcix_check,
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};
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/*
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* There are 4 PCIX Bridges on ATCA-6101 that share the same PCI Device ID,
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* so amd8131_probe() would be called by kernel 4 times, with different
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* address of pci_dev for each of them each time.
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*/
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static int amd8131_probe(struct pci_dev *dev, const struct pci_device_id *id)
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{
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struct amd8131_dev_info *dev_info;
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for (dev_info = amd8131_chipset.devices; dev_info->inst != NO_BRIDGE;
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dev_info++)
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if (dev_info->devfn == dev->devfn)
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break;
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if (dev_info->inst == NO_BRIDGE) /* should never happen */
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return -ENODEV;
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/*
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* We can't call pci_get_device() as we are used to do because
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* there are 4 of them but pci_dev_get() instead.
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*/
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dev_info->dev = pci_dev_get(dev);
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if (pci_enable_device(dev_info->dev)) {
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pci_dev_put(dev_info->dev);
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printk(KERN_ERR "failed to enable:"
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"vendor %x, device %x, devfn %x, name %s\n",
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PCI_VENDOR_ID_AMD, amd8131_chipset.err_dev,
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dev_info->devfn, dev_info->ctl_name);
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return -ENODEV;
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}
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/*
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* we do not allocate extra private structure for
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* edac_pci_ctl_info, but make use of existing
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* one instead.
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*/
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dev_info->edac_idx = edac_pci_alloc_index();
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dev_info->edac_dev = edac_pci_alloc_ctl_info(0, dev_info->ctl_name);
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if (!dev_info->edac_dev)
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return -ENOMEM;
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dev_info->edac_dev->pvt_info = dev_info;
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dev_info->edac_dev->dev = &dev_info->dev->dev;
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dev_info->edac_dev->mod_name = AMD8131_EDAC_MOD_STR;
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dev_info->edac_dev->ctl_name = dev_info->ctl_name;
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dev_info->edac_dev->dev_name = dev_info->dev->dev.bus_id;
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if (edac_op_state == EDAC_OPSTATE_POLL)
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dev_info->edac_dev->edac_check = amd8131_chipset.check;
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if (amd8131_chipset.init)
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amd8131_chipset.init(dev_info);
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if (edac_pci_add_device(dev_info->edac_dev, dev_info->edac_idx) > 0) {
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printk(KERN_ERR "failed edac_pci_add_device() for %s\n",
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dev_info->ctl_name);
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edac_pci_free_ctl_info(dev_info->edac_dev);
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return -ENODEV;
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}
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printk(KERN_INFO "added one device on AMD8131 "
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"vendor %x, device %x, devfn %x, name %s\n",
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PCI_VENDOR_ID_AMD, amd8131_chipset.err_dev,
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dev_info->devfn, dev_info->ctl_name);
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return 0;
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}
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static void amd8131_remove(struct pci_dev *dev)
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{
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struct amd8131_dev_info *dev_info;
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for (dev_info = amd8131_chipset.devices; dev_info->inst != NO_BRIDGE;
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dev_info++)
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if (dev_info->devfn == dev->devfn)
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break;
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if (dev_info->inst == NO_BRIDGE) /* should never happen */
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return;
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if (dev_info->edac_dev) {
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edac_pci_del_device(dev_info->edac_dev->dev);
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edac_pci_free_ctl_info(dev_info->edac_dev);
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}
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if (amd8131_chipset.exit)
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amd8131_chipset.exit(dev_info);
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pci_dev_put(dev_info->dev);
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}
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static const struct pci_device_id amd8131_edac_pci_tbl[] = {
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{
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PCI_VEND_DEV(AMD, 8131_BRIDGE),
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.class = 0,
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.class_mask = 0,
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.driver_data = 0,
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},
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{
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0,
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} /* table is NULL-terminated */
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};
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MODULE_DEVICE_TABLE(pci, amd8131_edac_pci_tbl);
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static struct pci_driver amd8131_edac_driver = {
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.name = AMD8131_EDAC_MOD_STR,
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.probe = amd8131_probe,
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.remove = amd8131_remove,
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.id_table = amd8131_edac_pci_tbl,
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};
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static int __init amd8131_edac_init(void)
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{
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printk(KERN_INFO "AMD8131 EDAC driver " AMD8131_EDAC_REVISION "\n");
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printk(KERN_INFO "\t(c) 2008 Wind River Systems, Inc.\n");
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/* Only POLL mode supported so far */
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edac_op_state = EDAC_OPSTATE_POLL;
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return pci_register_driver(&amd8131_edac_driver);
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}
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static void __exit amd8131_edac_exit(void)
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{
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pci_unregister_driver(&amd8131_edac_driver);
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}
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module_init(amd8131_edac_init);
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module_exit(amd8131_edac_exit);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Cao Qingtao <qingtao.cao@windriver.com>\n");
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MODULE_DESCRIPTION("AMD8131 HyperTransport PCI-X Tunnel EDAC kernel module");
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