cxl/pci: Add (hopeful) error handling support
Add nominal error handling that tears down CXL.mem in response to error notifications that imply a device reset. Given some CXL.mem may be operating as System RAM, there is a high likelihood that these error events are fatal. However, if the system survives the notification the expectation is that the driver behavior is equivalent to a hot-unplug and re-plug of an endpoint. Note that this does not change the mask values from the default. That awaits CXL _OSC support to determine whether platform firmware is in control of the mask registers. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/166974413966.1608150.15522782911404473932.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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2905cb5236
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@ -344,6 +344,7 @@ struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds)
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* needed as this is ordered with cdev_add() publishing the device.
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*/
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cxlmd->cxlds = cxlds;
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cxlds->cxlmd = cxlmd;
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cdev = &cxlmd->cdev;
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rc = cdev_device_add(cdev, dev);
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@ -132,6 +132,7 @@ static inline int ways_to_cxl(unsigned int ways, u8 *iw)
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#define CXL_RAS_CORRECTABLE_MASK_OFFSET 0x10
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#define CXL_RAS_CORRECTABLE_MASK_MASK GENMASK(6, 0)
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#define CXL_RAS_CAP_CONTROL_OFFSET 0x14
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#define CXL_RAS_CAP_CONTROL_FE_MASK GENMASK(5, 0)
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#define CXL_RAS_HEADER_LOG_OFFSET 0x18
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#define CXL_RAS_CAPABILITY_LENGTH 0x58
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@ -186,6 +186,7 @@ struct cxl_endpoint_dvsec_info {
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* Currently only memory devices are represented.
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*
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* @dev: The device associated with this CXL state
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* @cxlmd: The device representing the CXL.mem capabilities of @dev
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* @regs: Parsed register blocks
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* @cxl_dvsec: Offset to the PCIe device DVSEC
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* @payload_size: Size of space for payload
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@ -218,6 +219,7 @@ struct cxl_endpoint_dvsec_info {
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*/
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struct cxl_dev_state {
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struct device *dev;
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struct cxl_memdev *cxlmd;
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struct cxl_regs regs;
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int cxl_dvsec;
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@ -9,6 +9,7 @@
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#include <linux/list.h>
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#include <linux/pci.h>
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#include <linux/pci-doe.h>
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#include <linux/aer.h>
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#include <linux/io.h>
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#include "cxlmem.h"
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#include "cxlpci.h"
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@ -399,6 +400,11 @@ static void devm_cxl_pci_create_doe(struct cxl_dev_state *cxlds)
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}
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}
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static void disable_aer(void *pdev)
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{
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pci_disable_pcie_error_reporting(pdev);
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}
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static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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struct cxl_register_map map;
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@ -420,6 +426,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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cxlds = cxl_dev_state_create(&pdev->dev);
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if (IS_ERR(cxlds))
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return PTR_ERR(cxlds);
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pci_set_drvdata(pdev, cxlds);
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cxlds->serial = pci_get_dsn(pdev);
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cxlds->cxl_dvsec = pci_find_dvsec_capability(
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@ -474,6 +481,14 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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if (IS_ERR(cxlmd))
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return PTR_ERR(cxlmd);
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if (cxlds->regs.ras) {
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pci_enable_pcie_error_reporting(pdev);
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rc = devm_add_action_or_reset(&pdev->dev, disable_aer, pdev);
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if (rc)
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return rc;
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}
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pci_save_state(pdev);
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if (resource_size(&cxlds->pmem_res) && IS_ENABLED(CONFIG_CXL_PMEM))
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rc = devm_cxl_add_nvdimm(&pdev->dev, cxlmd);
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@ -487,10 +502,132 @@ static const struct pci_device_id cxl_mem_pci_tbl[] = {
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};
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MODULE_DEVICE_TABLE(pci, cxl_mem_pci_tbl);
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/* CXL spec rev3.0 8.2.4.16.1 */
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static void header_log_copy(struct cxl_dev_state *cxlds, u32 *log)
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{
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void __iomem *addr;
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u32 *log_addr;
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int i, log_u32_size = CXL_HEADERLOG_SIZE / sizeof(u32);
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addr = cxlds->regs.ras + CXL_RAS_HEADER_LOG_OFFSET;
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log_addr = log;
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for (i = 0; i < log_u32_size; i++) {
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*log_addr = readl(addr);
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log_addr++;
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addr += sizeof(u32);
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}
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}
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/*
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* Log the state of the RAS status registers and prepare them to log the
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* next error status. Return 1 if reset needed.
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*/
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static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
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{
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struct cxl_memdev *cxlmd = cxlds->cxlmd;
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struct device *dev = &cxlmd->dev;
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u32 hl[CXL_HEADERLOG_SIZE_U32];
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void __iomem *addr;
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u32 status;
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u32 fe;
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if (!cxlds->regs.ras)
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return false;
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addr = cxlds->regs.ras + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET;
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status = le32_to_cpu((__force __le32)readl(addr));
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if (!(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK))
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return false;
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/* If multiple errors, log header points to first error from ctrl reg */
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if (hweight32(status) > 1) {
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addr = cxlds->regs.ras + CXL_RAS_CAP_CONTROL_OFFSET;
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fe = BIT(le32_to_cpu((__force __le32)readl(addr)) &
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CXL_RAS_CAP_CONTROL_FE_MASK);
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} else {
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fe = status;
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}
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header_log_copy(cxlds, hl);
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trace_cxl_aer_uncorrectable_error(dev_name(dev), status, fe, hl);
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writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr);
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return true;
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}
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static pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
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pci_channel_state_t state)
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{
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struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
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struct cxl_memdev *cxlmd = cxlds->cxlmd;
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struct device *dev = &cxlmd->dev;
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bool ue;
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/*
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* A frozen channel indicates an impending reset which is fatal to
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* CXL.mem operation, and will likely crash the system. On the off
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* chance the situation is recoverable dump the status of the RAS
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* capability registers and bounce the active state of the memdev.
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*/
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ue = cxl_report_and_clear(cxlds);
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switch (state) {
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case pci_channel_io_normal:
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if (ue) {
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device_release_driver(dev);
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return PCI_ERS_RESULT_NEED_RESET;
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}
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return PCI_ERS_RESULT_CAN_RECOVER;
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case pci_channel_io_frozen:
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dev_warn(&pdev->dev,
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"%s: frozen state error detected, disable CXL.mem\n",
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dev_name(dev));
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device_release_driver(dev);
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return PCI_ERS_RESULT_NEED_RESET;
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case pci_channel_io_perm_failure:
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dev_warn(&pdev->dev,
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"failure state error detected, request disconnect\n");
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return PCI_ERS_RESULT_DISCONNECT;
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}
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return PCI_ERS_RESULT_NEED_RESET;
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}
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static pci_ers_result_t cxl_slot_reset(struct pci_dev *pdev)
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{
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struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
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struct cxl_memdev *cxlmd = cxlds->cxlmd;
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struct device *dev = &cxlmd->dev;
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dev_info(&pdev->dev, "%s: restart CXL.mem after slot reset\n",
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dev_name(dev));
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pci_restore_state(pdev);
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if (device_attach(dev) <= 0)
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return PCI_ERS_RESULT_DISCONNECT;
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return PCI_ERS_RESULT_RECOVERED;
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}
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static void cxl_error_resume(struct pci_dev *pdev)
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{
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struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
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struct cxl_memdev *cxlmd = cxlds->cxlmd;
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struct device *dev = &cxlmd->dev;
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dev_info(&pdev->dev, "%s: error resume %s\n", dev_name(dev),
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dev->driver ? "successful" : "failed");
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}
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static const struct pci_error_handlers cxl_error_handlers = {
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.error_detected = cxl_error_detected,
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.slot_reset = cxl_slot_reset,
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.resume = cxl_error_resume,
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};
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static struct pci_driver cxl_pci_driver = {
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.name = KBUILD_MODNAME,
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.id_table = cxl_mem_pci_tbl,
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.probe = cxl_pci_probe,
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.err_handler = &cxl_error_handlers,
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.driver = {
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.probe_type = PROBE_PREFER_ASYNCHRONOUS,
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},
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