drm/radeon: fix bank information in tiling config
While there are cards with more than 8 mem banks, the max number of banks from a tiling perspective is 8, so cap the tiling config at 8 banks. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=43448 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
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29d654067a
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@ -2136,9 +2136,12 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
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/* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
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/* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
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if (rdev->flags & RADEON_IS_IGP)
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if (rdev->flags & RADEON_IS_IGP)
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rdev->config.evergreen.tile_config |= 1 << 4;
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rdev->config.evergreen.tile_config |= 1 << 4;
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else
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else {
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rdev->config.evergreen.tile_config |=
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if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
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((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
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rdev->config.evergreen.tile_config |= 1 << 4;
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else
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rdev->config.evergreen.tile_config |= 0 << 4;
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}
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rdev->config.evergreen.tile_config |=
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rdev->config.evergreen.tile_config |=
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((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
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((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
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rdev->config.evergreen.tile_config |=
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rdev->config.evergreen.tile_config |=
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@ -866,9 +866,12 @@ static void cayman_gpu_init(struct radeon_device *rdev)
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/* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
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/* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
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if (rdev->flags & RADEON_IS_IGP)
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if (rdev->flags & RADEON_IS_IGP)
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rdev->config.cayman.tile_config |= 1 << 4;
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rdev->config.cayman.tile_config |= 1 << 4;
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else
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else {
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rdev->config.cayman.tile_config |=
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if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
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((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
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rdev->config.cayman.tile_config |= 1 << 4;
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else
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rdev->config.cayman.tile_config |= 0 << 4;
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}
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rdev->config.cayman.tile_config |=
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rdev->config.cayman.tile_config |=
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((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
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((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
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rdev->config.cayman.tile_config |=
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rdev->config.cayman.tile_config |=
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@ -689,8 +689,12 @@ static void rv770_gpu_init(struct radeon_device *rdev)
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if (rdev->family == CHIP_RV770)
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if (rdev->family == CHIP_RV770)
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gb_tiling_config |= BANK_TILING(1);
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gb_tiling_config |= BANK_TILING(1);
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else
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else {
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gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
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if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
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gb_tiling_config |= BANK_TILING(1);
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else
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gb_tiling_config |= BANK_TILING(0);
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}
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rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
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rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
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gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
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gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
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if ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
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if ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
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