OMAPDSS: DISPC: Add MFLAG defines
OMAP5 has MFLAG feature in DISPC. Add the register definition and dump it. The register is not used yet, though. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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@ -3213,6 +3213,8 @@ static void dispc_dump_regs(struct seq_file *s)
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DUMPREG(DISPC_CONTROL3);
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DUMPREG(DISPC_CONFIG3);
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}
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if (dss_has_feature(FEAT_MFLAG))
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DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
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#undef DUMPREG
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@ -3287,6 +3289,8 @@ static void dispc_dump_regs(struct seq_file *s)
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DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
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if (dss_has_feature(FEAT_PRELOAD))
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DUMPREG(i, DISPC_OVL_PRELOAD);
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if (dss_has_feature(FEAT_MFLAG))
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DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
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}
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#undef DISPC_REG
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@ -40,6 +40,7 @@
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#define DISPC_CONTROL3 0x0848
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#define DISPC_CONFIG3 0x084C
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#define DISPC_MSTANDBY_CTRL 0x0858
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#define DISPC_GLOBAL_MFLAG_ATTRIBUTE 0x085C
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/* DISPC overlay registers */
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#define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \
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@ -100,6 +101,8 @@
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DISPC_FIR_COEF_V2_OFFSET(n, i))
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#define DISPC_OVL_PRELOAD(n) (DISPC_OVL_BASE(n) + \
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DISPC_PRELOAD_OFFSET(n))
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#define DISPC_OVL_MFLAG_THRESHOLD(n) (DISPC_OVL_BASE(n) + \
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DISPC_MFLAG_THRESHOLD_OFFSET(n))
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/* DISPC up/downsampling FIR filter coefficient structure */
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struct dispc_coef {
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@ -894,4 +897,21 @@ static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
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return 0;
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}
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}
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static inline u16 DISPC_MFLAG_THRESHOLD_OFFSET(enum omap_plane plane)
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{
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switch (plane) {
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case OMAP_DSS_GFX:
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return 0x0860;
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case OMAP_DSS_VIDEO1:
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return 0x0864;
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case OMAP_DSS_VIDEO2:
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return 0x0868;
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case OMAP_DSS_VIDEO3:
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return 0x086c;
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default:
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BUG();
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return 0;
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}
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}
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#endif
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@ -613,6 +613,7 @@ static const enum dss_feat_id omap5_dss_feat_list[] = {
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FEAT_DSI_PLL_SELFREQDCO,
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FEAT_DSI_PLL_REFSEL,
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FEAT_DSI_PHY_DCC,
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FEAT_MFLAG,
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};
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/* OMAP2 DSS Features */
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@ -64,6 +64,7 @@ enum dss_feat_id {
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FEAT_DSI_PLL_SELFREQDCO,
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FEAT_DSI_PLL_REFSEL,
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FEAT_DSI_PHY_DCC,
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FEAT_MFLAG,
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};
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/* DSS register field id */
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