ath9k: fix indentation in ar9003_hw_set_power_per_rate_table
The current indentation is off by one tab. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Gabor Juhos
John W. Linville
Родитель
5fc512439f
Коммит
2a0b50c770
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@ -4901,84 +4901,79 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
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i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
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chan->channel);
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/*
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* compare test group from regulatory
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* channel list with test mode from pCtlMode
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* list
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*/
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if ((((cfgCtl & ~CTL_MODE_M) |
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(pCtlMode[ctlMode] & CTL_MODE_M)) ==
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ctlIndex[i]) ||
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(((cfgCtl & ~CTL_MODE_M) |
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(pCtlMode[ctlMode] & CTL_MODE_M)) ==
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((ctlIndex[i] & CTL_MODE_M) |
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SD_NO_CTL))) {
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twiceMinEdgePower =
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ar9003_hw_get_max_edge_power(pEepData,
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freq, i,
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is2ghz);
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/*
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* compare test group from regulatory
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* channel list with test mode from pCtlMode
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* list
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*/
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if ((((cfgCtl & ~CTL_MODE_M) |
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(pCtlMode[ctlMode] & CTL_MODE_M)) ==
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ctlIndex[i]) ||
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(((cfgCtl & ~CTL_MODE_M) |
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(pCtlMode[ctlMode] & CTL_MODE_M)) ==
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((ctlIndex[i] & CTL_MODE_M) |
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SD_NO_CTL))) {
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twiceMinEdgePower =
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ar9003_hw_get_max_edge_power(pEepData,
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freq, i,
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is2ghz);
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if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
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/*
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* Find the minimum of all CTL
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* edge powers that apply to
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* this channel
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*/
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twiceMaxEdgePower =
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min(twiceMaxEdgePower,
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twiceMinEdgePower);
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else {
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/* specific */
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twiceMaxEdgePower =
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twiceMinEdgePower;
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break;
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}
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if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
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/*
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* Find the minimum of all CTL
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* edge powers that apply to
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* this channel
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*/
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twiceMaxEdgePower =
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min(twiceMaxEdgePower,
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twiceMinEdgePower);
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else {
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/* specific */
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twiceMaxEdgePower = twiceMinEdgePower;
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break;
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}
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}
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}
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minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
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minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
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ath_dbg(common, REGULATORY,
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"SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
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ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
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scaledPower, minCtlPower);
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ath_dbg(common, REGULATORY,
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"SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
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ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
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scaledPower, minCtlPower);
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/* Apply ctl mode to correct target power set */
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switch (pCtlMode[ctlMode]) {
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case CTL_11B:
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for (i = ALL_TARGET_LEGACY_1L_5L;
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i <= ALL_TARGET_LEGACY_11S; i++)
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pPwrArray[i] =
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(u8)min((u16)pPwrArray[i],
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minCtlPower);
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break;
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case CTL_11A:
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case CTL_11G:
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for (i = ALL_TARGET_LEGACY_6_24;
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i <= ALL_TARGET_LEGACY_54; i++)
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pPwrArray[i] =
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(u8)min((u16)pPwrArray[i],
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minCtlPower);
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break;
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case CTL_5GHT20:
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case CTL_2GHT20:
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for (i = ALL_TARGET_HT20_0_8_16;
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i <= ALL_TARGET_HT20_23; i++)
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pPwrArray[i] =
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(u8)min((u16)pPwrArray[i],
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minCtlPower);
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break;
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case CTL_5GHT40:
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case CTL_2GHT40:
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for (i = ALL_TARGET_HT40_0_8_16;
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i <= ALL_TARGET_HT40_23; i++)
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pPwrArray[i] =
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(u8)min((u16)pPwrArray[i],
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minCtlPower);
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break;
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default:
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break;
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}
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/* Apply ctl mode to correct target power set */
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switch (pCtlMode[ctlMode]) {
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case CTL_11B:
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for (i = ALL_TARGET_LEGACY_1L_5L;
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i <= ALL_TARGET_LEGACY_11S; i++)
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pPwrArray[i] = (u8)min((u16)pPwrArray[i],
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minCtlPower);
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break;
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case CTL_11A:
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case CTL_11G:
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for (i = ALL_TARGET_LEGACY_6_24;
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i <= ALL_TARGET_LEGACY_54; i++)
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pPwrArray[i] = (u8)min((u16)pPwrArray[i],
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minCtlPower);
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break;
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case CTL_5GHT20:
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case CTL_2GHT20:
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for (i = ALL_TARGET_HT20_0_8_16;
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i <= ALL_TARGET_HT20_23; i++)
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pPwrArray[i] = (u8)min((u16)pPwrArray[i],
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minCtlPower);
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break;
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case CTL_5GHT40:
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case CTL_2GHT40:
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for (i = ALL_TARGET_HT40_0_8_16;
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i <= ALL_TARGET_HT40_23; i++)
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pPwrArray[i] = (u8)min((u16)pPwrArray[i],
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minCtlPower);
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break;
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default:
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break;
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}
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} /* end ctl mode checking */
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}
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