drm/i915: add some more "i" in platform names for consistency
Consistency FTW. Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/9ab811dc06570bd3fc05a917ade1bdc9bb805a75.1480520526.git.jani.nikula@intel.com
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c0f86832e3
Коммит
2a307c2e91
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@ -2955,7 +2955,7 @@ static bool cursor_active(struct drm_i915_private *dev_priv, int pipe)
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{
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u32 state;
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if (IS_845G(dev_priv) || IS_I865G(dev_priv))
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if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
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state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
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else
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state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
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@ -2515,7 +2515,7 @@ intel_info(const struct drm_i915_private *dev_priv)
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(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
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#define IS_I830(dev_priv) (INTEL_DEVID(dev_priv) == 0x3577)
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#define IS_845G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2562)
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#define IS_I845G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2562)
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#define IS_I85X(dev_priv) ((dev_priv)->info.platform == INTEL_I85X)
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#define IS_I865G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2572)
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#define IS_I915G(dev_priv) ((dev_priv)->info.platform == INTEL_I915G)
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@ -2667,7 +2667,7 @@ intel_info(const struct drm_i915_private *dev_priv)
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((dev_priv)->info.overlay_needs_physical)
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/* Early gen2 have a totally busted CS tlb and require pinned batches. */
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#define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_845G(dev_priv))
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#define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
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/* WaRsDisableCoarsePowerGating:skl,bxt */
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#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
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@ -153,7 +153,7 @@ static unsigned long i915_stolen_to_physical(struct drm_i915_private *dev_priv)
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tom = tmp * MB(32);
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base = tom - tseg_size - ggtt->stolen_size;
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} else if (IS_845G(dev_priv)) {
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} else if (IS_I845G(dev_priv)) {
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u32 tseg_size = 0;
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u32 tom;
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u8 tmp;
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@ -71,7 +71,7 @@ static const struct intel_device_info intel_i830_info = {
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.num_pipes = 2, /* legal, last one wins */
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};
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static const struct intel_device_info intel_845g_info = {
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static const struct intel_device_info intel_i845g_info = {
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GEN2_FEATURES,
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.platform = INTEL_I845G,
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};
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@ -432,7 +432,7 @@ static const struct intel_device_info intel_kabylake_gt3_info = {
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*/
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static const struct pci_device_id pciidlist[] = {
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INTEL_I830_IDS(&intel_i830_info),
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INTEL_I845G_IDS(&intel_845g_info),
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INTEL_I845G_IDS(&intel_i845g_info),
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INTEL_I85X_IDS(&intel_i85x_info),
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INTEL_I865G_IDS(&intel_i865g_info),
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INTEL_I915G_IDS(&intel_i915g_info),
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@ -1233,7 +1233,7 @@ static void assert_cursor(struct drm_i915_private *dev_priv,
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{
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bool cur_state;
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if (IS_845G(dev_priv) || IS_I865G(dev_priv))
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if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
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cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
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else
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cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
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@ -10936,7 +10936,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
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I915_WRITE(CURPOS(pipe), pos);
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if (IS_845G(dev_priv) || IS_I865G(dev_priv))
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if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
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i845_update_cursor(crtc, base, plane_state);
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else
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i9xx_update_cursor(crtc, base, plane_state);
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@ -10954,11 +10954,11 @@ static bool cursor_size_ok(struct drm_i915_private *dev_priv,
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* the precision of the register. Everything else requires
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* square cursors, limited to a few power-of-two sizes.
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*/
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if (IS_845G(dev_priv) || IS_I865G(dev_priv)) {
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if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
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if ((width & 63) != 0)
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return false;
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if (width > (IS_845G(dev_priv) ? 64 : 512))
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if (width > (IS_I845G(dev_priv) ? 64 : 512))
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return false;
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if (height > 1023)
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@ -16127,7 +16127,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
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else if (IS_I915G(dev_priv))
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dev_priv->display.get_display_clock_speed =
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i915_get_display_clock_speed;
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else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
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else if (IS_I945GM(dev_priv) || IS_I845G(dev_priv))
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dev_priv->display.get_display_clock_speed =
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i9xx_misc_get_display_clock_speed;
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else if (IS_I915GM(dev_priv))
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@ -16549,8 +16549,8 @@ int intel_modeset_init(struct drm_device *dev)
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dev->mode_config.max_height = 8192;
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}
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if (IS_845G(dev_priv) || IS_I865G(dev_priv)) {
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dev->mode_config.cursor_width = IS_845G(dev_priv) ? 64 : 512;
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if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
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dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
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dev->mode_config.cursor_height = 1023;
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} else if (IS_GEN2(dev_priv)) {
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dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
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@ -139,7 +139,7 @@ static u32 get_reserved(struct intel_gmbus *bus)
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u32 reserved = 0;
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/* On most chips, these bits must be preserved in software. */
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if (!IS_I830(dev_priv) && !IS_845G(dev_priv))
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if (!IS_I830(dev_priv) && !IS_I845G(dev_priv))
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reserved = I915_READ_NOTRACE(bus->gpio_reg) &
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(GPIO_DATA_PULLUP_DISABLE |
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GPIO_CLOCK_PULLUP_DISABLE);
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@ -957,7 +957,7 @@ static int check_overlay_src(struct drm_i915_private *dev_priv,
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u32 tmp;
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/* check src dimensions */
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if (IS_845G(dev_priv) || IS_I830(dev_priv)) {
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if (IS_I845G(dev_priv) || IS_I830(dev_priv)) {
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if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
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rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
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return -EINVAL;
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@ -1009,7 +1009,7 @@ static int check_overlay_src(struct drm_i915_private *dev_priv,
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return -EINVAL;
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/* stride checking */
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if (IS_I830(dev_priv) || IS_845G(dev_priv))
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if (IS_I830(dev_priv) || IS_I845G(dev_priv))
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stride_mask = 255;
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else
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stride_mask = 63;
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@ -1912,7 +1912,7 @@ intel_engine_create_ring(struct intel_engine_cs *engine, int size)
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* of the buffer.
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*/
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ring->effective_size = size;
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if (IS_I830(engine->i915) || IS_845G(engine->i915))
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if (IS_I830(engine->i915) || IS_I845G(engine->i915))
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ring->effective_size -= 2 * CACHELINE_BYTES;
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ring->last_retired_head = -1;
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@ -2608,7 +2608,7 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
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engine->emit_bb_start = gen6_emit_bb_start;
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else if (INTEL_GEN(dev_priv) >= 4)
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engine->emit_bb_start = i965_emit_bb_start;
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else if (IS_I830(dev_priv) || IS_845G(dev_priv))
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else if (IS_I830(dev_priv) || IS_I845G(dev_priv))
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engine->emit_bb_start = i830_emit_bb_start;
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else
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engine->emit_bb_start = i915_emit_bb_start;
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