MIPS: Netlogic: Move from u32 cpumask to cpumask_t
Initial code to support more than 32 cpus. The platform CPU mask is updated from 32-bit mask to cpumask_t. Convert places that use cpu_/cpus_ functions to use cpumask_* functions. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4464 Signed-off-by: John Crispin <blogic@openwrt.org>
This commit is contained in:
Jayachandran C
John Crispin
Родитель
7143246e9a
Коммит
2a37b1ae44
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@ -45,6 +45,8 @@
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#define BOOT_NMI_HANDLER 8
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#ifndef __ASSEMBLY__
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#include <linux/cpumask.h>
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struct irq_desc;
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extern struct plat_smp_ops nlm_smp_ops;
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extern char nlm_reset_entry[], nlm_reset_entry_end[];
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@ -52,7 +54,7 @@ void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
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void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
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void nlm_smp_irq_init(void);
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void nlm_boot_secondary_cpus(void);
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int nlm_wakeup_secondary_cpus(u32 wakeup_mask);
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int nlm_wakeup_secondary_cpus(void);
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void nlm_rmiboot_preboot(void);
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static inline void
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@ -71,6 +73,7 @@ unsigned int nlm_get_cpu_frequency(void);
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extern unsigned long nlm_common_ebase;
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extern int nlm_threads_per_core;
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extern uint32_t nlm_cpumask, nlm_coremask;
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extern uint32_t nlm_coremask;
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extern cpumask_t nlm_cpumask;
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#endif
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#endif /* _NETLOGIC_COMMON_H_ */
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@ -160,9 +160,9 @@ void __init nlm_smp_setup(void)
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int num_cpus, i;
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boot_cpu = hard_smp_processor_id();
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cpus_clear(phys_cpu_present_map);
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cpumask_clear(&phys_cpu_present_map);
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cpu_set(boot_cpu, phys_cpu_present_map);
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cpumask_set_cpu(boot_cpu, &phys_cpu_present_map);
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__cpu_number_map[boot_cpu] = 0;
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__cpu_logical_map[0] = boot_cpu;
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set_cpu_possible(0, true);
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@ -174,7 +174,7 @@ void __init nlm_smp_setup(void)
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* it is only set for ASPs (see smpboot.S)
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*/
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if (nlm_cpu_ready[i]) {
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cpu_set(i, phys_cpu_present_map);
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cpumask_set_cpu(i, &phys_cpu_present_map);
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__cpu_number_map[i] = num_cpus;
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__cpu_logical_map[num_cpus] = i;
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set_cpu_possible(num_cpus, true);
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@ -183,19 +183,22 @@ void __init nlm_smp_setup(void)
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}
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pr_info("Phys CPU present map: %lx, possible map %lx\n",
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(unsigned long)phys_cpu_present_map.bits[0],
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(unsigned long)cpumask_bits(&phys_cpu_present_map)[0],
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(unsigned long)cpumask_bits(cpu_possible_mask)[0]);
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pr_info("Detected %i Slave CPU(s)\n", num_cpus);
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nlm_set_nmi_handler(nlm_boot_secondary_cpus);
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}
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static int nlm_parse_cpumask(u32 cpu_mask)
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static int nlm_parse_cpumask(cpumask_t *wakeup_mask)
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{
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uint32_t core0_thr_mask, core_thr_mask;
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int threadmode, i;
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int threadmode, i, j;
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core0_thr_mask = cpu_mask & 0xf;
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core0_thr_mask = 0;
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for (i = 0; i < 4; i++)
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if (cpumask_test_cpu(i, wakeup_mask))
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core0_thr_mask |= (1 << i);
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switch (core0_thr_mask) {
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case 1:
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nlm_threads_per_core = 1;
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@ -214,25 +217,23 @@ static int nlm_parse_cpumask(u32 cpu_mask)
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}
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/* Verify other cores CPU masks */
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nlm_coremask = 1;
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nlm_cpumask = core0_thr_mask;
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for (i = 1; i < 8; i++) {
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core_thr_mask = (cpu_mask >> (i * 4)) & 0xf;
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if (core_thr_mask) {
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if (core_thr_mask != core0_thr_mask)
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for (i = 0; i < NR_CPUS; i += 4) {
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core_thr_mask = 0;
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for (j = 0; j < 4; j++)
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if (cpumask_test_cpu(i + j, wakeup_mask))
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core_thr_mask |= (1 << j);
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if (core_thr_mask != 0 && core_thr_mask != core0_thr_mask)
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goto unsupp;
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nlm_coremask |= 1 << i;
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nlm_cpumask |= core0_thr_mask << (4 * i);
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}
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}
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return threadmode;
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unsupp:
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panic("Unsupported CPU mask %x\n", cpu_mask);
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panic("Unsupported CPU mask %lx\n",
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(unsigned long)cpumask_bits(wakeup_mask)[0]);
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return 0;
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}
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int __cpuinit nlm_wakeup_secondary_cpus(u32 wakeup_mask)
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int __cpuinit nlm_wakeup_secondary_cpus(void)
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{
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unsigned long reset_vec;
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char *reset_data;
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@ -244,7 +245,7 @@ int __cpuinit nlm_wakeup_secondary_cpus(u32 wakeup_mask)
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(nlm_reset_entry_end - nlm_reset_entry));
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/* verify the mask and setup core config variables */
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threadmode = nlm_parse_cpumask(wakeup_mask);
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threadmode = nlm_parse_cpumask(&nlm_cpumask);
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/* Setup CPU init parameters */
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reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS);
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@ -55,7 +55,8 @@
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unsigned long nlm_common_ebase = 0x0;
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/* default to uniprocessor */
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uint32_t nlm_coremask = 1, nlm_cpumask = 1;
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uint32_t nlm_coremask = 1;
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cpumask_t nlm_cpumask = CPU_MASK_CPU0;
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int nlm_threads_per_core = 1;
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extern u32 __dtb_start[];
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@ -115,7 +116,8 @@ void __init prom_init(void)
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nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1));
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#ifdef CONFIG_SMP
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nlm_wakeup_secondary_cpus(0xffffffff);
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cpumask_setall(&nlm_cpumask);
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nlm_wakeup_secondary_cpus();
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/* update TLB size after waking up threads */
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current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
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@ -51,45 +51,66 @@
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#include <asm/netlogic/xlp-hal/xlp.h>
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#include <asm/netlogic/xlp-hal/sys.h>
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static void xlp_enable_secondary_cores(void)
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static int xlp_wakeup_core(uint64_t sysbase, int core)
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{
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uint32_t core, value, coremask, syscoremask;
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uint32_t coremask, value;
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int count;
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/* read cores in reset from SYS block */
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syscoremask = nlm_read_sys_reg(nlm_sys_base, SYS_CPU_RESET);
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coremask = (1 << core);
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/* update user specified */
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nlm_coremask = nlm_coremask & (syscoremask | 1);
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/* Enable CPU clock */
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value = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL);
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value &= ~coremask;
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nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value);
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for (core = 1; core < 8; core++) {
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coremask = 1 << core;
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if ((nlm_coremask & coremask) == 0)
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continue;
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/* Remove CPU Reset */
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value = nlm_read_sys_reg(sysbase, SYS_CPU_RESET);
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value &= ~coremask;
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nlm_write_sys_reg(sysbase, SYS_CPU_RESET, value);
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/* Enable CPU clock */
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value = nlm_read_sys_reg(nlm_sys_base, SYS_CORE_DFS_DIS_CTRL);
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value &= ~coremask;
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nlm_write_sys_reg(nlm_sys_base, SYS_CORE_DFS_DIS_CTRL, value);
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/* Poll for CPU to mark itself coherent */
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count = 100000;
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do {
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value = nlm_read_sys_reg(sysbase, SYS_CPU_NONCOHERENT_MODE);
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} while ((value & coremask) != 0 && --count > 0);
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/* Remove CPU Reset */
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value = nlm_read_sys_reg(nlm_sys_base, SYS_CPU_RESET);
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value &= ~coremask;
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nlm_write_sys_reg(nlm_sys_base, SYS_CPU_RESET, value);
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return count != 0;
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}
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/* Poll for CPU to mark itself coherent */
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count = 100000;
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do {
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value = nlm_read_sys_reg(nlm_sys_base,
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SYS_CPU_NONCOHERENT_MODE);
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} while ((value & coremask) != 0 && count-- > 0);
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static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
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{
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uint64_t syspcibase, sysbase;
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uint32_t syscoremask;
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int core, n;
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if (count == 0)
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pr_err("Failed to enable core %d\n", core);
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for (n = 0; n < 4; n++) {
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syspcibase = nlm_get_sys_pcibase(n);
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if (nlm_read_reg(syspcibase, 0) == 0xffffffff)
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break;
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/* read cores in reset from SYS and account for boot cpu */
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sysbase = nlm_get_sys_regbase(n);
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syscoremask = nlm_read_sys_reg(sysbase, SYS_CPU_RESET);
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if (n == 0)
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syscoremask |= 1;
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for (core = 0; core < 8; core++) {
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/* see if the core exists */
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if ((syscoremask & (1 << core)) == 0)
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continue;
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/* see if at least the first thread is enabled */
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if (!cpumask_test_cpu((n * 8 + core) * 4, wakeup_mask))
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continue;
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/* wake up the core */
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if (!xlp_wakeup_core(sysbase, core))
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pr_err("Failed to enable core %d\n", core);
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}
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}
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}
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void xlp_wakeup_secondary_cpus(void)
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void xlp_wakeup_secondary_cpus()
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{
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/*
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* In case of u-boot, the secondaries are in reset
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@ -98,5 +119,5 @@ void xlp_wakeup_secondary_cpus(void)
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xlp_boot_core0_siblings();
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/* now get other cores out of reset */
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xlp_enable_secondary_cores();
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xlp_enable_secondary_cores(&nlm_cpumask);
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}
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@ -57,8 +57,9 @@ struct psb_info nlm_prom_info;
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unsigned long nlm_common_ebase = 0x0;
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/* default to uniprocessor */
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uint32_t nlm_coremask = 1, nlm_cpumask = 1;
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uint32_t nlm_coremask = 1;
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int nlm_threads_per_core = 1;
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cpumask_t nlm_cpumask = CPU_MASK_CPU0;
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static void __init nlm_early_serial_setup(void)
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{
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@ -178,7 +179,7 @@ static void prom_add_memory(void)
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void __init prom_init(void)
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{
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int *argv, *envp; /* passed as 32 bit ptrs */
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int i, *argv, *envp; /* passed as 32 bit ptrs */
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struct psb_info *prom_infop;
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/* truncate to 32 bit and sign extend all args */
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@ -195,7 +196,10 @@ void __init prom_init(void)
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prom_add_memory();
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#ifdef CONFIG_SMP
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nlm_wakeup_secondary_cpus(nlm_prom_info.online_cpu_map);
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for (i = 0; i < 32; i++)
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if (nlm_prom_info.online_cpu_map & (1 << i))
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cpumask_set_cpu(i, &nlm_cpumask);
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nlm_wakeup_secondary_cpus();
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register_smp_ops(&nlm_smp_ops);
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#endif
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}
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@ -59,7 +59,7 @@ int __cpuinit xlr_wakeup_secondary_cpus(void)
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boot_cpu = hard_smp_processor_id();
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nlm_set_nmi_handler(nlm_rmiboot_preboot);
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for (i = 0; i < NR_CPUS; i++) {
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if (i == boot_cpu || (nlm_cpumask & (1u << i)) == 0)
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if (i == boot_cpu || !cpumask_test_cpu(i, &nlm_cpumask))
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continue;
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nlm_pic_send_ipi(nlm_pic_base, i, 1, 1); /* send NMI */
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}
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