ARM: dts: imx: Cleanup style around assignment operator
Use a space before and after assignment operator to have consistent style. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Коммит
2a44db1303
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@ -234,7 +234,7 @@
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compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
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"fsl,imx21-uart";
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reg = <0x02018000 0x4000>;
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interrupts =<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
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dma-names = "rx", "tx";
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clocks = <&clks IMX6SLL_CLK_UART4_IPG>,
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@ -801,7 +801,7 @@
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compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart",
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"fsl,imx21-uart";
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reg = <0x021f4000 0x4000>;
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interrupts =<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
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dma-names = "rx", "tx";
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clocks = <&clks IMX6SLL_CLK_UART5_IPG>,
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@ -926,8 +926,8 @@
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<&clks IMX6SX_CLK_ENET_PTP>;
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clock-names = "ipg", "ahb", "ptp",
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"enet_clk_ref", "enet_out";
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fsl,num-tx-queues=<3>;
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fsl,num-rx-queues=<3>;
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fsl,num-tx-queues = <3>;
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fsl,num-rx-queues = <3>;
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status = "disabled";
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};
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@ -69,7 +69,7 @@
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 =<&pinctrl_i2c1>;
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pinctrl-0 = <&pinctrl_i2c1>;
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clock-frequency = <100000>;
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status = "okay";
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@ -518,8 +518,8 @@
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<&clks IMX6UL_CLK_ENET2_REF_125M>;
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clock-names = "ipg", "ahb", "ptp",
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"enet_clk_ref", "enet_out";
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fsl,num-tx-queues=<1>;
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fsl,num-rx-queues=<1>;
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fsl,num-tx-queues = <1>;
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fsl,num-rx-queues = <1>;
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status = "disabled";
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};
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@ -853,8 +853,8 @@
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<&clks IMX6UL_CLK_ENET_REF>;
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clock-names = "ipg", "ahb", "ptp",
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"enet_clk_ref", "enet_out";
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fsl,num-tx-queues=<1>;
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fsl,num-rx-queues=<1>;
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fsl,num-tx-queues = <1>;
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fsl,num-rx-queues = <1>;
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status = "disabled";
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};
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@ -866,7 +866,7 @@
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<&clks IMX6UL_CLK_USDHC1>,
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<&clks IMX6UL_CLK_USDHC1>;
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clock-names = "ipg", "ahb", "per";
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fsl,tuning-step= <2>;
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fsl,tuning-step = <2>;
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fsl,tuning-start-tap = <20>;
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bus-width = <4>;
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status = "disabled";
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@ -881,7 +881,7 @@
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<&clks IMX6UL_CLK_USDHC2>;
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clock-names = "ipg", "ahb", "per";
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bus-width = <4>;
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fsl,tuning-step= <2>;
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fsl,tuning-step = <2>;
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fsl,tuning-start-tap = <20>;
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status = "disabled";
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};
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@ -147,8 +147,8 @@
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<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
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clock-names = "ipg", "ahb", "ptp",
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"enet_clk_ref", "enet_out";
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fsl,num-tx-queues=<3>;
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fsl,num-rx-queues=<3>;
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fsl,num-tx-queues = <3>;
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fsl,num-rx-queues = <3>;
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status = "disabled";
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};
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@ -151,7 +151,7 @@
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compatible = "fsl,imx7d-tempmon";
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interrupt-parent = <&gpc>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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fsl,tempmon =<&anatop>;
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fsl,tempmon = <&anatop>;
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nvmem-cells = <&tempmon_calib>,
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<&tempmon_temp_grade>;
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nvmem-cell-names = "calib", "temp_grade";
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@ -1184,8 +1184,8 @@
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<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
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clock-names = "ipg", "ahb", "ptp",
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"enet_clk_ref", "enet_out";
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fsl,num-tx-queues=<3>;
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fsl,num-rx-queues=<3>;
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fsl,num-tx-queues = <3>;
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fsl,num-rx-queues = <3>;
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status = "disabled";
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};
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};
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@ -229,12 +229,12 @@
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clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
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<&scg1 IMX7ULP_CLK_NIC1_DIV>,
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<&pcc2 IMX7ULP_CLK_USDHC0>;
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clock-names ="ipg", "ahb", "per";
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clock-names = "ipg", "ahb", "per";
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assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
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assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
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bus-width = <4>;
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fsl,tuning-start-tap = <20>;
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fsl,tuning-step= <2>;
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fsl,tuning-step = <2>;
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status = "disabled";
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};
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@ -245,12 +245,12 @@
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clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
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<&scg1 IMX7ULP_CLK_NIC1_DIV>,
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<&pcc2 IMX7ULP_CLK_USDHC1>;
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clock-names ="ipg", "ahb", "per";
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clock-names = "ipg", "ahb", "per";
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assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>;
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assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
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bus-width = <4>;
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fsl,tuning-start-tap = <20>;
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fsl,tuning-step= <2>;
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fsl,tuning-step = <2>;
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status = "disabled";
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};
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