ASoC: rsnd: add AUDIO_CLKOUT support
Renesas sound has AUDIO_CLKOUT (in Gen1/Gen2) AUDIO_CLKOUT1/2/3 (in Gen3) This patch support these patches as clock provider. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Kuninori Morimoto
Mark Brown
Родитель
248e88c2fb
Коммит
2a46db4a37
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@ -34,6 +34,9 @@ Required properties:
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see below for detail.
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- #sound-dai-cells : it must be 0 if your system is using single DAI
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it must be 1 if your system is using multi DAI
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- #clock-cells : it must be 0 if your system has audio_clkout
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it must be 1 if your system has audio_clkout0/1/2/3
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- clock-frequency : for all audio_clkout0/1/2/3
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SSI subnode properties:
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- interrupts : Should contain SSI interrupt for PIO transfer
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@ -7,6 +7,7 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/clk-provider.h>
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#include "rsnd.h"
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#define CLKA 0
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@ -15,6 +16,12 @@
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#define CLKI 3
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#define CLKMAX 4
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#define CLKOUT 0
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#define CLKOUT1 1
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#define CLKOUT2 2
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#define CLKOUT3 3
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#define CLKOUTMAX 4
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#define BRRx_MASK(x) (0x3FF & x)
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static struct rsnd_mod_ops adg_ops = {
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@ -23,6 +30,8 @@ static struct rsnd_mod_ops adg_ops = {
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struct rsnd_adg {
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struct clk *clk[CLKMAX];
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struct clk *clkout[CLKOUTMAX];
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struct clk_onecell_data onecell;
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struct rsnd_mod mod;
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int rbga_rate_for_441khz; /* RBGA */
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@ -34,6 +43,11 @@ struct rsnd_adg {
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(i < CLKMAX) && \
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((pos) = adg->clk[i]); \
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i++)
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#define for_each_rsnd_clkout(pos, adg, i) \
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for (i = 0; \
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(i < CLKOUTMAX) && \
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((pos) = adg->clkout[i]); \
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i++)
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#define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
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static u32 rsnd_adg_calculate_rbgx(unsigned long div)
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@ -416,14 +430,25 @@ static void rsnd_adg_get_clkin(struct rsnd_priv *priv,
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dev_dbg(dev, "clk %d : %p : %ld\n", i, clk, clk_get_rate(clk));
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}
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static void rsnd_adg_ssi_clk_init(struct rsnd_priv *priv, struct rsnd_adg *adg)
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static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
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struct rsnd_adg *adg)
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{
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struct clk *clk;
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struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
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struct device *dev = rsnd_priv_to_dev(priv);
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unsigned long rate, div;
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struct device_node *np = dev->of_node;
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u32 ckr, rbgx, rbga, rbgb;
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u32 rate, req_rate, div;
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uint32_t count = 0;
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unsigned long req_48kHz_rate, req_441kHz_rate;
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int i;
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const char *parent_clk_name = NULL;
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static const char * const clkout_name[] = {
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[CLKOUT] = "audio_clkout",
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[CLKOUT1] = "audio_clkout1",
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[CLKOUT2] = "audio_clkout2",
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[CLKOUT3] = "audio_clkout3",
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};
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int brg_table[] = {
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[CLKA] = 0x0,
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[CLKB] = 0x1,
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@ -431,6 +456,20 @@ static void rsnd_adg_ssi_clk_init(struct rsnd_priv *priv, struct rsnd_adg *adg)
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[CLKI] = 0x2,
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};
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of_property_read_u32(np, "#clock-cells", &count);
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/*
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* ADG supports BRRA/BRRB output only
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* this means all clkout0/1/2/3 will be same rate
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*/
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of_property_read_u32(np, "clock-frequency", &req_rate);
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req_48kHz_rate = 0;
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req_441kHz_rate = 0;
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if (0 == (req_rate % 44100))
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req_441kHz_rate = req_rate;
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if (0 == (req_rate % 48000))
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req_48kHz_rate = req_rate;
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/*
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* This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
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* have 44.1kHz or 48kHz base clocks for now.
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@ -454,22 +493,72 @@ static void rsnd_adg_ssi_clk_init(struct rsnd_priv *priv, struct rsnd_adg *adg)
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/* RBGA */
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if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) {
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div = 6;
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if (req_441kHz_rate)
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div = rate / req_441kHz_rate;
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rbgx = rsnd_adg_calculate_rbgx(div);
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if (BRRx_MASK(rbgx) == rbgx) {
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rbga = rbgx;
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adg->rbga_rate_for_441khz = rate / div;
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ckr |= brg_table[i] << 20;
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if (req_441kHz_rate)
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parent_clk_name = __clk_get_name(clk);
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}
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}
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/* RBGB */
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if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) {
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div = 6;
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if (req_48kHz_rate)
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div = rate / req_48kHz_rate;
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rbgx = rsnd_adg_calculate_rbgx(div);
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if (BRRx_MASK(rbgx) == rbgx) {
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rbgb = rbgx;
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adg->rbgb_rate_for_48khz = rate / div;
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ckr |= brg_table[i] << 16;
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if (req_48kHz_rate) {
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parent_clk_name = __clk_get_name(clk);
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ckr |= 0x80000000;
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}
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}
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}
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}
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/*
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* ADG supports BRRA/BRRB output only.
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* this means all clkout0/1/2/3 will be * same rate
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*/
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/*
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* for clkout
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*/
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if (!count) {
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clk = clk_register_fixed_rate(dev, clkout_name[i],
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parent_clk_name,
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(parent_clk_name) ?
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0 : CLK_IS_ROOT, req_rate);
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if (!IS_ERR(clk)) {
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adg->clkout[CLKOUT] = clk;
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of_clk_add_provider(np, of_clk_src_simple_get, clk);
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}
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}
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/*
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* for clkout0/1/2/3
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*/
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else {
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for (i = 0; i < CLKOUTMAX; i++) {
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clk = clk_register_fixed_rate(dev, clkout_name[i],
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parent_clk_name,
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(parent_clk_name) ?
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0 : CLK_IS_ROOT,
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req_rate);
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if (!IS_ERR(clk)) {
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adg->onecell.clks = adg->clkout;
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adg->onecell.clk_num = CLKOUTMAX;
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adg->clkout[i] = clk;
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of_clk_add_provider(np, of_clk_src_onecell_get,
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&adg->onecell);
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}
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}
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}
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@ -478,6 +567,8 @@ static void rsnd_adg_ssi_clk_init(struct rsnd_priv *priv, struct rsnd_adg *adg)
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rsnd_mod_write(adg_mod, BRRA, rbga);
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rsnd_mod_write(adg_mod, BRRB, rbgb);
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for_each_rsnd_clkout(clk, adg, i)
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dev_dbg(dev, "clkout %d : %p : %ld\n", i, clk, clk_get_rate(clk));
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dev_dbg(dev, "SSICKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n",
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ckr, rbga, rbgb);
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}
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@ -504,8 +595,7 @@ int rsnd_adg_probe(struct platform_device *pdev,
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adg->mod.priv = priv;
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rsnd_adg_get_clkin(priv, adg);
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rsnd_adg_ssi_clk_init(priv, adg);
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rsnd_adg_get_clkout(priv, adg);
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priv->adg = adg;
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