powerpc/mm: Split low level tlb invalidate for nohash processors
Currently, the various forms of low level TLB invalidations are all implemented in misc_32.S for 32-bit processors, in a fairly scary mess of #ifdef's and with interesting duplication such as a whole bunch of code for FSL _tlbie and _tlbia which are no longer used. This moves things around such that _tlbie is now defined in hash_low_32.S and is only used by the 32-bit hash code, and all nohash CPUs use the various _tlbil_* forms that are now moved to a new file, tlb_nohash_low.S. I moved all the definitions for that stuff out of include/asm/tlbflush.h as they are really internal mm stuff, into mm/mmu_decl.h The code should have no functional changes. I kept some variants inline for trivial forms on things like 40x and 8xx. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Benjamin Herrenschmidt
Paul Mackerras
Родитель
f048aace29
Коммит
2a4aca1144
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@ -33,17 +33,6 @@
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#define MMU_NO_CONTEXT ((unsigned int)-1)
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extern void _tlbil_all(void);
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extern void _tlbil_pid(unsigned int pid);
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extern void _tlbil_va(unsigned long address, unsigned int pid);
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extern void _tlbivax_bcast(unsigned long address, unsigned int pid);
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#if defined(CONFIG_40x) || defined(CONFIG_8xx)
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#define _tlbia() asm volatile ("tlbia; sync" : : : "memory")
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#else /* CONFIG_44x || CONFIG_FSL_BOOKE */
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extern void _tlbia(void);
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#endif
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extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end);
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extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
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@ -65,9 +54,6 @@ extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
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/*
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* TLB flushing for "classic" hash-MMU 32-bit CPUs, 6xx, 7xx, 7xxx
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*/
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extern void _tlbie(unsigned long address);
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extern void _tlbia(void);
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extern void flush_tlb_mm(struct mm_struct *mm);
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extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
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extern void flush_tlb_page_nohash(struct vm_area_struct *vma, unsigned long addr);
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@ -272,239 +272,6 @@ _GLOBAL(real_writeb)
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#endif /* CONFIG_40x */
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/*
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* Flush MMU TLB
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*/
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#ifndef CONFIG_FSL_BOOKE
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_GLOBAL(_tlbil_all)
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_GLOBAL(_tlbil_pid)
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#endif
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_GLOBAL(_tlbia)
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#if defined(CONFIG_40x)
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sync /* Flush to memory before changing mapping */
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tlbia
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isync /* Flush shadow TLB */
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#elif defined(CONFIG_44x)
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li r3,0
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sync
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/* Load high watermark */
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lis r4,tlb_44x_hwater@ha
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lwz r5,tlb_44x_hwater@l(r4)
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1: tlbwe r3,r3,PPC44x_TLB_PAGEID
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addi r3,r3,1
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cmpw 0,r3,r5
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ble 1b
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isync
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#elif defined(CONFIG_FSL_BOOKE)
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/* Invalidate all entries in TLB0 */
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li r3, 0x04
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tlbivax 0,3
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/* Invalidate all entries in TLB1 */
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li r3, 0x0c
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tlbivax 0,3
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msync
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#ifdef CONFIG_SMP
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tlbsync
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#endif /* CONFIG_SMP */
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#else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
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#if defined(CONFIG_SMP)
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rlwinm r8,r1,0,0,(31-THREAD_SHIFT)
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lwz r8,TI_CPU(r8)
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oris r8,r8,10
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mfmsr r10
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SYNC
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rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
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rlwinm r0,r0,0,28,26 /* clear DR */
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mtmsr r0
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SYNC_601
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isync
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lis r9,mmu_hash_lock@h
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ori r9,r9,mmu_hash_lock@l
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tophys(r9,r9)
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10: lwarx r7,0,r9
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cmpwi 0,r7,0
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bne- 10b
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stwcx. r8,0,r9
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bne- 10b
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sync
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tlbia
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sync
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TLBSYNC
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li r0,0
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stw r0,0(r9) /* clear mmu_hash_lock */
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mtmsr r10
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SYNC_601
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isync
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#else /* CONFIG_SMP */
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sync
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tlbia
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sync
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#endif /* CONFIG_SMP */
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#endif /* ! defined(CONFIG_40x) */
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blr
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/*
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* Flush MMU TLB for a particular address
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*/
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#ifndef CONFIG_FSL_BOOKE
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_GLOBAL(_tlbil_va)
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#endif
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_GLOBAL(_tlbie)
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#if defined(CONFIG_40x)
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/* We run the search with interrupts disabled because we have to change
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* the PID and I don't want to preempt when that happens.
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*/
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mfmsr r5
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mfspr r6,SPRN_PID
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wrteei 0
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mtspr SPRN_PID,r4
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tlbsx. r3, 0, r3
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mtspr SPRN_PID,r6
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wrtee r5
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bne 10f
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sync
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/* There are only 64 TLB entries, so r3 < 64, which means bit 25 is clear.
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* Since 25 is the V bit in the TLB_TAG, loading this value will invalidate
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* the TLB entry. */
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tlbwe r3, r3, TLB_TAG
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isync
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10:
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#elif defined(CONFIG_44x)
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mfspr r5,SPRN_MMUCR
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rlwimi r5,r4,0,24,31 /* Set TID */
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/* We have to run the search with interrupts disabled, even critical
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* and debug interrupts (in fact the only critical exceptions we have
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* are debug and machine check). Otherwise an interrupt which causes
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* a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */
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mfmsr r4
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lis r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha
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addi r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l
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andc r6,r4,r6
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mtmsr r6
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mtspr SPRN_MMUCR,r5
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tlbsx. r3, 0, r3
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mtmsr r4
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bne 10f
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sync
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/* There are only 64 TLB entries, so r3 < 64,
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* which means bit 22, is clear. Since 22 is
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* the V bit in the TLB_PAGEID, loading this
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* value will invalidate the TLB entry.
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*/
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tlbwe r3, r3, PPC44x_TLB_PAGEID
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isync
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10:
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#elif defined(CONFIG_FSL_BOOKE)
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rlwinm r4, r3, 0, 0, 19
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ori r5, r4, 0x08 /* TLBSEL = 1 */
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tlbivax 0, r4
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tlbivax 0, r5
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msync
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#if defined(CONFIG_SMP)
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tlbsync
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#endif /* CONFIG_SMP */
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#else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
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#if defined(CONFIG_SMP)
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rlwinm r8,r1,0,0,(31-THREAD_SHIFT)
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lwz r8,TI_CPU(r8)
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oris r8,r8,11
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mfmsr r10
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SYNC
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rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
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rlwinm r0,r0,0,28,26 /* clear DR */
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mtmsr r0
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SYNC_601
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isync
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lis r9,mmu_hash_lock@h
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ori r9,r9,mmu_hash_lock@l
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tophys(r9,r9)
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10: lwarx r7,0,r9
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cmpwi 0,r7,0
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bne- 10b
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stwcx. r8,0,r9
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bne- 10b
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eieio
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tlbie r3
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sync
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TLBSYNC
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li r0,0
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stw r0,0(r9) /* clear mmu_hash_lock */
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mtmsr r10
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SYNC_601
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isync
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#else /* CONFIG_SMP */
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tlbie r3
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sync
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#endif /* CONFIG_SMP */
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#endif /* ! CONFIG_40x */
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blr
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#if defined(CONFIG_FSL_BOOKE)
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/*
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* Flush MMU TLB, but only on the local processor (no broadcast)
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*/
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_GLOBAL(_tlbil_all)
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#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
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MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
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li r3,(MMUCSR0_TLBFI)@l
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mtspr SPRN_MMUCSR0, r3
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1:
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mfspr r3,SPRN_MMUCSR0
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andi. r3,r3,MMUCSR0_TLBFI@l
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bne 1b
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blr
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/*
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* Flush MMU TLB for a particular process id, but only on the local processor
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* (no broadcast)
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*/
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_GLOBAL(_tlbil_pid)
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/* we currently do an invalidate all since we don't have per pid invalidate */
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li r3,(MMUCSR0_TLBFI)@l
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mtspr SPRN_MMUCSR0, r3
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1:
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mfspr r3,SPRN_MMUCSR0
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andi. r3,r3,MMUCSR0_TLBFI@l
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bne 1b
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msync
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isync
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blr
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/*
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* Flush MMU TLB for a particular address, but only on the local processor
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* (no broadcast)
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*/
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_GLOBAL(_tlbil_va)
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mfmsr r10
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wrteei 0
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slwi r4,r4,16
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mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
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tlbsx 0,r3
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mfspr r4,SPRN_MAS1 /* check valid */
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andis. r3,r4,MAS1_VALID@h
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beq 1f
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rlwinm r4,r4,0,1,31
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mtspr SPRN_MAS1,r4
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tlbwe
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msync
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isync
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1: wrtee r10
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blr
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#endif /* CONFIG_FSL_BOOKE */
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/*
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* Nobody implements this yet
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*/
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_GLOBAL(_tlbivax_bcast)
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1: trap
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EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0;
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blr
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/*
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* Flush instruction cache.
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@ -330,7 +330,7 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
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/* XXX It would be nice to differentiate between heavyweight exit and
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* sched_out here, since we could avoid the TLB flush for heavyweight
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* exits. */
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_tlbia();
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_tlbil_all();
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}
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int kvm_arch_vcpu_ioctl_debug_guest(struct kvm_vcpu *vcpu,
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@ -9,7 +9,8 @@ endif
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obj-y := fault.o mem.o pgtable.o \
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init_$(CONFIG_WORD_SIZE).o \
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pgtable_$(CONFIG_WORD_SIZE).o
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obj-$(CONFIG_PPC_MMU_NOHASH) += mmu_context_nohash.o tlb_nohash.o
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obj-$(CONFIG_PPC_MMU_NOHASH) += mmu_context_nohash.o tlb_nohash.o \
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tlb_nohash_low.o
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hash-$(CONFIG_PPC_NATIVE) := hash_native_64.o
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obj-$(CONFIG_PPC64) += hash_utils_64.o \
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slb_low.o slb.o stab.o \
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@ -633,3 +633,79 @@ _GLOBAL(flush_hash_patch_B)
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SYNC_601
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isync
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blr
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/*
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* Flush an entry from the TLB
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*/
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_GLOBAL(_tlbie)
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#ifdef CONFIG_SMP
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rlwinm r8,r1,0,0,(31-THREAD_SHIFT)
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lwz r8,TI_CPU(r8)
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oris r8,r8,11
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mfmsr r10
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SYNC
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rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
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rlwinm r0,r0,0,28,26 /* clear DR */
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mtmsr r0
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SYNC_601
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isync
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lis r9,mmu_hash_lock@h
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ori r9,r9,mmu_hash_lock@l
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tophys(r9,r9)
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10: lwarx r7,0,r9
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cmpwi 0,r7,0
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bne- 10b
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stwcx. r8,0,r9
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bne- 10b
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eieio
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tlbie r3
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sync
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TLBSYNC
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li r0,0
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stw r0,0(r9) /* clear mmu_hash_lock */
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mtmsr r10
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SYNC_601
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isync
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#else /* CONFIG_SMP */
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tlbie r3
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sync
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#endif /* CONFIG_SMP */
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blr
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/*
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* Flush the entire TLB. 603/603e only
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*/
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_GLOBAL(_tlbia)
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#if defined(CONFIG_SMP)
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rlwinm r8,r1,0,0,(31-THREAD_SHIFT)
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lwz r8,TI_CPU(r8)
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oris r8,r8,10
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mfmsr r10
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SYNC
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rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
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rlwinm r0,r0,0,28,26 /* clear DR */
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mtmsr r0
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SYNC_601
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isync
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lis r9,mmu_hash_lock@h
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ori r9,r9,mmu_hash_lock@l
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tophys(r9,r9)
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10: lwarx r7,0,r9
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cmpwi 0,r7,0
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bne- 10b
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stwcx. r8,0,r9
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bne- 10b
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sync
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tlbia
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sync
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TLBSYNC
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li r0,0
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stw r0,0(r9) /* clear mmu_hash_lock */
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mtmsr r10
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SYNC_601
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isync
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#else /* CONFIG_SMP */
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sync
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tlbia
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sync
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#endif /* CONFIG_SMP */
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@ -22,10 +22,58 @@
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#include <asm/tlbflush.h>
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#include <asm/mmu.h>
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#ifdef CONFIG_PPC_MMU_NOHASH
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/*
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* On 40x and 8xx, we directly inline tlbia and tlbivax
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*/
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#if defined(CONFIG_40x) || defined(CONFIG_8xx)
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static inline void _tlbil_all(void)
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{
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asm volatile ("sync; tlbia; isync" : : : "memory")
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}
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static inline void _tlbil_pid(unsigned int pid)
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{
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asm volatile ("sync; tlbia; isync" : : : "memory")
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}
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#else /* CONFIG_40x || CONFIG_8xx */
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extern void _tlbil_all(void);
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extern void _tlbil_pid(unsigned int pid);
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#endif /* !(CONFIG_40x || CONFIG_8xx) */
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/*
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* On 8xx, we directly inline tlbie, on others, it's extern
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*/
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#ifdef CONFIG_8xx
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static inline void _tlbil_va(unsigned long address, unsigned int pid)
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{
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asm volatile ("tlbie %0; sync" : : "r" (address) : "memory")
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}
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#else /* CONFIG_8xx */
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extern void _tlbil_va(unsigned long address, unsigned int pid);
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#endif /* CONIFG_8xx */
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/*
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* As of today, we don't support tlbivax broadcast on any
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* implementation. When that becomes the case, this will be
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* an extern.
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*/
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static inline void _tlbivax_bcast(unsigned long address, unsigned int pid)
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{
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BUG();
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}
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#else /* CONFIG_PPC_MMU_NOHASH */
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extern void hash_preload(struct mm_struct *mm, unsigned long ea,
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unsigned long access, unsigned long trap);
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extern void _tlbie(unsigned long address);
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extern void _tlbia(void);
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#endif /* CONFIG_PPC_MMU_NOHASH */
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#ifdef CONFIG_PPC32
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extern void mapin_ram(void);
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extern int map_page(unsigned long va, phys_addr_t pa, int flags);
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|
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|
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@ -0,0 +1,165 @@
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/*
|
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* This file contains low-level functions for performing various
|
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* types of TLB invalidations on various processors with no hash
|
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* table.
|
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*
|
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* This file implements the following functions for all no-hash
|
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* processors. Some aren't implemented for some variants. Some
|
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* are inline in tlbflush.h
|
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*
|
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* - tlbil_va
|
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* - tlbil_pid
|
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* - tlbil_all
|
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* - tlbivax_bcast (not yet)
|
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*
|
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* Code mostly moved over from misc_32.S
|
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*
|
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
|
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*
|
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* Partially rewritten by Cort Dougan (cort@cs.nmt.edu)
|
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* Paul Mackerras, Kumar Gala and Benjamin Herrenschmidt.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <asm/reg.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/cputable.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/ppc_asm.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
#if defined(CONFIG_40x)
|
||||
|
||||
/*
|
||||
* 40x implementation needs only tlbil_va
|
||||
*/
|
||||
_GLOBAL(_tlbil_va)
|
||||
/* We run the search with interrupts disabled because we have to change
|
||||
* the PID and I don't want to preempt when that happens.
|
||||
*/
|
||||
mfmsr r5
|
||||
mfspr r6,SPRN_PID
|
||||
wrteei 0
|
||||
mtspr SPRN_PID,r4
|
||||
tlbsx. r3, 0, r3
|
||||
mtspr SPRN_PID,r6
|
||||
wrtee r5
|
||||
bne 1f
|
||||
sync
|
||||
/* There are only 64 TLB entries, so r3 < 64, which means bit 25 is
|
||||
* clear. Since 25 is the V bit in the TLB_TAG, loading this value
|
||||
* will invalidate the TLB entry. */
|
||||
tlbwe r3, r3, TLB_TAG
|
||||
isync
|
||||
1: blr
|
||||
|
||||
#elif defined(CONFIG_8xx)
|
||||
|
||||
/*
|
||||
* Nothing to do for 8xx, everything is inline
|
||||
*/
|
||||
|
||||
#elif defined(CONFIG_44x)
|
||||
|
||||
/*
|
||||
* 440 implementation uses tlbsx/we for tlbil_va and a full sweep
|
||||
* of the TLB for everything else.
|
||||
*/
|
||||
_GLOBAL(_tlbil_va)
|
||||
mfspr r5,SPRN_MMUCR
|
||||
rlwimi r5,r4,0,24,31 /* Set TID */
|
||||
|
||||
/* We have to run the search with interrupts disabled, even critical
|
||||
* and debug interrupts (in fact the only critical exceptions we have
|
||||
* are debug and machine check). Otherwise an interrupt which causes
|
||||
* a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */
|
||||
mfmsr r4
|
||||
lis r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha
|
||||
addi r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l
|
||||
andc r6,r4,r6
|
||||
mtmsr r6
|
||||
mtspr SPRN_MMUCR,r5
|
||||
tlbsx. r3, 0, r3
|
||||
mtmsr r4
|
||||
bne 1f
|
||||
sync
|
||||
/* There are only 64 TLB entries, so r3 < 64,
|
||||
* which means bit 22, is clear. Since 22 is
|
||||
* the V bit in the TLB_PAGEID, loading this
|
||||
* value will invalidate the TLB entry.
|
||||
*/
|
||||
tlbwe r3, r3, PPC44x_TLB_PAGEID
|
||||
isync
|
||||
1: blr
|
||||
|
||||
_GLOBAL(_tlbil_all)
|
||||
_GLOBAL(_tlbil_pid)
|
||||
li r3,0
|
||||
sync
|
||||
|
||||
/* Load high watermark */
|
||||
lis r4,tlb_44x_hwater@ha
|
||||
lwz r5,tlb_44x_hwater@l(r4)
|
||||
|
||||
1: tlbwe r3,r3,PPC44x_TLB_PAGEID
|
||||
addi r3,r3,1
|
||||
cmpw 0,r3,r5
|
||||
ble 1b
|
||||
|
||||
isync
|
||||
blr
|
||||
|
||||
#elif defined(CONFIG_FSL_BOOKE)
|
||||
/*
|
||||
* FSL BookE implementations. Currently _pid and _all are the
|
||||
* same. This will change when tlbilx is actually supported and
|
||||
* performs invalidate-by-PID. This change will be driven by
|
||||
* mmu_features conditional
|
||||
*/
|
||||
|
||||
/*
|
||||
* Flush MMU TLB on the local processor
|
||||
*/
|
||||
_GLOBAL(_tlbil_pid)
|
||||
_GLOBAL(_tlbil_all)
|
||||
#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
|
||||
MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
|
||||
li r3,(MMUCSR0_TLBFI)@l
|
||||
mtspr SPRN_MMUCSR0, r3
|
||||
1:
|
||||
mfspr r3,SPRN_MMUCSR0
|
||||
andi. r3,r3,MMUCSR0_TLBFI@l
|
||||
bne 1b
|
||||
msync
|
||||
isync
|
||||
blr
|
||||
|
||||
/*
|
||||
* Flush MMU TLB for a particular address, but only on the local processor
|
||||
* (no broadcast)
|
||||
*/
|
||||
_GLOBAL(_tlbil_va)
|
||||
mfmsr r10
|
||||
wrteei 0
|
||||
slwi r4,r4,16
|
||||
mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
|
||||
tlbsx 0,r3
|
||||
mfspr r4,SPRN_MAS1 /* check valid */
|
||||
andis. r3,r4,MAS1_VALID@h
|
||||
beq 1f
|
||||
rlwinm r4,r4,0,1,31
|
||||
mtspr SPRN_MAS1,r4
|
||||
tlbwe
|
||||
msync
|
||||
isync
|
||||
1: wrtee r10
|
||||
blr
|
||||
#elif
|
||||
#error Unsupported processor type !
|
||||
#endif
|
||||
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