[POWERPC] 4xx: Add PPC4xx L2-cache support (440GX)
This patch adds support for the 256k L2 cache found on some IBM/AMCC 4xx PPC's. It introduces a common 4xx SoC file (sysdev/ppc4xx_soc.c) which currently "only" adds the L2 cache init code. Other common 4xx stuff can be added later here. The L2 cache handling code is a copy of Eugene's code in arch/ppc with small modifications. Tested on AMCC Taishan 440GX. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
This commit is contained in:
Stefan Roese
Josh Boyer
Родитель
145692a734
Коммит
2a7069190e
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@ -501,6 +501,9 @@ config FSL_PCI
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bool
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select PPC_INDIRECT_PCI
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config 4xx_SOC
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bool
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# Yes MCA RS/6000s exist but Linux-PPC does not currently support any
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config MCA
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bool
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@ -129,6 +129,7 @@ config 440GP
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config 440GX
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bool
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select 4xx_SOC
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select IBM_NEW_EMAC_EMAC4
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select IBM_NEW_EMAC_RGMII
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select IBM_NEW_EMAC_ZMII #test only
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@ -27,6 +27,7 @@ obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o
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obj-$(CONFIG_PPC_I8259) += i8259.o
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obj-$(CONFIG_IPIC) += ipic.o
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obj-$(CONFIG_4xx) += uic.o
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obj-$(CONFIG_4xx_SOC) += ppc4xx_soc.o
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obj-$(CONFIG_XILINX_VIRTEX) += xilinx_intc.o
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obj-$(CONFIG_OF_RTC) += of_rtc.o
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ifeq ($(CONFIG_PCI),y)
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@ -0,0 +1,189 @@
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/*
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* IBM/AMCC PPC4xx SoC setup code
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*
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* Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
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*
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* L2 cache routines cloned from arch/ppc/syslib/ibm440gx_common.c which is:
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* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
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* Copyright (c) 2003 - 2006 Zultys Technologies
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/of_platform.h>
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#include <asm/dcr.h>
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#include <asm/dcr-regs.h>
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static u32 dcrbase_l2c;
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/*
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* L2-cache
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*/
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/* Issue L2C diagnostic command */
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static inline u32 l2c_diag(u32 addr)
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{
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mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, addr);
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mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_DIAG);
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while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC))
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;
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return mfdcr(dcrbase_l2c + DCRN_L2C0_DATA);
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}
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static irqreturn_t l2c_error_handler(int irq, void *dev)
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{
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u32 sr = mfdcr(dcrbase_l2c + DCRN_L2C0_SR);
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if (sr & L2C_SR_CPE) {
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/* Read cache trapped address */
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u32 addr = l2c_diag(0x42000000);
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printk(KERN_EMERG "L2C: Cache Parity Error, addr[16:26] = 0x%08x\n",
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addr);
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}
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if (sr & L2C_SR_TPE) {
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/* Read tag trapped address */
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u32 addr = l2c_diag(0x82000000) >> 16;
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printk(KERN_EMERG "L2C: Tag Parity Error, addr[16:26] = 0x%08x\n",
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addr);
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}
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/* Clear parity errors */
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if (sr & (L2C_SR_CPE | L2C_SR_TPE)){
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mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0);
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mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
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} else {
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printk(KERN_EMERG "L2C: LRU error\n");
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}
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return IRQ_HANDLED;
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}
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static int __init ppc4xx_l2c_probe(void)
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{
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struct device_node *np;
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u32 r;
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unsigned long flags;
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int irq;
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const u32 *dcrreg;
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u32 dcrbase_isram;
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int len;
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const u32 *prop;
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u32 l2_size;
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np = of_find_compatible_node(NULL, NULL, "ibm,l2-cache");
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if (!np)
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return 0;
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/* Get l2 cache size */
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prop = of_get_property(np, "cache-size", NULL);
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if (prop == NULL) {
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printk(KERN_ERR "%s: Can't get cache-size!\n", np->full_name);
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of_node_put(np);
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return -ENODEV;
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}
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l2_size = prop[0];
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/* Map DCRs */
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dcrreg = of_get_property(np, "dcr-reg", &len);
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if (!dcrreg || (len != 4 * sizeof(u32))) {
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printk(KERN_ERR "%s: Can't get DCR register base !",
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np->full_name);
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of_node_put(np);
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return -ENODEV;
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}
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dcrbase_isram = dcrreg[0];
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dcrbase_l2c = dcrreg[2];
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/* Get and map irq number from device tree */
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irq = irq_of_parse_and_map(np, 0);
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if (irq == NO_IRQ) {
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printk(KERN_ERR "irq_of_parse_and_map failed\n");
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of_node_put(np);
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return -ENODEV;
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}
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/* Install error handler */
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if (request_irq(irq, l2c_error_handler, IRQF_DISABLED, "L2C", 0) < 0) {
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printk(KERN_ERR "Cannot install L2C error handler"
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", cache is not enabled\n");
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of_node_put(np);
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return -ENODEV;
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}
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local_irq_save(flags);
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asm volatile ("sync" ::: "memory");
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/* Disable SRAM */
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mtdcr(dcrbase_isram + DCRN_SRAM0_DPC,
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mfdcr(dcrbase_isram + DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE);
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mtdcr(dcrbase_isram + DCRN_SRAM0_SB0CR,
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mfdcr(dcrbase_isram + DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK);
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mtdcr(dcrbase_isram + DCRN_SRAM0_SB1CR,
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mfdcr(dcrbase_isram + DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK);
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mtdcr(dcrbase_isram + DCRN_SRAM0_SB2CR,
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mfdcr(dcrbase_isram + DCRN_SRAM0_SB2CR) & ~SRAM_SBCR_BU_MASK);
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mtdcr(dcrbase_isram + DCRN_SRAM0_SB3CR,
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mfdcr(dcrbase_isram + DCRN_SRAM0_SB3CR) & ~SRAM_SBCR_BU_MASK);
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/* Enable L2_MODE without ICU/DCU */
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r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG) &
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~(L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_SS_MASK);
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r |= L2C_CFG_L2M | L2C_CFG_SS_256;
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mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r);
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mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0);
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/* Hardware Clear Command */
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mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_HCC);
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while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC))
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;
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/* Clear Cache Parity and Tag Errors */
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mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
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/* Enable 64G snoop region starting at 0 */
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r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP0) &
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~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK);
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r |= L2C_SNP_SSR_32G | L2C_SNP_ESR;
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mtdcr(dcrbase_l2c + DCRN_L2C0_SNP0, r);
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r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP1) &
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~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK);
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r |= 0x80000000 | L2C_SNP_SSR_32G | L2C_SNP_ESR;
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mtdcr(dcrbase_l2c + DCRN_L2C0_SNP1, r);
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asm volatile ("sync" ::: "memory");
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/* Enable ICU/DCU ports */
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r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG);
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r &= ~(L2C_CFG_DCW_MASK | L2C_CFG_PMUX_MASK | L2C_CFG_PMIM
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| L2C_CFG_TPEI | L2C_CFG_CPEI | L2C_CFG_NAM | L2C_CFG_NBRM);
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r |= L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_TPC | L2C_CFG_CPC | L2C_CFG_FRAN
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| L2C_CFG_CPIM | L2C_CFG_TPIM | L2C_CFG_LIM | L2C_CFG_SMCM;
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/* Check for 460EX/GT special handling */
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if (of_device_is_compatible(np, "ibm,l2-cache-460ex"))
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r |= L2C_CFG_RDBW;
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mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r);
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asm volatile ("sync; isync" ::: "memory");
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local_irq_restore(flags);
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printk(KERN_INFO "%dk L2-cache enabled\n", l2_size >> 10);
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of_node_put(np);
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return 0;
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}
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arch_initcall(ppc4xx_l2c_probe);
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@ -68,4 +68,82 @@
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#define SDR0_UART3 0x0123
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#define SDR0_CUST0 0x4000
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/*
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* All those DCR register addresses are offsets from the base address
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* for the SRAM0 controller (e.g. 0x20 on 440GX). The base address is
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* excluded here and configured in the device tree.
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*/
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#define DCRN_SRAM0_SB0CR 0x00
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#define DCRN_SRAM0_SB1CR 0x01
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#define DCRN_SRAM0_SB2CR 0x02
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#define DCRN_SRAM0_SB3CR 0x03
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#define SRAM_SBCR_BU_MASK 0x00000180
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#define SRAM_SBCR_BS_64KB 0x00000800
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#define SRAM_SBCR_BU_RO 0x00000080
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#define SRAM_SBCR_BU_RW 0x00000180
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#define DCRN_SRAM0_BEAR 0x04
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#define DCRN_SRAM0_BESR0 0x05
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#define DCRN_SRAM0_BESR1 0x06
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#define DCRN_SRAM0_PMEG 0x07
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#define DCRN_SRAM0_CID 0x08
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#define DCRN_SRAM0_REVID 0x09
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#define DCRN_SRAM0_DPC 0x0a
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#define SRAM_DPC_ENABLE 0x80000000
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/*
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* All those DCR register addresses are offsets from the base address
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* for the SRAM0 controller (e.g. 0x30 on 440GX). The base address is
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* excluded here and configured in the device tree.
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*/
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#define DCRN_L2C0_CFG 0x00
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#define L2C_CFG_L2M 0x80000000
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#define L2C_CFG_ICU 0x40000000
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#define L2C_CFG_DCU 0x20000000
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#define L2C_CFG_DCW_MASK 0x1e000000
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#define L2C_CFG_TPC 0x01000000
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#define L2C_CFG_CPC 0x00800000
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#define L2C_CFG_FRAN 0x00200000
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#define L2C_CFG_SS_MASK 0x00180000
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#define L2C_CFG_SS_256 0x00000000
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#define L2C_CFG_CPIM 0x00040000
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#define L2C_CFG_TPIM 0x00020000
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#define L2C_CFG_LIM 0x00010000
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#define L2C_CFG_PMUX_MASK 0x00007000
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#define L2C_CFG_PMUX_SNP 0x00000000
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#define L2C_CFG_PMUX_IF 0x00001000
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#define L2C_CFG_PMUX_DF 0x00002000
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#define L2C_CFG_PMUX_DS 0x00003000
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#define L2C_CFG_PMIM 0x00000800
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#define L2C_CFG_TPEI 0x00000400
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#define L2C_CFG_CPEI 0x00000200
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#define L2C_CFG_NAM 0x00000100
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#define L2C_CFG_SMCM 0x00000080
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#define L2C_CFG_NBRM 0x00000040
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#define L2C_CFG_RDBW 0x00000008 /* only 460EX/GT */
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#define DCRN_L2C0_CMD 0x01
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#define L2C_CMD_CLR 0x80000000
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#define L2C_CMD_DIAG 0x40000000
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#define L2C_CMD_INV 0x20000000
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#define L2C_CMD_CCP 0x10000000
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#define L2C_CMD_CTE 0x08000000
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#define L2C_CMD_STRC 0x04000000
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#define L2C_CMD_STPC 0x02000000
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#define L2C_CMD_RPMC 0x01000000
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#define L2C_CMD_HCC 0x00800000
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#define DCRN_L2C0_ADDR 0x02
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#define DCRN_L2C0_DATA 0x03
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#define DCRN_L2C0_SR 0x04
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#define L2C_SR_CC 0x80000000
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#define L2C_SR_CPE 0x40000000
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#define L2C_SR_TPE 0x20000000
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#define L2C_SR_LRU 0x10000000
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#define L2C_SR_PCS 0x08000000
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#define DCRN_L2C0_REVID 0x05
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#define DCRN_L2C0_SNP0 0x06
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#define DCRN_L2C0_SNP1 0x07
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#define L2C_SNP_BA_MASK 0xffff0000
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#define L2C_SNP_SSR_MASK 0x0000f000
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#define L2C_SNP_SSR_32G 0x0000f000
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#define L2C_SNP_ESR 0x00000800
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#endif /* __DCR_REGS_H__ */
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