gpu: host1x: Disassemble more instructions
The disassembler for debug dumps was missing some newer host1x opcodes. Add disassembly support for these. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -30,6 +30,13 @@ enum {
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HOST1X_OPCODE_IMM = 0x04,
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HOST1X_OPCODE_RESTART = 0x05,
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HOST1X_OPCODE_GATHER = 0x06,
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HOST1X_OPCODE_SETSTRMID = 0x07,
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HOST1X_OPCODE_SETAPPID = 0x08,
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HOST1X_OPCODE_SETPYLD = 0x09,
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HOST1X_OPCODE_INCR_W = 0x0a,
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HOST1X_OPCODE_NONINCR_W = 0x0b,
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HOST1X_OPCODE_GATHER_W = 0x0c,
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HOST1X_OPCODE_RESTART_W = 0x0d,
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HOST1X_OPCODE_EXTEND = 0x0e,
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};
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@ -38,11 +45,16 @@ enum {
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HOST1X_OPCODE_EXTEND_RELEASE_MLOCK = 0x01,
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};
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static unsigned int show_channel_command(struct output *o, u32 val)
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{
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unsigned int mask, subop, num;
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#define INVALID_PAYLOAD 0xffffffff
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switch (val >> 28) {
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static unsigned int show_channel_command(struct output *o, u32 val,
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u32 *payload)
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{
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unsigned int mask, subop, num, opcode;
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opcode = val >> 28;
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switch (opcode) {
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case HOST1X_OPCODE_SETCLASS:
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mask = val & 0x3f;
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if (mask) {
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@ -97,6 +109,44 @@ static unsigned int show_channel_command(struct output *o, u32 val)
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val >> 14 & 0x1, val & 0x3fff);
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return 1;
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#if HOST1X_HW >= 6
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case HOST1X_OPCODE_SETSTRMID:
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host1x_debug_cont(o, "SETSTRMID(offset=%06x)\n",
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val & 0x3fffff);
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return 0;
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case HOST1X_OPCODE_SETAPPID:
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host1x_debug_cont(o, "SETAPPID(appid=%02x)\n", val & 0xff);
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return 0;
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case HOST1X_OPCODE_SETPYLD:
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*payload = val & 0xffff;
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host1x_debug_cont(o, "SETPYLD(data=%04x)\n", *payload);
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return 0;
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case HOST1X_OPCODE_INCR_W:
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case HOST1X_OPCODE_NONINCR_W:
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host1x_debug_cont(o, "%s(offset=%06x, ",
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opcode == HOST1X_OPCODE_INCR_W ?
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"INCR_W" : "NONINCR_W",
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val & 0x3fffff);
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if (*payload == 0) {
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host1x_debug_cont(o, "[])\n");
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return 0;
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} else if (*payload == INVALID_PAYLOAD) {
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host1x_debug_cont(o, "unknown)\n");
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return 0;
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} else {
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host1x_debug_cont(o, "[");
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return *payload;
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}
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case HOST1X_OPCODE_GATHER_W:
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host1x_debug_cont(o, "GATHER_W(count=%04x, addr=[",
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val & 0x3fff);
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return 2;
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#endif
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case HOST1X_OPCODE_EXTEND:
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subop = val >> 24 & 0xf;
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if (subop == HOST1X_OPCODE_EXTEND_ACQUIRE_MLOCK)
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@ -122,6 +172,7 @@ static void show_gather(struct output *o, phys_addr_t phys_addr,
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/* Map dmaget cursor to corresponding mem handle */
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u32 offset = phys_addr - pin_addr;
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unsigned int data_count = 0, i;
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u32 payload = INVALID_PAYLOAD;
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/*
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* Sometimes we're given different hardware address to the same
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@ -139,7 +190,7 @@ static void show_gather(struct output *o, phys_addr_t phys_addr,
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if (!data_count) {
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host1x_debug_output(o, "%08x: %08x: ", addr, val);
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data_count = show_channel_command(o, val);
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data_count = show_channel_command(o, val, &payload);
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} else {
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host1x_debug_cont(o, "%08x%s", val,
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data_count > 1 ? ", " : "])\n");
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@ -112,7 +112,7 @@ static void host1x_debug_show_channel_fifo(struct host1x *host,
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if (!data_count) {
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host1x_debug_output(o, "%08x: ", val);
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data_count = show_channel_command(o, val);
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data_count = show_channel_command(o, val, NULL);
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} else {
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host1x_debug_cont(o, "%08x%s", val,
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data_count > 1 ? ", " : "])\n");
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@ -63,6 +63,7 @@ static void host1x_debug_show_channel_fifo(struct host1x *host,
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struct output *o)
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{
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u32 val, rd_ptr, wr_ptr, start, end;
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u32 payload = INVALID_PAYLOAD;
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unsigned int data_count = 0;
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host1x_debug_output(o, "%u: fifo:\n", ch->id);
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@ -107,7 +108,7 @@ static void host1x_debug_show_channel_fifo(struct host1x *host,
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if (!data_count) {
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host1x_debug_output(o, "%03x 0x%08x: ",
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rd_ptr - start, val);
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data_count = show_channel_command(o, val);
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data_count = show_channel_command(o, val, &payload);
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} else {
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host1x_debug_cont(o, "%08x%s", val,
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data_count > 1 ? ", " : "])\n");
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